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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [simulation/] [modelsim/] [spw_fifo_ulight.vo] - Rev 32
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// Copyright (C) 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition"
// DATE "08/24/2017 22:42:12"
//
// Device: Altera 5CSEMA4U23C6 Package UFBGA672
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//
`timescale 1 ps/ 1 ps
module SPW_ULIGHT_FIFO (
\dout_a(n) ,
\sout_a(n) ,
\din_a(n) ,
\sin_a(n) ,
FPGA_CLK1_50,
KEY,
din_a,
sin_a,
dout_a,
sout_a,
LED);
output \dout_a(n) ;
output \sout_a(n) ;
input \din_a(n) ;
input \sin_a(n) ;
input FPGA_CLK1_50;
input [1:0] KEY;
input din_a;
input sin_a;
output dout_a;
output sout_a;
output [7:0] LED;
// Design Ports Information
// LED[5] => Location: PIN_AE26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// LED[7] => Location: PIN_AA23, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// dout_a => Location: PIN_AG28, I/O Standard: LVDS, Current Strength: Default
// sout_a => Location: PIN_AF20, I/O Standard: LVDS, Current Strength: Default
// LED[0] => Location: PIN_W15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// LED[1] => Location: PIN_AA24, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// LED[2] => Location: PIN_V16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// LED[3] => Location: PIN_V15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// LED[4] => Location: PIN_AF26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// KEY[0] => Location: PIN_AH17, I/O Standard: 3.3-V LVTTL, Current Strength: Default
// LED[6] => Location: PIN_Y16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
// FPGA_CLK1_50 => Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
// KEY[1] => Location: PIN_AH16, I/O Standard: 3.3-V LVTTL, Current Strength: Default
// din_a => Location: PIN_Y15, I/O Standard: LVDS, Current Strength: Default
// sin_a => Location: PIN_AE20, I/O Standard: LVDS, Current Strength: Default
// dout_a(n) => Location: PIN_AH27, I/O Standard: LVDS, Current Strength: Default
// sout_a(n) => Location: PIN_AG20, I/O Standard: LVDS, Current Strength: Default
// din_a(n) => Location: PIN_AA15, I/O Standard: LVDS, Current Strength: Default
// sin_a(n) => Location: PIN_AD20, I/O Standard: LVDS, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ;
wire \u0|hps_0|fpga_interfaces|tpiu~trace_data ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 ;
wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 ;
wire \u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ;
wire \u0|hps_0|fpga_interfaces|fpga2hps~arready ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 ;
wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 ;
wire \u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ;
wire \KEY[0]~input_o ;
wire \FPGA_CLK1_50~input_o ;
wire \FPGA_CLK1_50~inputCLKENA0_outclk ;
wire \KEY[1]~input_o ;
wire \db_system_spwulight_b|PB_down~0_combout ;
wire \db_system_spwulight_b|Add0~61_sumout ;
wire \db_system_spwulight_b|counter~16_combout ;
wire \db_system_spwulight_b|LessThan0~0_combout ;
wire \db_system_spwulight_b|LessThan0~1_combout ;
wire \db_system_spwulight_b|counter[0]~1_combout ;
wire \db_system_spwulight_b|Add0~62 ;
wire \db_system_spwulight_b|Add0~57_sumout ;
wire \db_system_spwulight_b|counter~15_combout ;
wire \db_system_spwulight_b|Add0~58 ;
wire \db_system_spwulight_b|Add0~53_sumout ;
wire \db_system_spwulight_b|counter~14_combout ;
wire \db_system_spwulight_b|Add0~54 ;
wire \db_system_spwulight_b|Add0~49_sumout ;
wire \db_system_spwulight_b|counter~13_combout ;
wire \db_system_spwulight_b|Add0~50 ;
wire \db_system_spwulight_b|Add0~37_sumout ;
wire \db_system_spwulight_b|counter~10_combout ;
wire \db_system_spwulight_b|Add0~38 ;
wire \db_system_spwulight_b|Add0~41_sumout ;
wire \db_system_spwulight_b|counter~11_combout ;
wire \db_system_spwulight_b|Add0~42 ;
wire \db_system_spwulight_b|Add0~45_sumout ;
wire \db_system_spwulight_b|counter~12_combout ;
wire \db_system_spwulight_b|Add0~46 ;
wire \db_system_spwulight_b|Add0~29_sumout ;
wire \db_system_spwulight_b|counter~8_combout ;
wire \db_system_spwulight_b|Add0~30 ;
wire \db_system_spwulight_b|Add0~33_sumout ;
wire \db_system_spwulight_b|counter~9_combout ;
wire \db_system_spwulight_b|Add0~34 ;
wire \db_system_spwulight_b|Add0~9_sumout ;
wire \db_system_spwulight_b|counter~3_combout ;
wire \db_system_spwulight_b|Add0~10 ;
wire \db_system_spwulight_b|Add0~13_sumout ;
wire \db_system_spwulight_b|counter~4_combout ;
wire \db_system_spwulight_b|Add0~14 ;
wire \db_system_spwulight_b|Add0~17_sumout ;
wire \db_system_spwulight_b|counter~5_combout ;
wire \db_system_spwulight_b|Add0~18 ;
wire \db_system_spwulight_b|Add0~21_sumout ;
wire \db_system_spwulight_b|counter~6_combout ;
wire \db_system_spwulight_b|Add0~22 ;
wire \db_system_spwulight_b|Add0~25_sumout ;
wire \db_system_spwulight_b|counter~7_combout ;
wire \db_system_spwulight_b|Add0~26 ;
wire \db_system_spwulight_b|Add0~1_sumout ;
wire \db_system_spwulight_b|counter~0_combout ;
wire \db_system_spwulight_b|Add0~2 ;
wire \db_system_spwulight_b|Add0~5_sumout ;
wire \db_system_spwulight_b|counter~2_combout ;
wire \db_system_spwulight_b|aux_pb~0_combout ;
wire \db_system_spwulight_b|PB_down~q ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ;
wire \db_system_spwulight_b|aux_pb~1_combout ;
wire \db_system_spwulight_b|aux_pb~q ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ;
wire \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ;
wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;
wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;
wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ;
wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;
wire \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ;
wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout ;
wire \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|router_001|Equal7~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal10~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~3_combout ;
wire \u0|mm_interconnect_0|router_001|Equal2~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal12~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|router_001|Equal1~4_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~5_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~26 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ;
wire \A_SPW_TOP|tx_data|mem~0feeder_combout ;
wire \sin_a~input_o ;
wire \din_a~input_o ;
wire \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ;
wire \A_SPW_TOP|SPW|FSM|got_bit_internal~q ;
wire \A_SPW_TOP|SPW|FSM|Add2~1_sumout ;
wire \A_SPW_TOP|SPW|FSM|Add2~22 ;
wire \A_SPW_TOP|SPW|FSM|Add2~17_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~18 ;
wire \A_SPW_TOP|SPW|FSM|Add2~13_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~14 ;
wire \A_SPW_TOP|SPW|FSM|Add2~10 ;
wire \A_SPW_TOP|SPW|FSM|Add2~6 ;
wire \A_SPW_TOP|SPW|FSM|Add2~45_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~11_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~46 ;
wire \A_SPW_TOP|SPW|FSM|Add2~41_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~10_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~42 ;
wire \A_SPW_TOP|SPW|FSM|Add2~37_sumout ;
wire \A_SPW_TOP|SPW|FSM|LessThan2~1_combout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~9_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~38 ;
wire \A_SPW_TOP|SPW|FSM|Add2~33_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~8_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~34 ;
wire \A_SPW_TOP|SPW|FSM|Add2~29_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~7_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal1~1_combout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~2 ;
wire \A_SPW_TOP|SPW|FSM|Add2~25_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~26 ;
wire \A_SPW_TOP|SPW|FSM|Add2~21_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~5_combout ;
wire \A_SPW_TOP|SPW|FSM|LessThan2~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~5_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add2~9_sumout ;
wire \A_SPW_TOP|SPW|FSM|after850ns~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal1~0_combout ;
wire \A_SPW_TOP|SPW|RX|always3~0_combout ;
wire \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~2 ;
wire \A_SPW_TOP|SPW|FSM|Add1~25_sumout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~26 ;
wire \A_SPW_TOP|SPW|FSM|Add1~21_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~22 ;
wire \A_SPW_TOP|SPW|FSM|Add1~17_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~5_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~18 ;
wire \A_SPW_TOP|SPW|FSM|Add1~13_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~14 ;
wire \A_SPW_TOP|SPW|FSM|Add1~9_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~10 ;
wire \A_SPW_TOP|SPW|FSM|Add1~5_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~6 ;
wire \A_SPW_TOP|SPW|FSM|Add1~46 ;
wire \A_SPW_TOP|SPW|FSM|Add1~41_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~11_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~42 ;
wire \A_SPW_TOP|SPW|FSM|Add1~30 ;
wire \A_SPW_TOP|SPW|FSM|Add1~37_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~10_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~38 ;
wire \A_SPW_TOP|SPW|FSM|Add1~33_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ;
wire \m_x|counter_neg[0]~feeder_combout ;
wire \m_x|Selector4~0_combout ;
wire \m_x|Selector1~0_combout ;
wire \m_x|Selector2~0_combout ;
wire \m_x|Selector2~1_combout ;
wire \m_x|WideOr7~0_combout ;
wire \m_x|Selector5~0_combout ;
wire \m_x|Selector0~0_combout ;
wire \m_x|Equal1~0_combout ;
wire \m_x|control_bit_found~q ;
wire \m_x|Selector0~1_combout ;
wire \m_x|Selector0~2_combout ;
wire \m_x|is_control~q ;
wire \m_x|Selector3~0_combout ;
wire \m_x|always2~1_combout ;
wire \m_x|Selector5~1_combout ;
wire \m_x|Selector5~2_combout ;
wire \m_x|Selector5~3_combout ;
wire \m_x|always2~0_combout ;
wire \m_x|always1~0_combout ;
wire \m_x|bit_c_0~q ;
wire \m_x|bit_c_2~feeder_combout ;
wire \m_x|bit_c_2~q ;
wire \m_x|control_r[2]~feeder_combout ;
wire \m_x|control_p_r[2]~feeder_combout ;
wire \m_x|ready_control_p_r~0_combout ;
wire \m_x|ready_control_p_r~q ;
wire \m_x|info[12]~feeder_combout ;
wire \m_x|Equal1~1_combout ;
wire \m_x|ready_data_p~combout ;
wire \m_x|ready_data_p_r~0_combout ;
wire \m_x|ready_data_p_r~1_combout ;
wire \m_x|ready_data_p_r~q ;
wire \m_x|data_l_r[7]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ;
wire \m_x|bit_c_1~q ;
wire \m_x|bit_c_3~q ;
wire \m_x|control_r[3]~feeder_combout ;
wire \m_x|control_p_r[3]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|router_001|Equal13~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal13~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|router_001|Equal5~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|router_001|Equal18~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal18~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal19~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|router|Equal13~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ;
wire \u0|mm_interconnect_0|router|Equal15~0_combout ;
wire \u0|mm_interconnect_0|router|Equal15~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ;
wire \u0|mm_interconnect_0|router|Equal6~2_combout ;
wire \u0|mm_interconnect_0|router|Equal7~2_combout ;
wire \u0|mm_interconnect_0|router|Equal7~1_combout ;
wire \u0|mm_interconnect_0|router|Equal7~3_combout ;
wire \u0|mm_interconnect_0|router|Equal7~4_combout ;
wire \u0|mm_interconnect_0|router|Equal6~0_combout ;
wire \u0|mm_interconnect_0|router|Equal6~1_combout ;
wire \u0|mm_interconnect_0|router|src_data[103]~0_combout ;
wire \u0|mm_interconnect_0|router|Equal14~1_combout ;
wire \u0|mm_interconnect_0|router|Equal21~0_combout ;
wire \u0|mm_interconnect_0|router|Equal20~0_combout ;
wire \u0|mm_interconnect_0|router|src_data[102]~6_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ;
wire \u0|mm_interconnect_0|router|src_data[100]~2_combout ;
wire \u0|mm_interconnect_0|router|src_data[100]~3_combout ;
wire \u0|mm_interconnect_0|router|src_data[100]~1_combout ;
wire \u0|mm_interconnect_0|router|src_data[100]~7_combout ;
wire \u0|mm_interconnect_0|router|src_data[104]~9_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ;
wire \u0|mm_interconnect_0|router|src_data[101]~8_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal14~1_combout ;
wire \u0|mm_interconnect_0|router_001|Equal14~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ;
wire \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|router_001|Equal17~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal17~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ;
wire \u0|mm_interconnect_0|router|Equal17~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ;
wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ;
wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|router|src_data[103]~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal7~1_combout ;
wire \u0|mm_interconnect_0|router_001|Equal7~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ;
wire \u0|mm_interconnect_0|router|Equal7~9_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ;
wire \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ;
wire \u0|mm_interconnect_0|router_001|Equal8~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ;
wire \u0|mm_interconnect_0|router_001|Equal3~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal3~1_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[103]~5_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|router_001|Equal11~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|router_001|Equal9~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ;
wire \u0|mm_interconnect_0|router|Equal13~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ;
wire \u0|link_start|data_out~feeder_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ;
wire \u0|link_start|always0~0_combout ;
wire \u0|link_start|data_out~q ;
wire \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|auto_start|always0~0_combout ;
wire \u0|auto_start|data_out~q ;
wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|Selector2~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector2~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector3~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector3~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector1~0_combout ;
wire \A_SPW_TOP|SPW|RX|control_bit_found~q ;
wire \A_SPW_TOP|SPW|RX|Selector0~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector0~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector0~2_combout ;
wire \A_SPW_TOP|SPW|RX|is_control~q ;
wire \A_SPW_TOP|SPW|RX|always2~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_data_p~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_data_p~combout ;
wire \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_data_p_r~q ;
wire \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_control_p_r~q ;
wire \A_SPW_TOP|SPW|RX|last_is_control~0_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_control~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_control~q ;
wire \A_SPW_TOP|SPW|RX|bit_c_0~q ;
wire \A_SPW_TOP|SPW|RX|control_r[0]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_c_1~q ;
wire \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_c_2~q ;
wire \A_SPW_TOP|SPW|RX|control_r[2]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|always8~0_combout ;
wire \A_SPW_TOP|SPW|RX|always11~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ;
wire \A_SPW_TOP|SPW|RX|last_is_data~0_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_data~1_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_data~q ;
wire \A_SPW_TOP|SPW|RX|last_is_timec~0_combout ;
wire \A_SPW_TOP|SPW|RX|last_is_timec~q ;
wire \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_nchar~q ;
wire \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_time_code~q ;
wire \A_SPW_TOP|SPW|FSM|always0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~2_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_null~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_null~q ;
wire \A_SPW_TOP|SPW|FSM|Selector4~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector4~1_combout ;
wire \A_SPW_TOP|SPW|FSM|always2~0_combout ;
wire \A_SPW_TOP|SPW|FSM|always0~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector2~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector2~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector4~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector4~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|link_disable|always0~0_combout ;
wire \u0|link_disable|data_out~q ;
wire \A_SPW_TOP|SPW|FSM|Selector4~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector4~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector4~5_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ;
wire \A_SPW_TOP|SPW|FSM|Selector2~5_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector2~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector2~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector2~0_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ;
wire \A_SPW_TOP|SPW|FSM|Selector3~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector3~1_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.started~q ;
wire \A_SPW_TOP|SPW|FSM|Selector1~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector1~1_combout ;
wire \A_SPW_TOP|SPW|FSM|after128us~13_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~29_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~8_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~30 ;
wire \A_SPW_TOP|SPW|FSM|Add0~26 ;
wire \A_SPW_TOP|SPW|FSM|Add0~21_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~6_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~22 ;
wire \A_SPW_TOP|SPW|FSM|Add0~17_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~5_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~18 ;
wire \A_SPW_TOP|SPW|FSM|Add0~14 ;
wire \A_SPW_TOP|SPW|FSM|Add0~9_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~10 ;
wire \A_SPW_TOP|SPW|FSM|Add0~5_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~6 ;
wire \A_SPW_TOP|SPW|FSM|Add0~1_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~2 ;
wire \A_SPW_TOP|SPW|FSM|Add0~45_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~12_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~46 ;
wire \A_SPW_TOP|SPW|FSM|Add0~41_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~11_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~42 ;
wire \A_SPW_TOP|SPW|FSM|Add0~37_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~10_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~2_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector1~0_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ;
wire \A_SPW_TOP|SPW|FSM|always2~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~13_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~4_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~38 ;
wire \A_SPW_TOP|SPW|FSM|Add0~33_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~9_combout ;
wire \A_SPW_TOP|SPW|FSM|Add0~25_sumout ;
wire \A_SPW_TOP|SPW|FSM|after128us~7_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal0~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector0~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector0~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector0~2_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ;
wire \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ;
wire \A_SPW_TOP|SPW|FSM|after64us~7_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~0_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~45_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~12_combout ;
wire \A_SPW_TOP|SPW|FSM|Equal2~3_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~29_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~8_combout ;
wire \A_SPW_TOP|SPW|FSM|Add1~1_sumout ;
wire \A_SPW_TOP|SPW|FSM|after64us~1_combout ;
wire \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ;
wire \A_SPW_TOP|SPW|FSM|rx_resetn~q ;
wire \A_SPW_TOP|SPW|RX|WideOr7~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector5~1_combout ;
wire \A_SPW_TOP|SPW|RX|Selector5~0_combout ;
wire \A_SPW_TOP|SPW|RX|Selector5~2_combout ;
wire \A_SPW_TOP|SPW|RX|Selector4~0_combout ;
wire \A_SPW_TOP|SPW|RX|always2~1_combout ;
wire \A_SPW_TOP|SPW|RX|always1~0_combout ;
wire \A_SPW_TOP|SPW|RX|ready_data~combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_0~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_2~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_2~q ;
wire \A_SPW_TOP|SPW|RX|timecode[7]~0_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_4~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_1~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_3~q ;
wire \A_SPW_TOP|SPW|RX|timecode[4]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|timecode[6]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_5~q ;
wire \A_SPW_TOP|SPW|RX|always9~0_combout ;
wire \A_SPW_TOP|SPW|RX|last_was_control~q ;
wire \A_SPW_TOP|SPW|RX|last_was_timec~q ;
wire \A_SPW_TOP|SPW|RX|rx_error~1_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_7~q ;
wire \A_SPW_TOP|SPW|RX|bit_d_6~q ;
wire \A_SPW_TOP|SPW|RX|bit_c_3~q ;
wire \A_SPW_TOP|SPW|RX|control_r[3]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~2_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~6_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~4_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data[9]~0_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|always9~4_combout ;
wire \A_SPW_TOP|SPW|RX|last_was_data~q ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|always9~5_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~7_combout ;
wire \A_SPW_TOP|SPW|RX|always9~6_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~8_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_8~q ;
wire \A_SPW_TOP|SPW|RX|data[8]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|bit_d_9~q ;
wire \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|data[9]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~3_combout ;
wire \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|always9~2_combout ;
wire \A_SPW_TOP|SPW|RX|always9~3_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~5_combout ;
wire \A_SPW_TOP|SPW|RX|always9~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~9_combout ;
wire \A_SPW_TOP|SPW|RX|rx_error~q ;
wire \A_SPW_TOP|rx_data|overflow_credit_error~feeder_combout ;
wire \A_SPW_TOP|rx_data|credit_counter[0]~8_combout ;
wire \A_SPW_TOP|rx_data|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|data_read_en_rx|always0~0_combout ;
wire \u0|data_read_en_rx|data_out~q ;
wire \A_SPW_TOP|SPW|RX|rx_data_take~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_take~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_take~q ;
wire \A_SPW_TOP|SPW|RX|rx_data_take_0~q ;
wire \A_SPW_TOP|SPW|RX|rx_buffer_write~q ;
wire \A_SPW_TOP|rx_data|Add0~2 ;
wire \A_SPW_TOP|rx_data|Add0~5_sumout ;
wire \A_SPW_TOP|rx_data|Add0~6 ;
wire \A_SPW_TOP|rx_data|Add0~9_sumout ;
wire \A_SPW_TOP|rx_data|counter[2]~feeder_combout ;
wire \A_SPW_TOP|rx_data|Add0~10 ;
wire \A_SPW_TOP|rx_data|Add0~13_sumout ;
wire \A_SPW_TOP|rx_data|counter[3]~feeder_combout ;
wire \A_SPW_TOP|rx_data|Add0~14 ;
wire \A_SPW_TOP|rx_data|Add0~17_sumout ;
wire \A_SPW_TOP|rx_data|counter[4]~feeder_combout ;
wire \A_SPW_TOP|rx_data|Add0~18 ;
wire \A_SPW_TOP|rx_data|Add0~21_sumout ;
wire \A_SPW_TOP|rx_data|counter[5]~feeder_combout ;
wire \A_SPW_TOP|rx_data|Equal1~0_combout ;
wire \A_SPW_TOP|rx_data|f_empty~q ;
wire \A_SPW_TOP|rx_data|block_read~0_combout ;
wire \A_SPW_TOP|rx_data|block_read~q ;
wire \A_SPW_TOP|rx_data|counter~0_combout ;
wire \A_SPW_TOP|rx_data|Equal0~0_combout ;
wire \A_SPW_TOP|rx_data|f_full~q ;
wire \A_SPW_TOP|rx_data|block_write~0_combout ;
wire \A_SPW_TOP|rx_data|block_write~q ;
wire \A_SPW_TOP|rx_data|mem~12_combout ;
wire \A_SPW_TOP|rx_data|Add1~2_combout ;
wire \A_SPW_TOP|rx_data|Add1~1_combout ;
wire \A_SPW_TOP|rx_data|Add1~0_combout ;
wire \A_SPW_TOP|rx_data|credit_counter~3_combout ;
wire \A_SPW_TOP|rx_data|credit_counter[3]~4_combout ;
wire \A_SPW_TOP|rx_data|rd_ptr~1_combout ;
wire \A_SPW_TOP|rx_data|rd_ptr~2_combout ;
wire \A_SPW_TOP|rx_data|rd_ptr~3_combout ;
wire \A_SPW_TOP|rx_data|rd_ptr~4_combout ;
wire \A_SPW_TOP|rx_data|always2~1_combout ;
wire \A_SPW_TOP|rx_data|rd_ptr~5_combout ;
wire \A_SPW_TOP|rx_data|rd_ptr~0_combout ;
wire \A_SPW_TOP|rx_data|always2~0_combout ;
wire \A_SPW_TOP|rx_data|credit_counter[3]~1_combout ;
wire \A_SPW_TOP|rx_data|credit_counter~2_combout ;
wire \A_SPW_TOP|rx_data|credit_counter~5_combout ;
wire \A_SPW_TOP|rx_data|credit_counter~0_combout ;
wire \A_SPW_TOP|rx_data|always0~0_combout ;
wire \A_SPW_TOP|rx_data|overflow_credit_error~q ;
wire \A_SPW_TOP|SPW|FSM|Selector5~1_combout ;
wire \A_SPW_TOP|SPW|FSM|Selector5~0_combout ;
wire \A_SPW_TOP|SPW|FSM|state_fsm.run~q ;
wire \A_SPW_TOP|tx_reset_n~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|write_en_tx|always0~0_combout ;
wire \u0|write_en_tx|data_out~q ;
wire \A_SPW_TOP|tx_data|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|timecode_tx_enable|always0~0_combout ;
wire \u0|timecode_tx_enable|data_out~q ;
wire \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ;
wire \A_SPW_TOP|SPW|FSM|send_fct_tx~q ;
wire \A_SPW_TOP|rx_data|open_slot_fct~q ;
wire \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ;
wire \A_SPW_TOP|tx_data|write_tx~0_combout ;
wire \A_SPW_TOP|tx_data|write_tx~q ;
wire \A_SPW_TOP|SPW|TX|always7~3_combout ;
wire \A_SPW_TOP|SPW|TX|always7~5_combout ;
wire \A_SPW_TOP|SPW|TX|Selector5~1_combout ;
wire \A_SPW_TOP|SPW|TX|Add2~0_combout ;
wire \A_SPW_TOP|SPW|TX|fct_flag~3_combout ;
wire \A_SPW_TOP|SPW|FSM|enable_tx~0_combout ;
wire \A_SPW_TOP|SPW|FSM|enable_tx~q ;
wire \A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout ;
wire \A_SPW_TOP|SPW|TX|fct_flag~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector5~2_combout ;
wire \A_SPW_TOP|SPW|TX|Selector5~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ;
wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~0_combout ;
wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~q ;
wire \A_SPW_TOP|SPW|TX|fct_flag~4_combout ;
wire \A_SPW_TOP|SPW|TX|fct_flag[0]~10_combout ;
wire \A_SPW_TOP|SPW|TX|always7~4_combout ;
wire \A_SPW_TOP|SPW|TX|Selector3~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ;
wire \A_SPW_TOP|SPW|TX|enable_time_code~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector5~0_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer~5_combout ;
wire \A_SPW_TOP|SPW|TX|Selector4~0_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ;
wire \A_SPW_TOP|SPW|TX|Add4~0_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer~2_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~21_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_data~0_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_data~q ;
wire \A_SPW_TOP|tx_data|counter~0_combout ;
wire \A_SPW_TOP|tx_data|Add0~2 ;
wire \A_SPW_TOP|tx_data|Add0~5_sumout ;
wire \A_SPW_TOP|tx_data|Add0~6 ;
wire \A_SPW_TOP|tx_data|Add0~10 ;
wire \A_SPW_TOP|tx_data|Add0~13_sumout ;
wire \A_SPW_TOP|tx_data|Add0~14 ;
wire \A_SPW_TOP|tx_data|Add0~17_sumout ;
wire \A_SPW_TOP|tx_data|Add0~18 ;
wire \A_SPW_TOP|tx_data|Add0~21_sumout ;
wire \A_SPW_TOP|tx_data|Equal0~0_combout ;
wire \A_SPW_TOP|tx_data|f_full~q ;
wire \A_SPW_TOP|tx_data|block_write~0_combout ;
wire \A_SPW_TOP|tx_data|block_write~q ;
wire \A_SPW_TOP|tx_data|Add0~9_sumout ;
wire \A_SPW_TOP|tx_data|Equal1~0_combout ;
wire \A_SPW_TOP|tx_data|f_empty~q ;
wire \A_SPW_TOP|tx_data|block_read~0_combout ;
wire \A_SPW_TOP|tx_data|block_read~q ;
wire \A_SPW_TOP|tx_data|mem~0_q ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ;
wire \u0|write_data_fifo_tx|data_out[8]~feeder_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|write_data_fifo_tx|always0~0_combout ;
wire \A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ;
wire \A_SPW_TOP|tx_data|mem~14_combout ;
wire \A_SPW_TOP|tx_data|comb~0_combout ;
wire \A_SPW_TOP|tx_data|Add2~1_combout ;
wire \A_SPW_TOP|tx_data|Add2~2_combout ;
wire \A_SPW_TOP|tx_data|Add2~3_combout ;
wire \A_SPW_TOP|tx_data|Add2~4_combout ;
wire \A_SPW_TOP|tx_data|Add2~0_combout ;
wire \A_SPW_TOP|tx_data|mem~12_combout ;
wire \A_SPW_TOP|tx_data|mem~13_combout ;
wire \A_SPW_TOP|tx_data|mem~9_q ;
wire \A_SPW_TOP|tx_data|block_read~_wirecell_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ;
wire \u0|write_data_fifo_tx|data_out[0]~feeder_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~1_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~2_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~3_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~4_combout ;
wire \A_SPW_TOP|tx_data|Add3~0_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~5_combout ;
wire \A_SPW_TOP|tx_data|rd_ptr~0_combout ;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ;
wire \u0|write_data_fifo_tx|data_out[3]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ;
wire \u0|write_data_fifo_tx|data_out[4]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ;
wire \u0|write_data_fifo_tx|data_out[5]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ;
wire \u0|write_data_fifo_tx|data_out[7]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 ;
wire \A_SPW_TOP|tx_data|data_out~9_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem~10_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem~11_combout ;
wire \A_SPW_TOP|tx_data|data_out~10_combout ;
wire \A_SPW_TOP|tx_data|data_out~2_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~11_combout ;
wire \A_SPW_TOP|SPW|TX|Equal5~4_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer~8_combout ;
wire \A_SPW_TOP|SPW|TX|Equal5~0_combout ;
wire \A_SPW_TOP|SPW|TX|hold_fct~0_combout ;
wire \A_SPW_TOP|SPW|TX|hold_fct~q ;
wire \A_SPW_TOP|SPW|TX|always7~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~14_combout ;
wire \A_SPW_TOP|SPW|TX|hold_data~0_combout ;
wire \A_SPW_TOP|SPW|TX|hold_data~q ;
wire \A_SPW_TOP|SPW|TX|always7~1_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ;
wire \A_SPW_TOP|SPW|RX|always8~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_got_fct~q ;
wire \A_SPW_TOP|SPW|TX|always7~2_combout ;
wire \A_SPW_TOP|SPW|TX|hold_data~1_combout ;
wire \A_SPW_TOP|SPW|TX|block_sum~0_combout ;
wire \A_SPW_TOP|SPW|TX|block_sum~q ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~11_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~10_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan2~1_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~3_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~5_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~1_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout ;
wire \A_SPW_TOP|SPW|TX|fct_counter_receive~7_combout ;
wire \A_SPW_TOP|SPW|TX|LessThan2~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector4~1_combout ;
wire \A_SPW_TOP|SPW|TX|Selector4~2_combout ;
wire \A_SPW_TOP|SPW|TX|Add4~1_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer~4_combout ;
wire \A_SPW_TOP|SPW|TX|first_time~feeder_combout ;
wire \A_SPW_TOP|SPW|TX|first_time~q ;
wire \A_SPW_TOP|SPW|TX|last_type~10_combout ;
wire \A_SPW_TOP|SPW|TX|hold_null~0_combout ;
wire \A_SPW_TOP|SPW|TX|hold_null~q ;
wire \A_SPW_TOP|SPW|FSM|WideOr0~combout ;
wire \A_SPW_TOP|SPW|FSM|send_null_tx~q ;
wire \A_SPW_TOP|SPW|TX|Selector0~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ;
wire \A_SPW_TOP|SPW|TX|Selector1~0_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ;
wire \A_SPW_TOP|SPW|TX|Selector2~0_combout ;
wire \A_SPW_TOP|SPW|TX|Selector2~1_combout ;
wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ;
wire \A_SPW_TOP|SPW|TX|tx_sout~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ;
wire \u0|timecode_tx_data|data_out[3]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|timecode_tx_data|always0~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ;
wire \u0|timecode_tx_data|data_out[6]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ;
wire \u0|timecode_tx_data|data_out[7]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ;
wire \u0|timecode_tx_data|data_out[4]~feeder_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ;
wire \u0|timecode_tx_data|data_out[0]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ;
wire \u0|timecode_tx_data|data_out[2]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ;
wire \u0|timecode_tx_data|data_out[1]~feeder_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~15_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~16_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~17_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~12_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~13_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~20_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.TIMEC~q ;
wire \A_SPW_TOP|SPW|TX|Equal5~2_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~18_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~19_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.DATA~q ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a6 ;
wire \A_SPW_TOP|tx_data|mem~7_q ;
wire \A_SPW_TOP|tx_data|data_out~15_combout ;
wire \A_SPW_TOP|tx_data|data_out~16_combout ;
wire \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a5 ;
wire \A_SPW_TOP|tx_data|mem~6_q ;
wire \A_SPW_TOP|tx_data|data_out~5_combout ;
wire \A_SPW_TOP|tx_data|data_out~6_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a7 ;
wire \A_SPW_TOP|tx_data|mem~8_q ;
wire \A_SPW_TOP|tx_data|data_out~0_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder_combout ;
wire \A_SPW_TOP|tx_data|data_out~1_combout ;
wire \A_SPW_TOP|tx_data|mem~5_q ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 ;
wire \A_SPW_TOP|tx_data|data_out~7_combout ;
wire \A_SPW_TOP|tx_data|data_out~8_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a2 ;
wire \A_SPW_TOP|tx_data|mem~3_q ;
wire \A_SPW_TOP|tx_data|data_out~17_combout ;
wire \A_SPW_TOP|tx_data|data_out~18_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a3 ;
wire \A_SPW_TOP|tx_data|mem~4_q ;
wire \A_SPW_TOP|tx_data|data_out~3_combout ;
wire \A_SPW_TOP|tx_data|data_out~4_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~4_combout ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a1 ;
wire \A_SPW_TOP|tx_data|mem~2_q ;
wire \A_SPW_TOP|tx_data|data_out~11_combout ;
wire \A_SPW_TOP|tx_data|data_out~12_combout ;
wire \A_SPW_TOP|tx_data|mem~1_q ;
wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ;
wire \A_SPW_TOP|tx_data|data_out~13_combout ;
wire \A_SPW_TOP|tx_data|data_out~14_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~28_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~22_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.EOP~q ;
wire \A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_null~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_null~2_combout ;
wire \A_SPW_TOP|SPW|TX|enable_n_char~0_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~26_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~27_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.FCT~q ;
wire \A_SPW_TOP|SPW|TX|last_type~24_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~23_combout ;
wire \A_SPW_TOP|SPW|TX|last_type~25_combout ;
wire \A_SPW_TOP|SPW|TX|last_type.NULL~q ;
wire \A_SPW_TOP|SPW|TX|tx_dout~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~6_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~8_combout ;
wire \A_SPW_TOP|SPW|TX|Equal5~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~7_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~9_combout ;
wire \A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~5_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ;
wire \A_SPW_TOP|SPW|TX|always3~4_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ;
wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout ;
wire \A_SPW_TOP|SPW|TX|Equal5~1_combout ;
wire \A_SPW_TOP|SPW|TX|timecode_s~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~2_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~22_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~27_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~12_combout ;
wire \A_SPW_TOP|SPW|TX|always3~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~13_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~23_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~19_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout ;
wire \A_SPW_TOP|SPW|TX|always3~1_combout ;
wire \A_SPW_TOP|SPW|TX|always3~5_combout ;
wire \A_SPW_TOP|SPW|TX|always3~2_combout ;
wire \A_SPW_TOP|SPW|TX|always3~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~6_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~0_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~4_combout ;
wire \A_SPW_TOP|SPW|TX|tx_sout~2_combout ;
wire \A_SPW_TOP|SPW|TX|last_tx_sout~q ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~25_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~24_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_data~18_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~11_combout ;
wire \A_SPW_TOP|SPW|TX|last_tx_dout~q ;
wire \A_SPW_TOP|SPW|TX|tx_sout~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout~10_combout ;
wire \A_SPW_TOP|SPW|TX|tx_sout_e~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_sout_e~q ;
wire \m_x|always3~0_combout ;
wire \m_x|control_r[1]~feeder_combout ;
wire \m_x|control_p_r[1]~feeder_combout ;
wire \m_x|info[11]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \m_x|control_r[0]~feeder_combout ;
wire \m_x|info[10]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \A_SPW_TOP|rx_data|comb~0_combout ;
wire \A_SPW_TOP|rx_data|block_read~_wirecell_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ;
wire \A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ;
wire \A_SPW_TOP|rx_data|Add4~1_combout ;
wire \A_SPW_TOP|rx_data|Add4~2_combout ;
wire \A_SPW_TOP|rx_data|Add4~3_combout ;
wire \A_SPW_TOP|rx_data|Add4~4_combout ;
wire \A_SPW_TOP|rx_data|Add4~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ;
wire \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 ;
wire \A_SPW_TOP|rx_data|mem~0feeder_combout ;
wire \A_SPW_TOP|rx_data|mem~0_q ;
wire \A_SPW_TOP|rx_data|mem~14_combout ;
wire \A_SPW_TOP|rx_data|mem~13_combout ;
wire \A_SPW_TOP|rx_data|mem~9_q ;
wire \A_SPW_TOP|rx_data|data_out~16_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem~10_combout ;
wire \A_SPW_TOP|rx_data|mem~11_combout ;
wire \A_SPW_TOP|rx_data|data_out~17_combout ;
wire \A_SPW_TOP|rx_data|always1~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ;
wire \m_x|info[8]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a7 ;
wire \A_SPW_TOP|rx_data|mem~8_q ;
wire \A_SPW_TOP|rx_data|data_out~14_combout ;
wire \A_SPW_TOP|rx_data|data_out~15_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ;
wire \u0|mm_interconnect_0|router|Equal14~0_combout ;
wire \u0|mm_interconnect_0|router|Equal16~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a6 ;
wire \A_SPW_TOP|rx_data|mem~7_q ;
wire \A_SPW_TOP|rx_data|data_out~12_combout ;
wire \A_SPW_TOP|rx_data|data_out~13_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|counter_rx_fifo|read_mux_out[5]~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|counter_tx_fifo|read_mux_out[5]~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a5 ;
wire \A_SPW_TOP|rx_data|mem~6_q ;
wire \A_SPW_TOP|rx_data|data_out~10_combout ;
wire \A_SPW_TOP|rx_data|data_out~11_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ;
wire \m_x|bit_d_1~q ;
wire \m_x|bit_d_3~feeder_combout ;
wire \m_x|bit_d_3~q ;
wire \m_x|bit_d_5~feeder_combout ;
wire \m_x|bit_d_5~q ;
wire \m_x|dta_timec_p[2]~feeder_combout ;
wire \m_x|data~9_combout ;
wire \m_x|last_is_timec~0_combout ;
wire \m_x|last_is_timec~q ;
wire \m_x|last_is_control~0_combout ;
wire \m_x|last_is_control~q ;
wire \m_x|last_is_data~0_combout ;
wire \m_x|last_is_data~q ;
wire \m_x|data[8]~1_combout ;
wire \m_x|data[8]~2_combout ;
wire \m_x|dta_timec[6]~feeder_combout ;
wire \m_x|dta_timec_p[6]~feeder_combout ;
wire \m_x|data~5_combout ;
wire \m_x|bit_d_0~q ;
wire \m_x|bit_d_2~feeder_combout ;
wire \m_x|bit_d_2~q ;
wire \m_x|bit_d_4~q ;
wire \m_x|dta_timec_p[3]~feeder_combout ;
wire \m_x|data~8_combout ;
wire \m_x|data~6_combout ;
wire \m_x|dta_timec[4]~feeder_combout ;
wire \m_x|dta_timec_p[4]~feeder_combout ;
wire \m_x|data~7_combout ;
wire \m_x|dta_timec[7]~feeder_combout ;
wire \m_x|dta_timec_p[7]~feeder_combout ;
wire \m_x|data~4_combout ;
wire \m_x|always9~4_combout ;
wire \m_x|bit_d_6~q ;
wire \m_x|bit_d_8~feeder_combout ;
wire \m_x|bit_d_8~q ;
wire \m_x|dta_timec[8]~feeder_combout ;
wire \m_x|dta_timec_p[8]~feeder_combout ;
wire \m_x|data~0_combout ;
wire \m_x|rx_error~6_combout ;
wire \m_x|bit_d_7~q ;
wire \m_x|data~3_combout ;
wire \m_x|dta_timec[1]~feeder_combout ;
wire \m_x|dta_timec_p[1]~feeder_combout ;
wire \m_x|data~10_combout ;
wire \m_x|always9~5_combout ;
wire \m_x|last_was_data~q ;
wire \m_x|last_was_timec~q ;
wire \m_x|last_was_control~q ;
wire \m_x|rx_error~8_combout ;
wire \m_x|rx_error~7_combout ;
wire \m_x|rx_error~9_combout ;
wire \m_x|rx_error~2_combout ;
wire \m_x|timecode[5]~feeder_combout ;
wire \m_x|timecode[7]~0_combout ;
wire \m_x|always9~0_combout ;
wire \m_x|rx_error~0_combout ;
wire \m_x|rx_error~3_combout ;
wire \m_x|always9~3_combout ;
wire \m_x|rx_error~4_combout ;
wire \m_x|rx_error~5_combout ;
wire \m_x|data_l_r[7]~1_combout ;
wire \m_x|always9~2_combout ;
wire \m_x|always9~1_combout ;
wire \m_x|rx_error~1_combout ;
wire \m_x|rx_error~10_combout ;
wire \m_x|rx_error~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ;
wire \m_x|always0~0_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a4 ;
wire \A_SPW_TOP|rx_data|mem~5_q ;
wire \A_SPW_TOP|rx_data|data_out~8_combout ;
wire \A_SPW_TOP|rx_data|data_out~9_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|led_pio_test|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fsm_info|read_mux_out[4]~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ;
wire \u0|counter_rx_fifo|read_mux_out[4]~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ;
wire \u0|counter_tx_fifo|read_mux_out[4]~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ;
wire \u0|mm_interconnect_0|router|Equal7~7_combout ;
wire \u0|mm_interconnect_0|router|Equal7~8_combout ;
wire \u0|mm_interconnect_0|router|src_data[103]~5_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux|src1_valid~combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a3 ;
wire \A_SPW_TOP|rx_data|mem~4_q ;
wire \A_SPW_TOP|rx_data|data_out~6_combout ;
wire \A_SPW_TOP|rx_data|data_out~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ;
wire \m_x|always10~0_combout ;
wire \m_x|rx_got_null~1_combout ;
wire \m_x|rx_got_null~0_combout ;
wire \m_x|rx_got_null~q ;
wire \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|counter_tx_fifo|read_mux_out[3]~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|counter_rx_fifo|read_mux_out[3]~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ;
wire \u0|fsm_info|read_mux_out[3]~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ;
wire \u0|counter_tx_fifo|read_mux_out[2]~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ;
wire \u0|counter_rx_fifo|read_mux_out[2]~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|fsm_info|read_mux_out[2]~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ;
wire \m_x|rx_got_nchar~0_combout ;
wire \m_x|rx_got_nchar~1_combout ;
wire \m_x|rx_got_nchar~q ;
wire \m_x|info[2]~feeder_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem~3_q ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 ;
wire \A_SPW_TOP|rx_data|data_out~4_combout ;
wire \A_SPW_TOP|rx_data|data_out~5_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|clock_sel|readdata[2]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ;
wire \u0|mm_interconnect_0|router_001|Equal2~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal4~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem~2_q ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 ;
wire \A_SPW_TOP|rx_data|data_out~2_combout ;
wire \A_SPW_TOP|rx_data|data_out~3_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ;
wire \m_x|rx_got_time_code~0_combout ;
wire \m_x|rx_got_time_code~q ;
wire \u0|data_info|readdata[1]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ;
wire \u0|clock_sel|always0~0_combout ;
wire \u0|clock_sel|readdata[1]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ;
wire \u0|counter_tx_fifo|read_mux_out[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ;
wire \u0|counter_rx_fifo|read_mux_out[1]~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|fsm_info|read_mux_out[1]~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal21~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout ;
wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ;
wire \u0|clock_sel|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|timecode_tx_enable|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ;
wire \u0|link_disable|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ;
wire \u0|write_en_tx|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ;
wire \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ;
wire \u0|counter_tx_fifo|read_mux_out[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|auto_start|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ;
wire \u0|counter_rx_fifo|read_mux_out[0]~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ;
wire \u0|fsm_info|read_mux_out[0]~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_full_rx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ;
wire \u0|data_read_en_rx|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_empty_rx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_full_tx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ;
wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder_combout ;
wire \A_SPW_TOP|rx_data|mem~1_q ;
wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ;
wire \A_SPW_TOP|rx_data|data_out~0_combout ;
wire \A_SPW_TOP|rx_data|data_out~1_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ;
wire \u0|link_start|readdata[0]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|fifo_empty_tx_status|read_mux_out~combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~1_combout ;
wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~q ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|timecode_tx_ready|read_mux_out~combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ;
wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;
wire \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ;
wire \A_SPW_TOP|SPW|RX|rx_tick_out~q ;
wire \u0|timecode_ready_rx|read_mux_out~combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ;
wire \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ;
wire \m_x|rx_got_fct~0_combout ;
wire \m_x|rx_got_fct~q ;
wire \m_x|info[0]~feeder_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ;
wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ;
wire \u0|mm_interconnect_0|router_001|Equal16~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal16~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ;
wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ;
wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ;
wire \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[103]~0_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[101]~3_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[104]~4_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[102]~2_combout ;
wire \u0|mm_interconnect_0|router_001|src_data[100]~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ;
wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ;
wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ;
wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ;
wire \u0|mm_interconnect_0|router_001|Equal6~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ;
wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ;
wire \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;
wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~28_combout ;
wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ;
wire \u0|mm_interconnect_0|router|Equal7~0_combout ;
wire \u0|mm_interconnect_0|router|Equal7~5_combout ;
wire \u0|mm_interconnect_0|router|Equal7~6_combout ;
wire \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ;
wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ;
wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ;
wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ;
wire \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ;
wire \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ;
wire \u0|mm_interconnect_0|router_001|Equal1~1_combout ;
wire \u0|mm_interconnect_0|router_001|Equal20~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ;
wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ;
wire \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ;
wire \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal14~0_combout ;
wire \u0|mm_interconnect_0|router_001|Equal15~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ;
wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ;
wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ;
wire \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ;
wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~10 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~34 ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|always4~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ;
wire \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ;
wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ;
wire \A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_e~1_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_e~3_combout ;
wire \A_SPW_TOP|SPW|TX|tx_dout_e~q ;
wire [9:0] \m_x|dta_timec_p ;
wire [9:0] \m_x|dta_timec ;
wire [2:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [3:0] \A_SPW_TOP|SPW|RX|control_r ;
wire [5:0] \A_SPW_TOP|SPW|RX|counter_neg ;
wire [2:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits ;
wire [9:0] \m_x|data_l_r ;
wire [9:0] \m_x|data ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [2:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [8:0] \A_SPW_TOP|SPW|RX|rx_data_flag ;
wire [5:0] \A_SPW_TOP|rx_data|wr_ptr ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [2:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [2:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [9:0] \A_SPW_TOP|SPW|RX|data_l_r ;
wire [9:0] \A_SPW_TOP|SPW|RX|data ;
wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter ;
wire [5:0] \A_SPW_TOP|rx_data|rd_ptr ;
wire [3:0] \A_SPW_TOP|SPW|RX|control_l_r ;
wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter_100 ;
wire [5:0] \A_SPW_TOP|tx_data|wr_ptr ;
wire [11:0] \A_SPW_TOP|SPW|FSM|after850ns ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [0:21] \A_SPW_TOP|rx_data|mem_rtl_0_bypass ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [11:0] \A_SPW_TOP|SPW|FSM|after64us ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [3:0] \m_x|control_r ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre ;
wire [2:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [7:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count ;
wire [152:0] \u0|mm_interconnect_0|rsp_mux_001|src_payload ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg ;
wire [3:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften ;
wire [7:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_007|src_data ;
wire [3:0] \m_x|control ;
wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used ;
wire [0:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg ;
wire [7:0] \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [7:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg ;
wire [2:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used ;
wire [7:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used ;
wire [0:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [7:0] \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [31:0] \u0|fifo_full_tx_status|readdata ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_011|src_payload ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg ;
wire [0:0] \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [3:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used ;
wire [2:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [0:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|saved_grant ;
wire [3:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [7:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [3:0] \m_x|control_p_r ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_009|src_payload ;
wire [3:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [7:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used ;
wire [15:0] \db_system_spwulight_b|counter ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter ;
wire [7:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux|src_data ;
wire [128:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter ;
wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [7:0] \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter ;
wire [0:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg ;
wire [128:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_005|saved_grant ;
wire [128:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter ;
wire [3:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [3:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_018|src_data ;
wire [3:0] \m_x|control_l_r ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used ;
wire [31:0] \u0|fsm_info|readdata ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_016|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [7:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_020|saved_grant ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux|src_payload ;
wire [8:0] \A_SPW_TOP|tx_data|data_out ;
wire [7:0] \u0|timecode_tx_data|data_out ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_002|saved_grant ;
wire [3:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used ;
wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec_p ;
wire [0:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter ;
wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id ;
wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_ARVALID ;
wire [7:0] \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|divclk ;
wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter ;
wire [128:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [4:0] \u0|led_pio_test|data_out ;
wire [31:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_017|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_019|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [128:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [128:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [13:0] \u0|data_info|read_mux_out ;
wire [1:0] \u0|hps_0|fpga_interfaces|h2f_AWBURST ;
wire [128:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [3:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [31:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [31:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used ;
wire [3:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [0:0] \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [1:0] \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [31:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WVALID ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id ;
wire [29:0] \u0|hps_0|fpga_interfaces|h2f_ARADDR ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [0:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WLAST ;
wire [128:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [3:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [5:0] \A_SPW_TOP|rx_data|counter ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg ;
wire [7:0] \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [3:0] \u0|hps_0|fpga_interfaces|h2f_ARLEN ;
wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|saved_grant ;
wire [3:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_RREADY ;
wire [7:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_012|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|saved_grant ;
wire [0:21] \A_SPW_TOP|tx_data|mem_rtl_0_bypass ;
wire [31:0] \u0|data_info|readdata ;
wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used ;
wire [31:0] \u0|fifo_full_rx_status|readdata ;
wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used ;
wire [11:0] \u0|hps_0|fpga_interfaces|h2f_ARID ;
wire [3:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_013|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|saved_grant ;
wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [11:0] \u0|hps_0|fpga_interfaces|h2f_AWID ;
wire [3:0] \u0|hps_0|fpga_interfaces|h2f_WSTRB ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg ;
wire [0:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus ;
wire [8:0] \A_SPW_TOP|rx_data|data_out ;
wire [2:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used ;
wire [31:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_010|src_payload ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [3:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [31:0] \u0|timecode_ready_rx|readdata ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [2:0] \u0|hps_0|fpga_interfaces|h2f_ARSIZE ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_AWVALID ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used ;
wire [0:0] \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [3:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [1:0] \u0|hps_0|fpga_interfaces|h2f_ARBURST ;
wire [1:0] \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter ;
wire [31:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre ;
wire [128:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_011|src_data ;
wire [128:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [2:0] \u0|hps_0|fpga_interfaces|h2f_AWSIZE ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|saved_grant ;
wire [128:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [7:0] \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_006|saved_grant ;
wire [0:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used ;
wire [3:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [3:0] \A_SPW_TOP|SPW|RX|control_p_r ;
wire [7:0] \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec ;
wire [128:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [31:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre ;
wire [2:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [29:0] \u0|hps_0|fpga_interfaces|h2f_AWADDR ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter ;
wire [0:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used ;
wire [7:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [7:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used ;
wire [3:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [128:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [31:0] \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre ;
wire [128:0] \u0|mm_interconnect_0|rsp_mux|src_data ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_rst_n ;
wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter ;
wire [8:0] \u0|write_data_fifo_tx|data_out ;
wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter ;
wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used ;
wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter ;
wire [3:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [128:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [0:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_003|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_021|saved_grant ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [7:0] \u0|timecode_rx|read_mux_out ;
wire [3:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [31:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre ;
wire [13:0] \A_SPW_TOP|SPW|TX|timecode_s ;
wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used ;
wire [31:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre ;
wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [3:0] \A_SPW_TOP|SPW|RX|control ;
wire [31:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre ;
wire [3:0] \u0|hps_0|fpga_interfaces|h2f_AWLEN ;
wire [31:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre ;
wire [31:0] \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre ;
wire [31:0] \u0|hps_0|fpga_interfaces|h2f_WDATA ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [31:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_014|src_payload ;
wire [1:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire ;
wire [31:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre ;
wire [2:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [128:0] \u0|mm_interconnect_0|rsp_mux_001|src_data ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [5:0] \m_x|counter_neg ;
wire [128:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_009|src_data ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|saved_grant ;
wire [6:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount ;
wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_008|src_data ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_008|src_payload ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_004|src_data ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg ;
wire [5:0] \A_SPW_TOP|rx_data|credit_counter ;
wire [7:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [128:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;
wire [3:0] \A_SPW_TOP|SPW|TX|global_counter_transfer ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_004|src_payload ;
wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used ;
wire [128:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;
wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [13:0] \m_x|info ;
wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;
wire [128:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [0:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_receive ;
wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_018|src_payload ;
wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_015|src_data ;
wire [5:0] \A_SPW_TOP|tx_data|counter ;
wire [128:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_015|src_payload ;
wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [128:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [128:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_014|src_data ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [3:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg ;
wire [128:0] \u0|mm_interconnect_0|cmd_mux_010|src_data ;
wire [2:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;
wire [9:0] \A_SPW_TOP|SPW|RX|timecode ;
wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter ;
wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [31:0] \u0|counter_rx_fifo|readdata ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [11:0] \A_SPW_TOP|SPW|FSM|after128us ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;
wire [9:0] \m_x|timecode ;
wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|counter_tx_fifo|readdata ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_001|saved_grant ;
wire [31:0] \u0|write_data_fifo_tx|readdata ;
wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [0:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [5:0] \A_SPW_TOP|tx_data|rd_ptr ;
wire [0:0] \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg ;
wire [31:0] \u0|timecode_tx_data|readdata ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [2:0] \u0|clock_sel|data_out ;
wire [31:0] \u0|data_flag_rx|readdata ;
wire [31:0] \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre ;
wire [31:0] \u0|led_pio_test|readdata ;
wire [7:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [31:0] \u0|timecode_rx|readdata ;
wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;
wire [31:0] \u0|fifo_empty_tx_status|readdata ;
wire [31:0] \u0|fifo_empty_rx_status|readdata ;
wire [31:0] \u0|timecode_tx_ready|readdata ;
wire [7:0] \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx ;
wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire ;
wire [8:0] \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last ;
wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag ;
wire [1:0] \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;
wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [152:0] \u0|mm_interconnect_0|cmd_mux_007|src_payload ;
wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [7:0] \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [7:0] \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;
wire [8:0] \u0|data_flag_rx|read_mux_out ;
wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|saved_grant ;
wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;
wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used ;
wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;
wire [0:0] \u0|hps_0|fpga_interfaces|h2f_BREADY ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;
wire [31:0] \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ;
wire [3:0] \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ;
wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ;
wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ;
wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ;
wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ;
wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ;
wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ;
wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ;
wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ;
wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ;
wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ;
wire [127:0] \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ;
wire [15:0] \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ;
wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ;
wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ;
wire [39:0] \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
wire [39:0] \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
assign \u0|hps_0|fpga_interfaces|tpiu~trace_data = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [0];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [1];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [2];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [3];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [4];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [5];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [6];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [7];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [8];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [9];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [10];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [11];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [12];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [13];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [14];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [15];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [16];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [17];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [18];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [19];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [20];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [21];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [22];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [23];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [24];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [25];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [26];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [27];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [28];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [29];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [30];
assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [31];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [0];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [1];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [2];
assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [11];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [12];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [13];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [14];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [15];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [16];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [17];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [18];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [19];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [20] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [20];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [21] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [21];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [22] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [22];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [23] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [23];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [24] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [24];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [25] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [25];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [26] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [26];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [27] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [27];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [28] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [28];
assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [29] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [29];
assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_ARID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [11];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [11];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [12];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [13];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [14];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [15];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [16];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [17];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [18];
assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [19];
assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [9];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [10];
assign \u0|hps_0|fpga_interfaces|h2f_AWID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [11];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [3];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [4] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [4];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [5] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [5];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [6] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [6];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [7] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [7];
assign \u0|hps_0|fpga_interfaces|h2f_WDATA [8] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [8];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [0];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [1];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [2];
assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [3];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [0];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [1];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [2];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [3];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [4];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [5];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [6];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [7];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [0];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [1];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [2];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [3];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [4];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [5];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [6];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [7];
assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus [2];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a1 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a2 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [2];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a3 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [3];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [4];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a5 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [5];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a6 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [6];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a7 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [7];
assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [8];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [2];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a3 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [3];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a4 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [4];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a5 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [5];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a6 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [6];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a7 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [7];
assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [8];
// Location: IOOBUF_X68_Y10_N96
cyclonev_io_obuf \LED[5]~output (
.i(\db_system_spwulight_b|PB_down~q ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[5]),
.obar());
// synopsys translate_off
defparam \LED[5]~output .bus_hold = "false";
defparam \LED[5]~output .open_drain_output = "false";
defparam \LED[5]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y13_N56
cyclonev_io_obuf \LED[7]~output (
.i(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[7]),
.obar());
// synopsys translate_off
defparam \LED[7]~output .bus_hold = "false";
defparam \LED[7]~output .open_drain_output = "false";
defparam \LED[7]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X65_Y0_N36
cyclonev_io_obuf \dout_a~output (
.i(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(dout_a),
.obar(\dout_a(n) ));
// synopsys translate_off
defparam \dout_a~output .bus_hold = "false";
defparam \dout_a~output .open_drain_output = "false";
defparam \dout_a~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X53_Y0_N36
cyclonev_io_obuf \sout_a~output (
.i(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(sout_a),
.obar(\sout_a(n) ));
// synopsys translate_off
defparam \sout_a~output .bus_hold = "false";
defparam \sout_a~output .open_drain_output = "false";
defparam \sout_a~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y12_N22
cyclonev_io_obuf \LED[0]~output (
.i(\u0|led_pio_test|data_out [0]),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[0]),
.obar());
// synopsys translate_off
defparam \LED[0]~output .bus_hold = "false";
defparam \LED[0]~output .open_drain_output = "false";
defparam \LED[0]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y13_N39
cyclonev_io_obuf \LED[1]~output (
.i(\u0|led_pio_test|data_out [1]),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[1]),
.obar());
// synopsys translate_off
defparam \LED[1]~output .bus_hold = "false";
defparam \LED[1]~output .open_drain_output = "false";
defparam \LED[1]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y13_N5
cyclonev_io_obuf \LED[2]~output (
.i(\u0|led_pio_test|data_out [2]),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[2]),
.obar());
// synopsys translate_off
defparam \LED[2]~output .bus_hold = "false";
defparam \LED[2]~output .open_drain_output = "false";
defparam \LED[2]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y13_N22
cyclonev_io_obuf \LED[3]~output (
.i(\u0|led_pio_test|data_out [3]),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[3]),
.obar());
// synopsys translate_off
defparam \LED[3]~output .bus_hold = "false";
defparam \LED[3]~output .open_drain_output = "false";
defparam \LED[3]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y10_N79
cyclonev_io_obuf \LED[4]~output (
.i(\u0|led_pio_test|data_out [4]),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[4]),
.obar());
// synopsys translate_off
defparam \LED[4]~output .bus_hold = "false";
defparam \LED[4]~output .open_drain_output = "false";
defparam \LED[4]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOOBUF_X68_Y12_N5
cyclonev_io_obuf \LED[6]~output (
.i(gnd),
.oe(vcc),
.dynamicterminationcontrol(gnd),
.seriesterminationcontrol(16'b0000000000000000),
.parallelterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(LED[6]),
.obar());
// synopsys translate_off
defparam \LED[6]~output .bus_hold = "false";
defparam \LED[6]~output .open_drain_output = "false";
defparam \LED[6]~output .shift_series_termination_control = "false";
// synopsys translate_on
// Location: IOIBUF_X38_Y0_N1
cyclonev_io_ibuf \FPGA_CLK1_50~input (
.i(FPGA_CLK1_50),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\FPGA_CLK1_50~input_o ));
// synopsys translate_off
defparam \FPGA_CLK1_50~input .bus_hold = "false";
defparam \FPGA_CLK1_50~input .simulate_z_as = "z";
// synopsys translate_on
// Location: CLKCTRL_G5
cyclonev_clkena \FPGA_CLK1_50~inputCLKENA0 (
.inclk(\FPGA_CLK1_50~input_o ),
.ena(vcc),
.outclk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.enaout());
// synopsys translate_off
defparam \FPGA_CLK1_50~inputCLKENA0 .clock_type = "global clock";
defparam \FPGA_CLK1_50~inputCLKENA0 .disable_mode = "low";
defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_mode = "always enabled";
defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_power_up = "high";
defparam \FPGA_CLK1_50~inputCLKENA0 .test_syn = "high";
// synopsys translate_on
// Location: IOIBUF_X46_Y0_N52
cyclonev_io_ibuf \KEY[1]~input (
.i(KEY[1]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\KEY[1]~input_o ));
// synopsys translate_off
defparam \KEY[1]~input .bus_hold = "false";
defparam \KEY[1]~input .simulate_z_as = "z";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N33
cyclonev_lcell_comb \db_system_spwulight_b|PB_down~0 (
// Equation(s):
// \db_system_spwulight_b|PB_down~0_combout = !\KEY[1]~input_o
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|PB_down~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|PB_down~0 .extended_lut = "off";
defparam \db_system_spwulight_b|PB_down~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \db_system_spwulight_b|PB_down~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N0
cyclonev_lcell_comb \db_system_spwulight_b|Add0~61 (
// Equation(s):
// \db_system_spwulight_b|Add0~61_sumout = SUM(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))
// \db_system_spwulight_b|Add0~62 = CARRY(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|counter [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~61_sumout ),
.cout(\db_system_spwulight_b|Add0~62 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~61 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~61 .lut_mask = 64'h00000000000000FF;
defparam \db_system_spwulight_b|Add0~61 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N57
cyclonev_lcell_comb \db_system_spwulight_b|counter~16 (
// Equation(s):
// \db_system_spwulight_b|counter~16_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~61_sumout )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|Add0~61_sumout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~16 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~16 .lut_mask = 64'h00AA00AA00AA00AA;
defparam \db_system_spwulight_b|counter~16 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N6
cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~0 (
// Equation(s):
// \db_system_spwulight_b|LessThan0~0_combout = ( !\db_system_spwulight_b|counter [9] & ( (!\db_system_spwulight_b|counter [10] & (!\db_system_spwulight_b|counter [11] & (!\db_system_spwulight_b|counter [13] & !\db_system_spwulight_b|counter [12]))) ) )
.dataa(!\db_system_spwulight_b|counter [10]),
.datab(!\db_system_spwulight_b|counter [11]),
.datac(!\db_system_spwulight_b|counter [13]),
.datad(!\db_system_spwulight_b|counter [12]),
.datae(gnd),
.dataf(!\db_system_spwulight_b|counter [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|LessThan0~0 .extended_lut = "off";
defparam \db_system_spwulight_b|LessThan0~0 .lut_mask = 64'h8000800000000000;
defparam \db_system_spwulight_b|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N12
cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~1 (
// Equation(s):
// \db_system_spwulight_b|LessThan0~1_combout = ( \db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [7] & \db_system_spwulight_b|counter [8]) ) ) # ( !\db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [7] &
// (\db_system_spwulight_b|counter [8] & ((\db_system_spwulight_b|counter [4]) # (\db_system_spwulight_b|counter [6])))) ) )
.dataa(!\db_system_spwulight_b|counter [6]),
.datab(!\db_system_spwulight_b|counter [7]),
.datac(!\db_system_spwulight_b|counter [4]),
.datad(!\db_system_spwulight_b|counter [8]),
.datae(gnd),
.dataf(!\db_system_spwulight_b|counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|LessThan0~1 .extended_lut = "off";
defparam \db_system_spwulight_b|LessThan0~1 .lut_mask = 64'h0013001300330033;
defparam \db_system_spwulight_b|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N21
cyclonev_lcell_comb \db_system_spwulight_b|counter[0]~1 (
// Equation(s):
// \db_system_spwulight_b|counter[0]~1_combout = ( \KEY[1]~input_o ) # ( !\KEY[1]~input_o & ( (!\db_system_spwulight_b|counter [15] & (\db_system_spwulight_b|LessThan0~0_combout & (!\db_system_spwulight_b|LessThan0~1_combout &
// !\db_system_spwulight_b|counter [14]))) ) )
.dataa(!\db_system_spwulight_b|counter [15]),
.datab(!\db_system_spwulight_b|LessThan0~0_combout ),
.datac(!\db_system_spwulight_b|LessThan0~1_combout ),
.datad(!\db_system_spwulight_b|counter [14]),
.datae(gnd),
.dataf(!\KEY[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter[0]~1 .extended_lut = "off";
defparam \db_system_spwulight_b|counter[0]~1 .lut_mask = 64'h20002000FFFFFFFF;
defparam \db_system_spwulight_b|counter[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X46_Y1_N59
dffeas \db_system_spwulight_b|counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~16_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[0] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N3
cyclonev_lcell_comb \db_system_spwulight_b|Add0~57 (
// Equation(s):
// \db_system_spwulight_b|Add0~57_sumout = SUM(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 ))
// \db_system_spwulight_b|Add0~58 = CARRY(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|counter [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~62 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~57_sumout ),
.cout(\db_system_spwulight_b|Add0~58 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~57 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~57 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~57 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N54
cyclonev_lcell_comb \db_system_spwulight_b|counter~15 (
// Equation(s):
// \db_system_spwulight_b|counter~15_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~57_sumout )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(!\db_system_spwulight_b|Add0~57_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~15 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~15 .lut_mask = 64'h0A0A0A0A0A0A0A0A;
defparam \db_system_spwulight_b|counter~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X46_Y1_N56
dffeas \db_system_spwulight_b|counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~15_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[1] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N6
cyclonev_lcell_comb \db_system_spwulight_b|Add0~53 (
// Equation(s):
// \db_system_spwulight_b|Add0~53_sumout = SUM(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 ))
// \db_system_spwulight_b|Add0~54 = CARRY(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~58 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~53_sumout ),
.cout(\db_system_spwulight_b|Add0~54 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~53 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~53 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~53 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N51
cyclonev_lcell_comb \db_system_spwulight_b|counter~14 (
// Equation(s):
// \db_system_spwulight_b|counter~14_combout = ( \db_system_spwulight_b|Add0~53_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~53_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~14 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~14 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X46_Y1_N53
dffeas \db_system_spwulight_b|counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~14_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[2] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N9
cyclonev_lcell_comb \db_system_spwulight_b|Add0~49 (
// Equation(s):
// \db_system_spwulight_b|Add0~49_sumout = SUM(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 ))
// \db_system_spwulight_b|Add0~50 = CARRY(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 ))
.dataa(!\db_system_spwulight_b|counter [3]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~54 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~49_sumout ),
.cout(\db_system_spwulight_b|Add0~50 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~49 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~49 .lut_mask = 64'h0000FFFF00005555;
defparam \db_system_spwulight_b|Add0~49 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N48
cyclonev_lcell_comb \db_system_spwulight_b|counter~13 (
// Equation(s):
// \db_system_spwulight_b|counter~13_combout = ( \db_system_spwulight_b|Add0~49_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~49_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~13 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~13 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X46_Y1_N50
dffeas \db_system_spwulight_b|counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~13_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[3] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N12
cyclonev_lcell_comb \db_system_spwulight_b|Add0~37 (
// Equation(s):
// \db_system_spwulight_b|Add0~37_sumout = SUM(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 ))
// \db_system_spwulight_b|Add0~38 = CARRY(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~50 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~37_sumout ),
.cout(\db_system_spwulight_b|Add0~38 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~37 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~37 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~37 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N0
cyclonev_lcell_comb \db_system_spwulight_b|counter~10 (
// Equation(s):
// \db_system_spwulight_b|counter~10_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~37_sumout )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(!\db_system_spwulight_b|Add0~37_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~10 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~10 .lut_mask = 64'h0A0A0A0A0A0A0A0A;
defparam \db_system_spwulight_b|counter~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N2
dffeas \db_system_spwulight_b|counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~10_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[4] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N15
cyclonev_lcell_comb \db_system_spwulight_b|Add0~41 (
// Equation(s):
// \db_system_spwulight_b|Add0~41_sumout = SUM(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 ))
// \db_system_spwulight_b|Add0~42 = CARRY(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~38 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~41_sumout ),
.cout(\db_system_spwulight_b|Add0~42 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~41 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~41 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~41 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N15
cyclonev_lcell_comb \db_system_spwulight_b|counter~11 (
// Equation(s):
// \db_system_spwulight_b|counter~11_combout = ( !\KEY[1]~input_o & ( \db_system_spwulight_b|Add0~41_sumout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|Add0~41_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(!\KEY[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~11 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~11 .lut_mask = 64'h0F0F0F0F00000000;
defparam \db_system_spwulight_b|counter~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N17
dffeas \db_system_spwulight_b|counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~11_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[5] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N18
cyclonev_lcell_comb \db_system_spwulight_b|Add0~45 (
// Equation(s):
// \db_system_spwulight_b|Add0~45_sumout = SUM(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 ))
// \db_system_spwulight_b|Add0~46 = CARRY(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~42 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~45_sumout ),
.cout(\db_system_spwulight_b|Add0~46 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~45 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~45 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~45 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N3
cyclonev_lcell_comb \db_system_spwulight_b|counter~12 (
// Equation(s):
// \db_system_spwulight_b|counter~12_combout = ( \db_system_spwulight_b|Add0~45_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~45_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~12 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~12 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N5
dffeas \db_system_spwulight_b|counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~12_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[6] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N21
cyclonev_lcell_comb \db_system_spwulight_b|Add0~29 (
// Equation(s):
// \db_system_spwulight_b|Add0~29_sumout = SUM(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 ))
// \db_system_spwulight_b|Add0~30 = CARRY(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|counter [7]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~46 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~29_sumout ),
.cout(\db_system_spwulight_b|Add0~30 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~29 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~29 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N9
cyclonev_lcell_comb \db_system_spwulight_b|counter~8 (
// Equation(s):
// \db_system_spwulight_b|counter~8_combout = ( !\KEY[1]~input_o & ( \db_system_spwulight_b|Add0~29_sumout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|Add0~29_sumout ),
.datae(gnd),
.dataf(!\KEY[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~8 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~8 .lut_mask = 64'h00FF00FF00000000;
defparam \db_system_spwulight_b|counter~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N11
dffeas \db_system_spwulight_b|counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~8_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[7] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N24
cyclonev_lcell_comb \db_system_spwulight_b|Add0~33 (
// Equation(s):
// \db_system_spwulight_b|Add0~33_sumout = SUM(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 ))
// \db_system_spwulight_b|Add0~34 = CARRY(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|counter [8]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~30 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~33_sumout ),
.cout(\db_system_spwulight_b|Add0~34 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~33 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~33 .lut_mask = 64'h0000FFFF000000FF;
defparam \db_system_spwulight_b|Add0~33 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N57
cyclonev_lcell_comb \db_system_spwulight_b|counter~9 (
// Equation(s):
// \db_system_spwulight_b|counter~9_combout = ( \db_system_spwulight_b|Add0~33_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~9 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~9 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N59
dffeas \db_system_spwulight_b|counter[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~9_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [8]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[8] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N27
cyclonev_lcell_comb \db_system_spwulight_b|Add0~9 (
// Equation(s):
// \db_system_spwulight_b|Add0~9_sumout = SUM(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 ))
// \db_system_spwulight_b|Add0~10 = CARRY(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~34 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~9_sumout ),
.cout(\db_system_spwulight_b|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~9 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N48
cyclonev_lcell_comb \db_system_spwulight_b|counter~3 (
// Equation(s):
// \db_system_spwulight_b|counter~3_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~9_sumout )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(!\db_system_spwulight_b|Add0~9_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~3 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~3 .lut_mask = 64'h0A0A0A0A0A0A0A0A;
defparam \db_system_spwulight_b|counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N50
dffeas \db_system_spwulight_b|counter[9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~3_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [9]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[9] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N30
cyclonev_lcell_comb \db_system_spwulight_b|Add0~13 (
// Equation(s):
// \db_system_spwulight_b|Add0~13_sumout = SUM(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 ))
// \db_system_spwulight_b|Add0~14 = CARRY(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~13_sumout ),
.cout(\db_system_spwulight_b|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~13 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N51
cyclonev_lcell_comb \db_system_spwulight_b|counter~4 (
// Equation(s):
// \db_system_spwulight_b|counter~4_combout = ( \db_system_spwulight_b|Add0~13_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~4 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~4 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N53
dffeas \db_system_spwulight_b|counter[10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~4_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [10]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[10] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N33
cyclonev_lcell_comb \db_system_spwulight_b|Add0~17 (
// Equation(s):
// \db_system_spwulight_b|Add0~17_sumout = SUM(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 ))
// \db_system_spwulight_b|Add0~18 = CARRY(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [11]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~17_sumout ),
.cout(\db_system_spwulight_b|Add0~18 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~17 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~17 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N42
cyclonev_lcell_comb \db_system_spwulight_b|counter~5 (
// Equation(s):
// \db_system_spwulight_b|counter~5_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~17_sumout )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(!\db_system_spwulight_b|Add0~17_sumout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~5 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~5 .lut_mask = 64'h00AA00AA00AA00AA;
defparam \db_system_spwulight_b|counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N44
dffeas \db_system_spwulight_b|counter[11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~5_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [11]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[11] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N36
cyclonev_lcell_comb \db_system_spwulight_b|Add0~21 (
// Equation(s):
// \db_system_spwulight_b|Add0~21_sumout = SUM(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 ))
// \db_system_spwulight_b|Add0~22 = CARRY(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [12]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~18 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~21_sumout ),
.cout(\db_system_spwulight_b|Add0~22 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~21 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~21 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N45
cyclonev_lcell_comb \db_system_spwulight_b|counter~6 (
// Equation(s):
// \db_system_spwulight_b|counter~6_combout = ( \db_system_spwulight_b|Add0~21_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~6 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~6 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N47
dffeas \db_system_spwulight_b|counter[12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~6_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [12]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[12] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N39
cyclonev_lcell_comb \db_system_spwulight_b|Add0~25 (
// Equation(s):
// \db_system_spwulight_b|Add0~25_sumout = SUM(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 ))
// \db_system_spwulight_b|Add0~26 = CARRY(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [13]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~22 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~25_sumout ),
.cout(\db_system_spwulight_b|Add0~26 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~25 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~25 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N54
cyclonev_lcell_comb \db_system_spwulight_b|counter~7 (
// Equation(s):
// \db_system_spwulight_b|counter~7_combout = ( \db_system_spwulight_b|Add0~25_sumout & ( !\KEY[1]~input_o ) )
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~25_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~7 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~7 .lut_mask = 64'h00000000AAAAAAAA;
defparam \db_system_spwulight_b|counter~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N56
dffeas \db_system_spwulight_b|counter[13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~7_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [13]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[13] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[13] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N42
cyclonev_lcell_comb \db_system_spwulight_b|Add0~1 (
// Equation(s):
// \db_system_spwulight_b|Add0~1_sumout = SUM(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 ))
// \db_system_spwulight_b|Add0~2 = CARRY(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [14]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~26 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~1_sumout ),
.cout(\db_system_spwulight_b|Add0~2 ),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~1 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N27
cyclonev_lcell_comb \db_system_spwulight_b|counter~0 (
// Equation(s):
// \db_system_spwulight_b|counter~0_combout = ( \db_system_spwulight_b|Add0~1_sumout & ( !\KEY[1]~input_o ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\db_system_spwulight_b|Add0~1_sumout ),
.dataf(!\KEY[1]~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~0 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~0 .lut_mask = 64'h0000FFFF00000000;
defparam \db_system_spwulight_b|counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N29
dffeas \db_system_spwulight_b|counter[14] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~0_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [14]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[14] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[14] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X46_Y1_N45
cyclonev_lcell_comb \db_system_spwulight_b|Add0~5 (
// Equation(s):
// \db_system_spwulight_b|Add0~5_sumout = SUM(( \db_system_spwulight_b|counter [15] ) + ( GND ) + ( \db_system_spwulight_b|Add0~2 ))
.dataa(gnd),
.datab(gnd),
.datac(!\db_system_spwulight_b|counter [15]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\db_system_spwulight_b|Add0~2 ),
.sharein(gnd),
.combout(),
.sumout(\db_system_spwulight_b|Add0~5_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|Add0~5 .extended_lut = "off";
defparam \db_system_spwulight_b|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;
defparam \db_system_spwulight_b|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N36
cyclonev_lcell_comb \db_system_spwulight_b|counter~2 (
// Equation(s):
// \db_system_spwulight_b|counter~2_combout = ( \db_system_spwulight_b|Add0~5_sumout & ( !\KEY[1]~input_o ) )
.dataa(gnd),
.datab(gnd),
.datac(!\KEY[1]~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|Add0~5_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|counter~2 .extended_lut = "off";
defparam \db_system_spwulight_b|counter~2 .lut_mask = 64'h00000000F0F0F0F0;
defparam \db_system_spwulight_b|counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N38
dffeas \db_system_spwulight_b|counter[15] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|counter~2_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|counter[0]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|counter [15]),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|counter[15] .is_wysiwyg = "true";
defparam \db_system_spwulight_b|counter[15] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N18
cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~0 (
// Equation(s):
// \db_system_spwulight_b|aux_pb~0_combout = ( \db_system_spwulight_b|LessThan0~1_combout ) # ( !\db_system_spwulight_b|LessThan0~1_combout & ( ((!\db_system_spwulight_b|LessThan0~0_combout ) # ((\db_system_spwulight_b|counter [14]) # (\KEY[1]~input_o )))
// # (\db_system_spwulight_b|counter [15]) ) )
.dataa(!\db_system_spwulight_b|counter [15]),
.datab(!\db_system_spwulight_b|LessThan0~0_combout ),
.datac(!\KEY[1]~input_o ),
.datad(!\db_system_spwulight_b|counter [14]),
.datae(gnd),
.dataf(!\db_system_spwulight_b|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|aux_pb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|aux_pb~0 .extended_lut = "off";
defparam \db_system_spwulight_b|aux_pb~0 .lut_mask = 64'hDFFFDFFFFFFFFFFF;
defparam \db_system_spwulight_b|aux_pb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N34
dffeas \db_system_spwulight_b|PB_down (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|PB_down~0_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|aux_pb~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|PB_down~q ),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|PB_down .is_wysiwyg = "true";
defparam \db_system_spwulight_b|PB_down .power_up = "low";
// synopsys translate_on
// Location: PLLREFCLKSELECT_X68_Y7_N0
cyclonev_pll_refclk_select \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT (
.adjpllin(gnd),
.cclk(gnd),
.coreclkin(gnd),
.extswitch(gnd),
.iqtxrxclkin(gnd),
.plliqclkin(gnd),
.rxiqclkin(gnd),
.clkin({gnd,gnd,gnd,\FPGA_CLK1_50~input_o }),
.refiqclk(2'b00),
.clk0bad(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ),
.clk1bad(),
.clkout(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),
.extswitchbuf(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),
.pllclksel());
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_auto_clk_sw_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_edge = "both_edges";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_sw_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_sw_dly = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_0_src = "clk_0";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_1_src = "clk_1";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_manu_clk_sw_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_sw_refclk_src = "clk_0";
// synopsys translate_on
// Location: MLABCELL_X47_Y1_N30
cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~1 (
// Equation(s):
// \db_system_spwulight_b|aux_pb~1_combout = !\KEY[1]~input_o
.dataa(!\KEY[1]~input_o ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\db_system_spwulight_b|aux_pb~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \db_system_spwulight_b|aux_pb~1 .extended_lut = "off";
defparam \db_system_spwulight_b|aux_pb~1 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \db_system_spwulight_b|aux_pb~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X47_Y1_N32
dffeas \db_system_spwulight_b|aux_pb (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\db_system_spwulight_b|aux_pb~1_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\db_system_spwulight_b|aux_pb~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\db_system_spwulight_b|aux_pb~q ),
.prn(vcc));
// synopsys translate_off
defparam \db_system_spwulight_b|aux_pb .is_wysiwyg = "true";
defparam \db_system_spwulight_b|aux_pb .power_up = "low";
// synopsys translate_on
// Location: FRACTIONALPLL_X68_Y1_N0
cyclonev_fractional_pll \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll (
.coreclkfb(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),
.ecnc1test(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),
.ecnc2test(gnd),
.fbclkfpll(gnd),
.lvdsfbin(gnd),
.nresync(!\db_system_spwulight_b|aux_pb~q ),
.pfden(vcc),
.refclkin(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),
.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
.shiftdonein(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),
.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),
.zdb(gnd),
.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),
.fbclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),
.fblvdsout(),
.lock(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.mcntout(),
.plniotribuf(),
.shiftdoneout(),
.tclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),
.mhi(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ),
.vcoph(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ));
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .dsm_accumulator_reset_value = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .forcelock = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .mimic_fbclk_type = "none";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .nreset_invert = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .output_clock_frequency = "400.0 mhz";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_atb = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_bwctrl = 4000;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cmp_buf_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_comp = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_current = 10;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ctrl_override_setting = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_dither = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_out_sel = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_reset = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_bypass = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_test_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_enable = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_1 = "glb";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_2 = "m_cnt";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_carry_out = 32;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division_string = "1";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_value_ready = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lf_testen = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_cfg = 25;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_test = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_bypass_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_coarse_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_fine_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_hi_div = 4;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_in_src = "ph_mux_clk";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_lo_div = 4;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_odd_div_duty_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_ph_mux_prst = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_prst = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_bypass_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_coarse_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_fine_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_hi_div = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_lo_div = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_odd_div_duty_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ref_buf_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_reg_boost = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_regulator_bypass = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ripplecap_ctrl = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_slf_rst = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_mux_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_sel = "n_src";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_test_enable = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testdn_enable = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testup_enable = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_unlock_fltr_cfg = 2;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_div = 2;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph0_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph1_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph2_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph3_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph4_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph5_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph6_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph7_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vctrl_test_voltage = 750;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .reference_clock_frequency = "100.0 mhz";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_atb = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_output = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_atb = "disable";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_output = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccm1g_tap = 2;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccr_pd = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vcodiv_override = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .fractional_pll_index = 0;
// synopsys translate_on
// Location: PLLRECONFIG_X68_Y5_N0
cyclonev_pll_reconfig \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG (
.atpgmode(gnd),
.clk(gnd),
.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),
.fpllcsrtest(gnd),
.iocsrclkin(gnd),
.iocsrdatain(gnd),
.iocsren(gnd),
.iocsrrstn(gnd),
.mdiodis(vcc),
.phaseen(gnd),
.read(gnd),
.rstn(vcc),
.scanen(gnd),
.sershiftload(vcc),
.shiftdonei(gnd),
.updn(gnd),
.write(gnd),
.addr(6'b000000),
.byteen(2'b00),
.cntsel(5'b00000),
.din(16'b0000000000000000),
.mhi({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4],
\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0]}),
.blockselect(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ),
.iocsrdataout(),
.iocsrenbuf(),
.iocsrrstnbuf(),
.phasedone(),
.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
.shiftenm(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),
.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),
.dout(),
.dprioout(),
.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ));
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG .fractional_pll_index = 0;
// synopsys translate_on
// Location: PLLOUTPUTCOUNTER_X68_Y2_N1
cyclonev_pll_output_counter \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter (
.cascadein(gnd),
.nen0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),
.shift0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),
.shiftdone0i(gnd),
.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2]),
.tclk0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),
.up0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),
.vco0ph({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3],
\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0]}),
.cascadeout(\u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire [0]),
.divclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),
.shiftdone0o());
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_coarse_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_fine_dly = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_in_src = "ph_mux_clk";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_ph_mux_prst = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_prst = 1;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .cnt_fpll_src = "fpll_0";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_bypass_en = "true";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_hi_div = 256;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_lo_div = 256;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_odd_div_even_duty_en = "false";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .duty_cycle = 50;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_clock_frequency = "400.0 mhz";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .phase_shift = "0 ps";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .fractional_pll_index = 0;
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_counter_index = 2;
// synopsys translate_on
// Location: CLKCTRL_G11
cyclonev_clkena \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 (
.inclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),
.ena(vcc),
.outclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.enaout());
// synopsys translate_off
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .clock_type = "global clock";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .disable_mode = "low";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_mode = "always enabled";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_power_up = "high";
defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .test_syn = "high";
// synopsys translate_on
// Location: LABCELL_X27_Y1_N15
cyclonev_lcell_comb \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (
// Equation(s):
// \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y1_N17
dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y1_N14
dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y1_N38
dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";
// synopsys translate_on
// Location: CLKCTRL_G6
cyclonev_clkena \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (
.inclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.ena(vcc),
.outclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.enaout());
// synopsys translate_off
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .clock_type = "global clock";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .disable_mode = "low";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_mode = "always enabled";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_power_up = "high";
defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .test_syn = "high";
// synopsys translate_on
// Location: FF_X23_Y19_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y18_N52
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y20_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y23_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y25_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N54
cyclonev_lcell_comb \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (
// Equation(s):
// \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: HPSINTERFACECLOCKSRESETS_X32_Y50_N111
cyclonev_hps_interface_clocks_resets \u0|hps_0|fpga_interfaces|clocks_resets (
.f2h_cold_rst_req_n(vcc),
.f2h_dbg_rst_req_n(vcc),
.f2h_pending_rst_ack(vcc),
.f2h_periph_ref_clk(gnd),
.f2h_sdram_ref_clk(gnd),
.f2h_warm_rst_req_n(vcc),
.ptp_ref_clk(gnd),
.h2f_cold_rst_n(\u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ),
.h2f_pending_rst_req_n(),
.h2f_rst_n(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),
.h2f_user0_clk(),
.h2f_user1_clk(),
.h2f_user2_clk());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user0_clk_freq = 100;
defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user1_clk_freq = 100;
defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user2_clk_freq = 100;
// synopsys translate_on
// Location: CLKCTRL_G10
cyclonev_clkena \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 (
.inclk(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),
.ena(vcc),
.outclk(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
.enaout());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .clock_type = "global clock";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .disable_mode = "low";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_mode = "always enabled";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_power_up = "high";
defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .test_syn = "high";
// synopsys translate_on
// Location: FF_X30_Y32_N56
dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y32_N59
dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),
.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y32_N17
dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),
.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";
defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout = ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|rsp_mux_001|src_payload [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N55
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout = !\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY
// [0] & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N20
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y22_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout & ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y29_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y21_N1
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal7~0_combout = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal7~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal7~0 .lut_mask = 64'h00AA00AA00AA00AA;
defparam \u0|mm_interconnect_0|router_001|Equal7~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal10~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal10~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal7~0_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal10~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router_001|Equal10~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N28
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal10~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// \u0|mm_interconnect_0|router_001|Equal10~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(!\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .lut_mask = 64'h0000330000003333;
defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N1
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter
// [0] & \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter
// [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) )
// )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y17_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0])))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0707070707000700;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h1F1F1F1F00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]))))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] $ (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout )) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h731F731F731F731F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h1111111111111111;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h00005F5F00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFF8F807F70;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )
// # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0AF50AF54EE44EE4;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y17_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0A00F5FF4E44E4EE;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h01DD01DD00CC00CC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) ) )
// ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) )
// ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) ) )
// )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000F0F50005F0F5;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA50FA50;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFAC5CAC5C;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & (
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h030003FF030003FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF0F000F00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y17_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h202F202F707F707F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000B78484B7;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33CC33CCCCCCCCCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y17_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h00000F0F00F00FFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q
// ))))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000A5CC0FCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0000000035C53ACA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000000033005050;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N31
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h5505550555555555;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000CC0CCC0C;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66CC66CCCCCCCCCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000003000300;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y17_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h330033FF330033FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y17_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout
// )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0F0E0F0E0F000F00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout
// & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0])) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0303CFCF01016767;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y17_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )
// ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) )
// ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FF550003FF57;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y19_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &
// ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C0C0C0C000C000C;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y19_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y19_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y19_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~3 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~3_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~3 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|router_001|Equal1~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal2~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal2~0_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal2~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal2~1 .lut_mask = 64'h0000000000550055;
defparam \u0|mm_interconnect_0|router_001|Equal2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout
// & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]
// & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 .lut_mask = 64'hFFFF800088118000;
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N38
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0] &
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout )) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 .lut_mask = 64'h000F000F00050005;
defparam \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y18_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .lut_mask = 64'h0000000055550000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal12~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal12~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// (\u0|mm_interconnect_0|router_001|Equal2~0_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal12~0 .lut_mask = 64'h0000000100000000;
defparam \u0|mm_interconnect_0|router_001|Equal12~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N25
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21] & ( \u0|mm_interconnect_0|router_001|Equal12~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21] & ( \u0|mm_interconnect_0|router_001|Equal12~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .lut_mask = 64'h0000000033003333;
defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h50A050A05CAC5CAC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y21_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h4040B0B0404FB0BF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) # (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY
// [0] & ( (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~4 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~4_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|mm_interconnect_0|router_001|Equal1~2_combout
// & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~4 .lut_mask = 64'h0000000000020000;
defparam \u0|mm_interconnect_0|router_001|Equal1~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~5 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~5_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~5 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|router_001|Equal1~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N56
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .lut_mask = 64'h0000000044044404;
defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y29_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant
// [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y17_N2
dffeas \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1_combout = (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout & !\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0F000F000F000F00;
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N32
dffeas \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N59
dffeas \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q &
// !\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N23
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] )
// )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFCCCC0000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N38
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y20_N14
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y20_N47
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y20_N59
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout & !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5450105055550000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF0003AAAB;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N32
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N8
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .lut_mask = 64'hAFAFAFAF00000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h01FF01FF01010101;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )
// # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CF33CF30CC30CC;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y17_N32
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $
// (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h33C333C333AA33AA;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFD85072FA;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y17_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]))
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) # (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h5555AAAA3030FCFC;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y17_N11
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N25
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [6] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h5303AFFF5000ACFC;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8080000000000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))))
// # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00AE00AE04AE04AE;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N44
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y20_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h2220222022002200;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ) #
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h5F5F5F5F50505050;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) # (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F550F0F0F1D0F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )
// ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h04EE04EE00AA00AA;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N47
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ((((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// ))))) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
// # ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h087FFFFF087F000F;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]
// & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000110011;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N11
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y20_N40
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000003F003F00;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00F000F000FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]))))) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0])) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00F500F5313B313B;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N47
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout )) ) ) #
// ( !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFAFAFAFAF0FAF0FA;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N56
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h04AE04AEAE04AE04;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0005F0F5C0C53035;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N32
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [4] & ( ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2])) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF3FFF3FF0C000C00;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAAAFAAAF00050005;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]
// & !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0000C0C000000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h0AA00AA01BB11BB1;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N14
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y20_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~10 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .lut_mask = 64'h0000000000000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~2 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N26
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~6 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ))
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .lut_mask = 64'h000000000000FFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N59
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~13 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~14 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ))
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N5
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~17 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~18 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .lut_mask = 64'h0303030303030303;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N2
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~21 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~22 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N20
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~25 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~26 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~26 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N23
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~29 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~26 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~30 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~26 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~26 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .lut_mask = 64'h0303030303030303;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N50
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~33 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~34 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N53
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] &
// (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] & !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]))) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .lut_mask = 64'h8000000000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~37 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add1~38 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ))
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .lut_mask = 64'h0303030303030303;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N32
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y10_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~41 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N33
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .lut_mask = 64'h0000000033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N35
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & (
// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & (\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ))) ) ) ) # (
// !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & (\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout &
// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) )
.dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 .lut_mask = 64'h0011001000110000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .lut_mask = 64'h000000000F0F0F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N11
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y10_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &
// (((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1])) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & (
// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ((!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]) # (!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ))) ) ) ) # (
// \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] & (
// !\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ) ) )
.dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .lut_mask = 64'h5555555555505515;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y10_N38
dffeas \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem~0feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem~0feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem~0feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~0feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem~0feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem~0feeder .shared_arith = "off";
// synopsys translate_on
// Location: IOIBUF_X51_Y0_N1
cyclonev_io_ibuf \sin_a~input (
.i(sin_a),
.ibar(\sin_a(n) ),
.dynamicterminationcontrol(gnd),
.o(\sin_a~input_o ));
// synopsys translate_off
defparam \sin_a~input .bus_hold = "false";
defparam \sin_a~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X46_Y0_N1
cyclonev_io_ibuf \din_a~input (
.i(din_a),
.ibar(\din_a(n) ),
.dynamicterminationcontrol(gnd),
.o(\din_a~input_o ));
// synopsys translate_off
defparam \din_a~input .bus_hold = "false";
defparam \din_a~input .simulate_z_as = "z";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|got_bit_internal~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout = ( \din_a~input_o & ( !\db_system_spwulight_b|aux_pb~q ) ) # ( !\din_a~input_o & ( (!\db_system_spwulight_b|aux_pb~q & \sin_a~input_o ) ) )
.dataa(gnd),
.datab(!\db_system_spwulight_b|aux_pb~q ),
.datac(!\sin_a~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(!\din_a~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal~0 .lut_mask = 64'h0C0C0C0CCCCCCCCC;
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N50
dffeas \A_SPW_TOP|SPW|FSM|got_bit_internal (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|got_bit_internal .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~1_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|SPW|FSM|Add2~2 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~1_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~2 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~1 .lut_mask = 64'h0000000000003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~21_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~26 ))
// \A_SPW_TOP|SPW|FSM|Add2~22 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~26 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~26 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~21_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~22 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~17_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~22 ))
// \A_SPW_TOP|SPW|FSM|Add2~18 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~22 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~22 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~17_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~18 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~17 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~17 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~4_combout = ( \A_SPW_TOP|SPW|FSM|Add2~17_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|tx_reset_n~0_combout & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datab(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~17_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~4 .lut_mask = 64'h0000000000008C00;
defparam \A_SPW_TOP|SPW|FSM|after850ns~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N5
dffeas \A_SPW_TOP|SPW|FSM|after850ns[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~4_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~13_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~18 ))
// \A_SPW_TOP|SPW|FSM|Add2~14 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~18 ))
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~18 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~13_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~14 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~13 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~3_combout = ( \A_SPW_TOP|SPW|FSM|Add2~13_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (!\A_SPW_TOP|tx_reset_n~0_combout & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datab(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datad(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~13_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~3 .lut_mask = 64'h000000000000A200;
defparam \A_SPW_TOP|SPW|FSM|after850ns~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N26
dffeas \A_SPW_TOP|SPW|FSM|after850ns[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~3_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~9_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~14 ))
// \A_SPW_TOP|SPW|FSM|Add2~10 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~14 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~14 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~9_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~10 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~9 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~5_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~10 ))
// \A_SPW_TOP|SPW|FSM|Add2~6 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~10 ))
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~10 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~5_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~6 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~5 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~45 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~45_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~6 ))
// \A_SPW_TOP|SPW|FSM|Add2~46 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~6 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [7]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~6 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~45_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~46 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~45 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~45 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add2~45 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~11_combout = ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( \A_SPW_TOP|SPW|FSM|after850ns [6] & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout & (!\A_SPW_TOP|tx_reset_n~0_combout &
// \A_SPW_TOP|SPW|FSM|Add2~45_sumout ))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( !\A_SPW_TOP|SPW|FSM|after850ns [6] & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (!\A_SPW_TOP|tx_reset_n~0_combout & \A_SPW_TOP|SPW|FSM|Add2~45_sumout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datab(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Add2~45_sumout ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~11 .lut_mask = 64'h000000A000000020;
defparam \A_SPW_TOP|SPW|FSM|after850ns~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N35
dffeas \A_SPW_TOP|SPW|FSM|after850ns[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~11_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~41 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~41_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~46 ))
// \A_SPW_TOP|SPW|FSM|Add2~42 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~46 ))
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [8]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~46 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~41_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~42 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~41 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add2~41 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~10 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~10_combout = ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( !\A_SPW_TOP|tx_reset_n~0_combout & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (\A_SPW_TOP|SPW|FSM|Add2~41_sumout & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datab(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Add2~41_sumout ),
.datad(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datae(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.dataf(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~10 .lut_mask = 64'h00000A0200000000;
defparam \A_SPW_TOP|SPW|FSM|after850ns~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N59
dffeas \A_SPW_TOP|SPW|FSM|after850ns[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~10_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~37 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~37_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~42 ))
// \A_SPW_TOP|SPW|FSM|Add2~38 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~42 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~42 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~37_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~38 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~37 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~37 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|LessThan2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|LessThan2~1_combout = ( \A_SPW_TOP|SPW|FSM|after850ns [6] & ( !\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|LessThan2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|LessThan2~1 .lut_mask = 64'h00000000F0F0F0F0;
defparam \A_SPW_TOP|SPW|FSM|LessThan2~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~9_combout = ( \A_SPW_TOP|SPW|FSM|Add2~37_sumout & ( !\A_SPW_TOP|SPW|FSM|LessThan2~1_combout & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (!\db_system_spwulight_b|aux_pb~q & (\A_SPW_TOP|SPW|FSM|Equal1~1_combout &
// \A_SPW_TOP|SPW|FSM|state_fsm.run~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datab(!\db_system_spwulight_b|aux_pb~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~37_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~9 .lut_mask = 64'h0000000800000000;
defparam \A_SPW_TOP|SPW|FSM|after850ns~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N38
dffeas \A_SPW_TOP|SPW|FSM|after850ns[9] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~9_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~33 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~33_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~38 ))
// \A_SPW_TOP|SPW|FSM|Add2~34 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~38 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~38 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~33_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~34 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~33 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~8 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~8_combout = ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( \A_SPW_TOP|SPW|FSM|Add2~33_sumout & ( (!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q & (!\db_system_spwulight_b|aux_pb~q &
// !\A_SPW_TOP|SPW|FSM|got_bit_internal~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datac(!\db_system_spwulight_b|aux_pb~q ),
.datad(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add2~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~8 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|after850ns~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N47
dffeas \A_SPW_TOP|SPW|FSM|after850ns[10] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~8_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [10]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~29 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~29_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [11] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~34 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [11]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~34 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~29_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~29 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~29 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~7 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~7_combout = ( \A_SPW_TOP|SPW|FSM|Add2~29_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q &
// !\db_system_spwulight_b|aux_pb~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|LessThan2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datac(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datad(!\db_system_spwulight_b|aux_pb~q ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~29_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~7 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|after850ns~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N44
dffeas \A_SPW_TOP|SPW|FSM|after850ns[11] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~7_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [11]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal1~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal1~1_combout = ( !\A_SPW_TOP|SPW|FSM|after850ns [11] & ( !\A_SPW_TOP|SPW|FSM|after850ns [10] & ( (!\A_SPW_TOP|SPW|FSM|after850ns [7] & (!\A_SPW_TOP|SPW|FSM|after850ns [9] & !\A_SPW_TOP|SPW|FSM|after850ns [8])) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [7]),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [9]),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|FSM|after850ns [8]),
.datae(!\A_SPW_TOP|SPW|FSM|after850ns [11]),
.dataf(!\A_SPW_TOP|SPW|FSM|after850ns [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal1~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal1~1 .lut_mask = 64'h8800000000000000;
defparam \A_SPW_TOP|SPW|FSM|Equal1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~0_combout = ( \A_SPW_TOP|SPW|FSM|Add2~1_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|tx_reset_n~0_combout & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datab(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datad(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~1_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~0 .lut_mask = 64'h00000000000080C0;
defparam \A_SPW_TOP|SPW|FSM|after850ns~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N14
dffeas \A_SPW_TOP|SPW|FSM|after850ns[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~0_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add2~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add2~25_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after850ns [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~2 ))
// \A_SPW_TOP|SPW|FSM|Add2~26 = CARRY(( \A_SPW_TOP|SPW|FSM|after850ns [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add2~2 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add2~2 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add2~25_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add2~26 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add2~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add2~25 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add2~25 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~6_combout = ( \A_SPW_TOP|SPW|FSM|Add2~25_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (!\A_SPW_TOP|tx_reset_n~0_combout & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datab(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~25_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~6 .lut_mask = 64'h000000000000A020;
defparam \A_SPW_TOP|SPW|FSM|after850ns~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N29
dffeas \A_SPW_TOP|SPW|FSM|after850ns[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~6_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~5_combout = ( \A_SPW_TOP|SPW|FSM|Add2~21_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|tx_reset_n~0_combout & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datab(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datad(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~21_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~5 .lut_mask = 64'h00000000000080C0;
defparam \A_SPW_TOP|SPW|FSM|after850ns~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N2
dffeas \A_SPW_TOP|SPW|FSM|after850ns[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~5_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|LessThan2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|LessThan2~0_combout = ( \A_SPW_TOP|SPW|FSM|after850ns [1] & ( \A_SPW_TOP|SPW|FSM|after850ns [4] & ( (!\A_SPW_TOP|SPW|FSM|after850ns [2] & (!\A_SPW_TOP|SPW|FSM|after850ns [5] & !\A_SPW_TOP|SPW|FSM|after850ns [3])) ) ) ) # (
// !\A_SPW_TOP|SPW|FSM|after850ns [1] & ( \A_SPW_TOP|SPW|FSM|after850ns [4] & ( (!\A_SPW_TOP|SPW|FSM|after850ns [5] & (!\A_SPW_TOP|SPW|FSM|after850ns [3] & ((!\A_SPW_TOP|SPW|FSM|after850ns [2]) # (!\A_SPW_TOP|SPW|FSM|after850ns [0])))) ) ) ) # (
// \A_SPW_TOP|SPW|FSM|after850ns [1] & ( !\A_SPW_TOP|SPW|FSM|after850ns [4] & ( !\A_SPW_TOP|SPW|FSM|after850ns [5] ) ) ) # ( !\A_SPW_TOP|SPW|FSM|after850ns [1] & ( !\A_SPW_TOP|SPW|FSM|after850ns [4] & ( !\A_SPW_TOP|SPW|FSM|after850ns [5] ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
.datad(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
.datae(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
.dataf(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|LessThan2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|LessThan2~0 .lut_mask = 64'hCCCCCCCCC0808080;
defparam \A_SPW_TOP|SPW|FSM|LessThan2~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~1_combout = ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( !\A_SPW_TOP|tx_reset_n~0_combout & ( (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & (\A_SPW_TOP|SPW|FSM|Add2~5_sumout & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datab(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Add2~5_sumout ),
.datad(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datae(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.dataf(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~1 .lut_mask = 64'h00000A0200000000;
defparam \A_SPW_TOP|SPW|FSM|after850ns~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N20
dffeas \A_SPW_TOP|SPW|FSM|after850ns[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|after850ns~1_combout ),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y9_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after850ns~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after850ns~2_combout = ( \A_SPW_TOP|SPW|FSM|Add2~9_sumout & ( \A_SPW_TOP|SPW|FSM|Equal1~1_combout & ( (!\A_SPW_TOP|tx_reset_n~0_combout & (!\A_SPW_TOP|SPW|FSM|got_bit_internal~q & ((!\A_SPW_TOP|SPW|FSM|after850ns [6]) #
// (\A_SPW_TOP|SPW|FSM|LessThan2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datab(!\A_SPW_TOP|tx_reset_n~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|LessThan2~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|got_bit_internal~q ),
.datae(!\A_SPW_TOP|SPW|FSM|Add2~9_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after850ns~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after850ns~2 .lut_mask = 64'h0000000000008C00;
defparam \A_SPW_TOP|SPW|FSM|after850ns~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y9_N17
dffeas \A_SPW_TOP|SPW|FSM|after850ns[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after850ns~2_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after850ns [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after850ns[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after850ns[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal1~0_combout = ( \A_SPW_TOP|SPW|FSM|after850ns [2] & ( \A_SPW_TOP|SPW|FSM|after850ns [6] & ( (!\A_SPW_TOP|SPW|FSM|after850ns [5] & (\A_SPW_TOP|SPW|FSM|after850ns [4] & (!\A_SPW_TOP|SPW|FSM|after850ns [3] &
// !\A_SPW_TOP|SPW|FSM|after850ns [1]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after850ns [5]),
.datab(!\A_SPW_TOP|SPW|FSM|after850ns [4]),
.datac(!\A_SPW_TOP|SPW|FSM|after850ns [3]),
.datad(!\A_SPW_TOP|SPW|FSM|after850ns [1]),
.datae(!\A_SPW_TOP|SPW|FSM|after850ns [2]),
.dataf(!\A_SPW_TOP|SPW|FSM|after850ns [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal1~0 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|Equal1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always3~0_combout = LCELL(( \din_a~input_o & ( !\sin_a~input_o ) ) # ( !\din_a~input_o & ( \sin_a~input_o ) ))
.dataa(gnd),
.datab(gnd),
.datac(!\sin_a~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(!\din_a~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always3~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|SPW|RX|always3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~1_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|SPW|FSM|Add1~2 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~1_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~2 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~1 .lut_mask = 64'h0000000000000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~25_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~2 ))
// \A_SPW_TOP|SPW|FSM|Add1~26 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~2 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~2 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~25_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~26 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~25 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~25 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~1_combout = (\A_SPW_TOP|SPW|FSM|after64us [0] & \A_SPW_TOP|SPW|FSM|Equal2~0_combout )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datab(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~1 .lut_mask = 64'h1111111111111111;
defparam \A_SPW_TOP|SPW|FSM|Equal2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~21_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~26 ))
// \A_SPW_TOP|SPW|FSM|Add1~22 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~26 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~26 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~21_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~22 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~6_combout = ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( \A_SPW_TOP|SPW|FSM|Add1~21_sumout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) #
// (!\A_SPW_TOP|SPW|FSM|after64us [0])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add1~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~6 .lut_mask = 64'h000000000000AAFE;
defparam \A_SPW_TOP|SPW|FSM|after64us~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N23
dffeas \A_SPW_TOP|SPW|FSM|after64us[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~6_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~17_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~22 ))
// \A_SPW_TOP|SPW|FSM|Add1~18 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~22 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [3]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~22 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~17_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~18 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~17 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~5_combout = ( \A_SPW_TOP|SPW|FSM|Add1~17_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) #
// (!\A_SPW_TOP|SPW|FSM|after64us [0])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~17_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~5 .lut_mask = 64'h000000000000AFAE;
defparam \A_SPW_TOP|SPW|FSM|after64us~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N20
dffeas \A_SPW_TOP|SPW|FSM|after64us[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~5_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~13_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~18 ))
// \A_SPW_TOP|SPW|FSM|Add1~14 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~18 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~18 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~13_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~14 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~4_combout = ( \A_SPW_TOP|SPW|FSM|Add1~13_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [0]) #
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~13_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~4 .lut_mask = 64'h000000000000AAFE;
defparam \A_SPW_TOP|SPW|FSM|after64us~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N47
dffeas \A_SPW_TOP|SPW|FSM|after64us[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~4_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~9_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~14 ))
// \A_SPW_TOP|SPW|FSM|Add1~10 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~14 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~9_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~10 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~3_combout = ( \A_SPW_TOP|SPW|FSM|Add1~9_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [0]) #
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~9_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~3 .lut_mask = 64'h000000000000AFAE;
defparam \A_SPW_TOP|SPW|FSM|after64us~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N44
dffeas \A_SPW_TOP|SPW|FSM|after64us[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~3_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~5_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~10 ))
// \A_SPW_TOP|SPW|FSM|Add1~6 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~10 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~5_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~6 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~5 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~2_combout = ( \A_SPW_TOP|SPW|FSM|Add1~5_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [0]) #
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~5_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~2 .lut_mask = 64'h000000000000AAFE;
defparam \A_SPW_TOP|SPW|FSM|after64us~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N59
dffeas \A_SPW_TOP|SPW|FSM|after64us[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~2_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~45 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~45_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~6 ))
// \A_SPW_TOP|SPW|FSM|Add1~46 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [7]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~6 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~45_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~46 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~45 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~45 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~45 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~41 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~41_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~46 ))
// \A_SPW_TOP|SPW|FSM|Add1~42 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~46 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~46 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~41_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~42 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~41 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~41 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~11_combout = ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( \A_SPW_TOP|SPW|FSM|after64us [0] & ( (\A_SPW_TOP|SPW|FSM|Add1~41_sumout & ((!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout &
// !\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( !\A_SPW_TOP|SPW|FSM|after64us [0] & ( (\A_SPW_TOP|SPW|FSM|Add1~41_sumout & ((!\A_SPW_TOP|SPW|FSM|after64us [9]) # (\A_SPW_TOP|SPW|FSM|Equal2~3_combout )))
// ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Add1~41_sumout ),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~11 .lut_mask = 64'h0000313100003130;
defparam \A_SPW_TOP|SPW|FSM|after64us~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N50
dffeas \A_SPW_TOP|SPW|FSM|after64us[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~11_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~29 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~29_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~42 ))
// \A_SPW_TOP|SPW|FSM|Add1~30 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~42 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~42 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~29_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~30 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~29 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~37 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~37_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~30 ))
// \A_SPW_TOP|SPW|FSM|Add1~38 = CARRY(( \A_SPW_TOP|SPW|FSM|after64us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~30 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~30 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~37_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add1~38 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~37 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add1~37 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~10 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~10_combout = ( \A_SPW_TOP|SPW|FSM|Add1~37_sumout & ( (\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & !\A_SPW_TOP|SPW|FSM|Equal2~1_combout )))) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|Add1~37_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~10 .lut_mask = 64'h0000000031303130;
defparam \A_SPW_TOP|SPW|FSM|after64us~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N29
dffeas \A_SPW_TOP|SPW|FSM|after64us[10] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~10_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [10]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add1~33 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add1~33_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after64us [11] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add1~38 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [11]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add1~38 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add1~33_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add1~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add1~33 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add1~33 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~9_combout = ( \A_SPW_TOP|SPW|FSM|Add1~33_sumout & ( (\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & !\A_SPW_TOP|SPW|FSM|Equal2~1_combout )))) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|Add1~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~9 .lut_mask = 64'h0000000031303130;
defparam \A_SPW_TOP|SPW|FSM|after64us~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N26
dffeas \A_SPW_TOP|SPW|FSM|after64us[11] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~9_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [11]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[11] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N33
cyclonev_lcell_comb \m_x|counter_neg[0]~feeder (
// Equation(s):
// \m_x|counter_neg[0]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|counter_neg[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|counter_neg[0]~feeder .extended_lut = "off";
defparam \m_x|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \m_x|counter_neg[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N57
cyclonev_lcell_comb \m_x|Selector4~0 (
// Equation(s):
// \m_x|Selector4~0_combout = ( \m_x|always2~1_combout & ( \m_x|counter_neg [1] ) ) # ( !\m_x|always2~1_combout & ( \m_x|counter_neg [2] ) )
.dataa(gnd),
.datab(!\m_x|counter_neg [2]),
.datac(!\m_x|counter_neg [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|always2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector4~0 .extended_lut = "off";
defparam \m_x|Selector4~0 .lut_mask = 64'h333333330F0F0F0F;
defparam \m_x|Selector4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N17
dffeas \m_x|counter_neg[2] (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|Selector4~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|counter_neg [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[2] .is_wysiwyg = "true";
defparam \m_x|counter_neg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N30
cyclonev_lcell_comb \m_x|Selector1~0 (
// Equation(s):
// \m_x|Selector1~0_combout = ( \m_x|counter_neg [3] & ( \m_x|counter_neg [0] & ( \m_x|counter_neg [5] ) ) ) # ( !\m_x|counter_neg [3] & ( \m_x|counter_neg [0] & ( (!\m_x|counter_neg [1] & ((!\m_x|counter_neg [2] & (\m_x|counter_neg [4])) #
// (\m_x|counter_neg [2] & ((\m_x|counter_neg [5]))))) # (\m_x|counter_neg [1] & (((\m_x|counter_neg [5])))) ) ) ) # ( \m_x|counter_neg [3] & ( !\m_x|counter_neg [0] & ( \m_x|counter_neg [5] ) ) ) # ( !\m_x|counter_neg [3] & ( !\m_x|counter_neg [0] & (
// \m_x|counter_neg [5] ) ) )
.dataa(!\m_x|counter_neg [4]),
.datab(!\m_x|counter_neg [5]),
.datac(!\m_x|counter_neg [1]),
.datad(!\m_x|counter_neg [2]),
.datae(!\m_x|counter_neg [3]),
.dataf(!\m_x|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector1~0 .extended_lut = "off";
defparam \m_x|Selector1~0 .lut_mask = 64'h3333333353333333;
defparam \m_x|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N14
dffeas \m_x|counter_neg[5] (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|Selector1~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|counter_neg [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[5] .is_wysiwyg = "true";
defparam \m_x|counter_neg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N30
cyclonev_lcell_comb \m_x|Selector2~0 (
// Equation(s):
// \m_x|Selector2~0_combout = ( !\m_x|counter_neg [5] & ( (!\m_x|counter_neg [2] & (!\m_x|counter_neg [1] & \m_x|counter_neg [0])) ) )
.dataa(!\m_x|counter_neg [2]),
.datab(!\m_x|counter_neg [1]),
.datac(!\m_x|counter_neg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector2~0 .extended_lut = "off";
defparam \m_x|Selector2~0 .lut_mask = 64'h0808080800000000;
defparam \m_x|Selector2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N9
cyclonev_lcell_comb \m_x|Selector2~1 (
// Equation(s):
// \m_x|Selector2~1_combout = ( \m_x|counter_neg [4] & ( (!\m_x|Selector2~0_combout ) # (\m_x|counter_neg [3]) ) ) # ( !\m_x|counter_neg [4] & ( (\m_x|counter_neg [3] & \m_x|Selector2~0_combout ) ) )
.dataa(gnd),
.datab(!\m_x|counter_neg [3]),
.datac(!\m_x|Selector2~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|counter_neg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector2~1 .extended_lut = "off";
defparam \m_x|Selector2~1 .lut_mask = 64'h03030303F3F3F3F3;
defparam \m_x|Selector2~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N53
dffeas \m_x|counter_neg[4] (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|Selector2~1_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|counter_neg [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[4] .is_wysiwyg = "true";
defparam \m_x|counter_neg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N54
cyclonev_lcell_comb \m_x|WideOr7~0 (
// Equation(s):
// \m_x|WideOr7~0_combout = ( !\m_x|counter_neg [2] & ( \m_x|counter_neg [5] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [1] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [3]))) ) ) ) # ( \m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & (
// (\m_x|counter_neg [0] & (!\m_x|counter_neg [1] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [3]))) ) ) ) # ( !\m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & ( (!\m_x|counter_neg [0] & (!\m_x|counter_neg [1] & (!\m_x|counter_neg [4] & !\m_x|counter_neg
// [3]))) # (\m_x|counter_neg [0] & ((!\m_x|counter_neg [1] & (!\m_x|counter_neg [4] $ (!\m_x|counter_neg [3]))) # (\m_x|counter_neg [1] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [3])))) ) ) )
.dataa(!\m_x|counter_neg [0]),
.datab(!\m_x|counter_neg [1]),
.datac(!\m_x|counter_neg [4]),
.datad(!\m_x|counter_neg [3]),
.datae(!\m_x|counter_neg [2]),
.dataf(!\m_x|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|WideOr7~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|WideOr7~0 .extended_lut = "off";
defparam \m_x|WideOr7~0 .lut_mask = 64'h9440400040000000;
defparam \m_x|WideOr7~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y7_N35
dffeas \m_x|counter_neg[0] (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|counter_neg[0]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|WideOr7~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|counter_neg [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[0] .is_wysiwyg = "true";
defparam \m_x|counter_neg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N6
cyclonev_lcell_comb \m_x|Selector5~0 (
// Equation(s):
// \m_x|Selector5~0_combout = ( !\m_x|counter_neg [5] & ( (\m_x|counter_neg [0] & \m_x|counter_neg [2]) ) )
.dataa(!\m_x|counter_neg [0]),
.datab(gnd),
.datac(!\m_x|counter_neg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector5~0 .extended_lut = "off";
defparam \m_x|Selector5~0 .lut_mask = 64'h0505050500000000;
defparam \m_x|Selector5~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N54
cyclonev_lcell_comb \m_x|Selector0~0 (
// Equation(s):
// \m_x|Selector0~0_combout = ( \m_x|counter_neg [5] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [2] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [3]))) ) ) # ( !\m_x|counter_neg [5] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & !\m_x|counter_neg
// [3])) ) )
.dataa(!\m_x|counter_neg [0]),
.datab(!\m_x|counter_neg [2]),
.datac(!\m_x|counter_neg [4]),
.datad(!\m_x|counter_neg [3]),
.datae(gnd),
.dataf(!\m_x|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector0~0 .extended_lut = "off";
defparam \m_x|Selector0~0 .lut_mask = 64'h5000500040004000;
defparam \m_x|Selector0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N27
cyclonev_lcell_comb \m_x|Equal1~0 (
// Equation(s):
// \m_x|Equal1~0_combout = ( !\m_x|counter_neg [4] & ( !\m_x|counter_neg [3] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|counter_neg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|counter_neg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Equal1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Equal1~0 .extended_lut = "off";
defparam \m_x|Equal1~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \m_x|Equal1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N11
dffeas \m_x|control_bit_found (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_bit_found~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_bit_found .is_wysiwyg = "true";
defparam \m_x|control_bit_found .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N9
cyclonev_lcell_comb \m_x|Selector0~1 (
// Equation(s):
// \m_x|Selector0~1_combout = ( \m_x|control_bit_found~q & ( \m_x|is_control~q & ( (!\m_x|counter_neg [5] & ((!\m_x|counter_neg [2]) # (\m_x|counter_neg [1]))) # (\m_x|counter_neg [5] & (\m_x|counter_neg [1] & !\m_x|counter_neg [2])) ) ) ) # (
// !\m_x|control_bit_found~q & ( \m_x|is_control~q & ( (!\m_x|counter_neg [5] & (!\m_x|counter_neg [1] $ (\m_x|counter_neg [2]))) # (\m_x|counter_neg [5] & (\m_x|counter_neg [1] & !\m_x|counter_neg [2])) ) ) ) # ( \m_x|control_bit_found~q & (
// !\m_x|is_control~q & ( (!\m_x|counter_neg [5] & (\m_x|counter_neg [1] & !\m_x|counter_neg [2])) ) ) )
.dataa(!\m_x|counter_neg [5]),
.datab(!\m_x|counter_neg [1]),
.datac(!\m_x|counter_neg [2]),
.datad(gnd),
.datae(!\m_x|control_bit_found~q ),
.dataf(!\m_x|is_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector0~1 .extended_lut = "off";
defparam \m_x|Selector0~1 .lut_mask = 64'h000020209292B2B2;
defparam \m_x|Selector0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N36
cyclonev_lcell_comb \m_x|Selector0~2 (
// Equation(s):
// \m_x|Selector0~2_combout = ( \m_x|counter_neg [0] & ( (!\m_x|Selector0~0_combout & (\m_x|is_control~q )) # (\m_x|Selector0~0_combout & (((\m_x|Equal1~0_combout & \m_x|Selector0~1_combout )))) ) ) # ( !\m_x|counter_neg [0] & ( (\m_x|is_control~q &
// !\m_x|Selector0~0_combout ) ) )
.dataa(!\m_x|is_control~q ),
.datab(!\m_x|Selector0~0_combout ),
.datac(!\m_x|Equal1~0_combout ),
.datad(!\m_x|Selector0~1_combout ),
.datae(gnd),
.dataf(!\m_x|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector0~2 .extended_lut = "off";
defparam \m_x|Selector0~2 .lut_mask = 64'h4444444444474447;
defparam \m_x|Selector0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N38
dffeas \m_x|is_control (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|Selector0~2_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|is_control~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|is_control .is_wysiwyg = "true";
defparam \m_x|is_control .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N42
cyclonev_lcell_comb \m_x|Selector3~0 (
// Equation(s):
// \m_x|Selector3~0_combout = ( \m_x|counter_neg [3] & ( \m_x|counter_neg [1] & ( (!\m_x|Selector2~0_combout ) # (\m_x|counter_neg [4]) ) ) ) # ( \m_x|counter_neg [3] & ( !\m_x|counter_neg [1] & ( (!\m_x|Selector2~0_combout ) # (((\m_x|Selector5~0_combout
// & !\m_x|is_control~q )) # (\m_x|counter_neg [4])) ) ) ) # ( !\m_x|counter_neg [3] & ( !\m_x|counter_neg [1] & ( (\m_x|Selector5~0_combout & (!\m_x|counter_neg [4] & !\m_x|is_control~q )) ) ) )
.dataa(!\m_x|Selector5~0_combout ),
.datab(!\m_x|Selector2~0_combout ),
.datac(!\m_x|counter_neg [4]),
.datad(!\m_x|is_control~q ),
.datae(!\m_x|counter_neg [3]),
.dataf(!\m_x|counter_neg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector3~0 .extended_lut = "off";
defparam \m_x|Selector3~0 .lut_mask = 64'h5000DFCF0000CFCF;
defparam \m_x|Selector3~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N56
dffeas \m_x|counter_neg[3] (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|Selector3~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|counter_neg [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[3] .is_wysiwyg = "true";
defparam \m_x|counter_neg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N18
cyclonev_lcell_comb \m_x|always2~1 (
// Equation(s):
// \m_x|always2~1_combout = (!\m_x|counter_neg [3] & (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [5])))
.dataa(!\m_x|counter_neg [3]),
.datab(!\m_x|counter_neg [0]),
.datac(!\m_x|counter_neg [4]),
.datad(!\m_x|counter_neg [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always2~1 .extended_lut = "off";
defparam \m_x|always2~1 .lut_mask = 64'h2000200020002000;
defparam \m_x|always2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N21
cyclonev_lcell_comb \m_x|Selector5~1 (
// Equation(s):
// \m_x|Selector5~1_combout = ( !\m_x|counter_neg [4] & ( (!\m_x|counter_neg [3] & ((!\m_x|counter_neg [0] & (!\m_x|counter_neg [2] & !\m_x|counter_neg [5])) # (\m_x|counter_neg [0] & ((!\m_x|counter_neg [2]) # (!\m_x|counter_neg [5]))))) ) )
.dataa(!\m_x|counter_neg [3]),
.datab(!\m_x|counter_neg [0]),
.datac(!\m_x|counter_neg [2]),
.datad(!\m_x|counter_neg [5]),
.datae(gnd),
.dataf(!\m_x|counter_neg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector5~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector5~1 .extended_lut = "off";
defparam \m_x|Selector5~1 .lut_mask = 64'hA220A22000000000;
defparam \m_x|Selector5~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N24
cyclonev_lcell_comb \m_x|Selector5~2 (
// Equation(s):
// \m_x|Selector5~2_combout = ( !\m_x|counter_neg [2] & ( \m_x|counter_neg [5] & ( \m_x|counter_neg [0] ) ) ) # ( \m_x|counter_neg [2] & ( !\m_x|counter_neg [5] & ( (\m_x|is_control~q & \m_x|counter_neg [0]) ) ) ) # ( !\m_x|counter_neg [2] & (
// !\m_x|counter_neg [5] & ( !\m_x|counter_neg [0] ) ) )
.dataa(gnd),
.datab(!\m_x|is_control~q ),
.datac(!\m_x|counter_neg [0]),
.datad(gnd),
.datae(!\m_x|counter_neg [2]),
.dataf(!\m_x|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector5~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector5~2 .extended_lut = "off";
defparam \m_x|Selector5~2 .lut_mask = 64'hF0F003030F0F0000;
defparam \m_x|Selector5~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N42
cyclonev_lcell_comb \m_x|Selector5~3 (
// Equation(s):
// \m_x|Selector5~3_combout = ( \m_x|Equal1~0_combout & ( \m_x|counter_neg [2] & ( (!\m_x|Selector5~1_combout & (((\m_x|counter_neg [1])))) # (\m_x|Selector5~1_combout & (((\m_x|always2~1_combout & \m_x|counter_neg [1])) # (\m_x|Selector5~2_combout )))
// ) ) ) # ( !\m_x|Equal1~0_combout & ( \m_x|counter_neg [2] & ( (\m_x|counter_neg [1] & ((!\m_x|Selector5~1_combout ) # (\m_x|always2~1_combout ))) ) ) ) # ( \m_x|Equal1~0_combout & ( !\m_x|counter_neg [2] & ( (!\m_x|Selector5~1_combout &
// (\m_x|counter_neg [1])) # (\m_x|Selector5~1_combout & ((\m_x|Selector5~2_combout ))) ) ) ) # ( !\m_x|Equal1~0_combout & ( !\m_x|counter_neg [2] & ( (!\m_x|Selector5~1_combout & \m_x|counter_neg [1]) ) ) )
.dataa(!\m_x|always2~1_combout ),
.datab(!\m_x|Selector5~1_combout ),
.datac(!\m_x|counter_neg [1]),
.datad(!\m_x|Selector5~2_combout ),
.datae(!\m_x|Equal1~0_combout ),
.dataf(!\m_x|counter_neg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Selector5~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Selector5~3 .extended_lut = "off";
defparam \m_x|Selector5~3 .lut_mask = 64'h0C0C0C3F0D0D0D3F;
defparam \m_x|Selector5~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N50
dffeas \m_x|counter_neg[1] (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|Selector5~3_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|counter_neg [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|counter_neg[1] .is_wysiwyg = "true";
defparam \m_x|counter_neg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N3
cyclonev_lcell_comb \m_x|always2~0 (
// Equation(s):
// \m_x|always2~0_combout = LCELL(( \m_x|always2~1_combout & ( (!\m_x|counter_neg [1] & (\m_x|counter_neg [2] & \m_x|always3~0_combout )) ) ))
.dataa(!\m_x|counter_neg [1]),
.datab(gnd),
.datac(!\m_x|counter_neg [2]),
.datad(!\m_x|always3~0_combout ),
.datae(gnd),
.dataf(!\m_x|always2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always2~0 .extended_lut = "off";
defparam \m_x|always2~0 .lut_mask = 64'h00000000000A000A;
defparam \m_x|always2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N6
cyclonev_lcell_comb \m_x|always1~0 (
// Equation(s):
// \m_x|always1~0_combout = LCELL(( !\m_x|always3~0_combout & ( (\m_x|counter_neg [2] & (!\m_x|counter_neg [1] & \m_x|always2~1_combout )) ) ))
.dataa(gnd),
.datab(!\m_x|counter_neg [2]),
.datac(!\m_x|counter_neg [1]),
.datad(!\m_x|always2~1_combout ),
.datae(gnd),
.dataf(!\m_x|always3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always1~0 .extended_lut = "off";
defparam \m_x|always1~0 .lut_mask = 64'h0030003000000000;
defparam \m_x|always1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N41
dffeas \m_x|bit_c_0 (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_c_0~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_0 .is_wysiwyg = "true";
defparam \m_x|bit_c_0 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N27
cyclonev_lcell_comb \m_x|bit_c_2~feeder (
// Equation(s):
// \m_x|bit_c_2~feeder_combout = ( \m_x|bit_c_0~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_c_0~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|bit_c_2~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|bit_c_2~feeder .extended_lut = "off";
defparam \m_x|bit_c_2~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_c_2~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N28
dffeas \m_x|bit_c_2 (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|bit_c_2~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_c_2~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_2 .is_wysiwyg = "true";
defparam \m_x|bit_c_2 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y8_N12
cyclonev_lcell_comb \m_x|control_r[2]~feeder (
// Equation(s):
// \m_x|control_r[2]~feeder_combout = ( \m_x|bit_c_2~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_c_2~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_r[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_r[2]~feeder .extended_lut = "off";
defparam \m_x|control_r[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y8_N14
dffeas \m_x|control_r[2] (
.clk(\m_x|always1~0_combout ),
.d(\m_x|control_r[2]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[2] .is_wysiwyg = "true";
defparam \m_x|control_r[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y8_N6
cyclonev_lcell_comb \m_x|control_p_r[2]~feeder (
// Equation(s):
// \m_x|control_p_r[2]~feeder_combout = ( \m_x|control_r [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control_r [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_p_r[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_p_r[2]~feeder .extended_lut = "off";
defparam \m_x|control_p_r[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_p_r[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y8_N7
dffeas \m_x|control_p_r[2] (
.clk(\m_x|always2~0_combout ),
.d(\m_x|control_p_r[2]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_p_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[2] .is_wysiwyg = "true";
defparam \m_x|control_p_r[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N39
cyclonev_lcell_comb \m_x|ready_control_p_r~0 (
// Equation(s):
// \m_x|ready_control_p_r~0_combout = ( \m_x|ready_control_p_r~q & ( (\m_x|always2~0_combout ) # (\m_x|always1~0_combout ) ) ) # ( !\m_x|ready_control_p_r~q & ( (\m_x|is_control~q & ((\m_x|always2~0_combout ) # (\m_x|always1~0_combout ))) ) )
.dataa(!\m_x|is_control~q ),
.datab(gnd),
.datac(!\m_x|always1~0_combout ),
.datad(!\m_x|always2~0_combout ),
.datae(gnd),
.dataf(!\m_x|ready_control_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|ready_control_p_r~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|ready_control_p_r~0 .extended_lut = "off";
defparam \m_x|ready_control_p_r~0 .lut_mask = 64'h055505550FFF0FFF;
defparam \m_x|ready_control_p_r~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N59
dffeas \m_x|ready_control_p_r (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|ready_control_p_r~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|ready_control_p_r~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|ready_control_p_r .is_wysiwyg = "true";
defparam \m_x|ready_control_p_r .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N56
dffeas \m_x|control[2] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control_p_r [2]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control[2] .is_wysiwyg = "true";
defparam \m_x|control[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N26
dffeas \m_x|control_l_r[2] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [2]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_l_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[2] .is_wysiwyg = "true";
defparam \m_x|control_l_r[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N48
cyclonev_lcell_comb \m_x|info[12]~feeder (
// Equation(s):
// \m_x|info[12]~feeder_combout = ( \m_x|control_l_r [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control_l_r [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|info[12]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|info[12]~feeder .extended_lut = "off";
defparam \m_x|info[12]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|info[12]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N15
cyclonev_lcell_comb \m_x|Equal1~1 (
// Equation(s):
// \m_x|Equal1~1_combout = ( !\m_x|counter_neg [1] & ( (\m_x|counter_neg [0] & !\m_x|counter_neg [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|counter_neg [0]),
.datad(!\m_x|counter_neg [2]),
.datae(gnd),
.dataf(!\m_x|counter_neg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|Equal1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|Equal1~1 .extended_lut = "off";
defparam \m_x|Equal1~1 .lut_mask = 64'h0F000F0000000000;
defparam \m_x|Equal1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N12
cyclonev_lcell_comb \m_x|ready_data_p (
// Equation(s):
// \m_x|ready_data_p~combout = LCELL(( \m_x|always3~0_combout & ( (\m_x|Equal1~0_combout & (\m_x|Equal1~1_combout & (!\m_x|always2~0_combout & \m_x|counter_neg [5]))) ) ))
.dataa(!\m_x|Equal1~0_combout ),
.datab(!\m_x|Equal1~1_combout ),
.datac(!\m_x|always2~0_combout ),
.datad(!\m_x|counter_neg [5]),
.datae(gnd),
.dataf(!\m_x|always3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|ready_data_p~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|ready_data_p .extended_lut = "off";
defparam \m_x|ready_data_p .lut_mask = 64'h0000000000100010;
defparam \m_x|ready_data_p .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N51
cyclonev_lcell_comb \m_x|ready_data_p_r~0 (
// Equation(s):
// \m_x|ready_data_p_r~0_combout = ( \m_x|counter_neg [5] & ( (\m_x|Equal1~0_combout & (\m_x|Equal1~1_combout & !\m_x|always3~0_combout )) ) )
.dataa(!\m_x|Equal1~0_combout ),
.datab(gnd),
.datac(!\m_x|Equal1~1_combout ),
.datad(!\m_x|always3~0_combout ),
.datae(gnd),
.dataf(!\m_x|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|ready_data_p_r~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|ready_data_p_r~0 .extended_lut = "off";
defparam \m_x|ready_data_p_r~0 .lut_mask = 64'h0000000005000500;
defparam \m_x|ready_data_p_r~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N24
cyclonev_lcell_comb \m_x|ready_data_p_r~1 (
// Equation(s):
// \m_x|ready_data_p_r~1_combout = ( \m_x|ready_data_p_r~0_combout & ( (!\m_x|is_control~q & (((!\m_x|always1~0_combout ) # (\m_x|ready_data_p~combout )))) # (\m_x|is_control~q & (\m_x|ready_data_p_r~q & ((!\m_x|always1~0_combout ) #
// (\m_x|ready_data_p~combout )))) ) ) # ( !\m_x|ready_data_p_r~0_combout & ( (\m_x|ready_data_p~combout & ((!\m_x|is_control~q ) # (\m_x|ready_data_p_r~q ))) ) )
.dataa(!\m_x|is_control~q ),
.datab(!\m_x|ready_data_p_r~q ),
.datac(!\m_x|ready_data_p~combout ),
.datad(!\m_x|always1~0_combout ),
.datae(gnd),
.dataf(!\m_x|ready_data_p_r~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|ready_data_p_r~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|ready_data_p_r~1 .extended_lut = "off";
defparam \m_x|ready_data_p_r~1 .lut_mask = 64'h0B0B0B0BBB0BBB0B;
defparam \m_x|ready_data_p_r~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N29
dffeas \m_x|ready_data_p_r (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|ready_data_p_r~1_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|ready_data_p_r~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|ready_data_p_r .is_wysiwyg = "true";
defparam \m_x|ready_data_p_r .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N48
cyclonev_lcell_comb \m_x|data_l_r[7]~0 (
// Equation(s):
// \m_x|data_l_r[7]~0_combout = (!\m_x|ready_data_p_r~q & !\m_x|ready_control_p_r~q )
.dataa(gnd),
.datab(!\m_x|ready_data_p_r~q ),
.datac(!\m_x|ready_control_p_r~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data_l_r[7]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data_l_r[7]~0 .extended_lut = "off";
defparam \m_x|data_l_r[7]~0 .lut_mask = 64'hC0C0C0C0C0C0C0C0;
defparam \m_x|data_l_r[7]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N49
dffeas \m_x|info[12] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|info[12]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [12]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[12] .is_wysiwyg = "true";
defparam \m_x|info[12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N0
cyclonev_lcell_comb \u0|data_info|read_mux_out[12] (
// Equation(s):
// \u0|data_info|read_mux_out [12] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \m_x|info [12] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\m_x|info [12]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [12]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[12] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[12] .lut_mask = 64'h00000000CCCC0000;
defparam \u0|data_info|read_mux_out[12] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N2
dffeas \u0|data_info|readdata[12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [12]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [12]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[12] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[12] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y10_N17
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [12]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y18_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout &
// !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h330033003F0F3F0F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [0]) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h050405040F0C0F0C;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .lut_mask = 64'h03030303F3F3F3F3;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFF00FF00FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout = (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout &
// ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ))) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]))))
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .lut_mask = 64'h0145014501450145;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N23
dffeas \m_x|bit_c_1 (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_c_1~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_1 .is_wysiwyg = "true";
defparam \m_x|bit_c_1 .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y7_N46
dffeas \m_x|bit_c_3 (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|bit_c_1~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_c_3~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_c_3 .is_wysiwyg = "true";
defparam \m_x|bit_c_3 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y8_N33
cyclonev_lcell_comb \m_x|control_r[3]~feeder (
// Equation(s):
// \m_x|control_r[3]~feeder_combout = ( \m_x|bit_c_3~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_c_3~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_r[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_r[3]~feeder .extended_lut = "off";
defparam \m_x|control_r[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y8_N35
dffeas \m_x|control_r[3] (
.clk(\m_x|always1~0_combout ),
.d(\m_x|control_r[3]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[3] .is_wysiwyg = "true";
defparam \m_x|control_r[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y8_N33
cyclonev_lcell_comb \m_x|control_p_r[3]~feeder (
// Equation(s):
// \m_x|control_p_r[3]~feeder_combout = ( \m_x|control_r [3] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control_r [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_p_r[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_p_r[3]~feeder .extended_lut = "off";
defparam \m_x|control_p_r[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_p_r[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y8_N34
dffeas \m_x|control_p_r[3] (
.clk(\m_x|always2~0_combout ),
.d(\m_x|control_p_r[3]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_p_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[3] .is_wysiwyg = "true";
defparam \m_x|control_p_r[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N35
dffeas \m_x|control[3] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control_p_r [3]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control[3] .is_wysiwyg = "true";
defparam \m_x|control[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N22
dffeas \m_x|control_l_r[3] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [3]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_l_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[3] .is_wysiwyg = "true";
defparam \m_x|control_l_r[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X33_Y7_N52
dffeas \m_x|info[13] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control_l_r [3]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [13]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[13] .is_wysiwyg = "true";
defparam \m_x|info[13] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N21
cyclonev_lcell_comb \u0|data_info|read_mux_out[13] (
// Equation(s):
// \u0|data_info|read_mux_out [13] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \m_x|info [13] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\m_x|info [13]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [13]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[13] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[13] .lut_mask = 64'h00000000F0F00000;
defparam \u0|data_info|read_mux_out[13] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N23
dffeas \u0|data_info|readdata[13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [13]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [13]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[13] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[13] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y10_N32
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [13]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] &
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 .lut_mask = 64'h000F0303000F0303;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~34 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y23_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N50
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal13~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal13~0_combout = (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal13~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|router_001|Equal13~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal13~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal13~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal13~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal13~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal13~1 .lut_mask = 64'h0000000000000010;
defparam \u0|mm_interconnect_0|router_001|Equal13~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N53
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal13~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal13~1_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q
// )) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 .lut_mask = 64'h0500050005050505;
defparam \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y33_N1
dffeas \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal13~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .lut_mask = 64'h0000000011011101;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal5~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal5~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal5~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal5~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|router_001|Equal5~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|Equal5~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 .lut_mask = 64'h0000000004050405;
defparam \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q &
// !\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y30_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y32_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0030003030303030;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00000000F5F5F5F5;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55DF55DF55FF55FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y30_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h3030303030FF30FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAFAFAFAFAAAAAAAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 .lut_mask = 64'hFF00FF000F000F00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout =
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))))
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h54AE54AE54AE54AE;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2] $ (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) )
// # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h00FF00FFE44EE44E;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))
// ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))
// ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .lut_mask = 64'h0000FFFF8F807F70;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4])) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEAE54AE54;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) )
// ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .lut_mask = 64'h0500FFFAC5C03F3A;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N19
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y32_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y32_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h083B083B4C7F4C7F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4411441150500505;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q
// & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000E22E2E2E;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3C3CF0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66AA66AAAAAAAAAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000FC30FC30;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC0C0000000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q )))
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h000000003C553CAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000000003008B88;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N49
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000FF5FFF5F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000CC0CCC0C;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [66])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y32_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q & (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0F0E0F0E0A0A0A0A;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout & (((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0D0D0D0D02DF02DF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y30_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N49
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) # (!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFF0FFF0FF00FF00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N58
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h10DC10DCDC10DC10;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) #
// ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) )
// ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h2222DDDD000F000F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [4] $ (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3]))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h99AA99AAAAAAAAAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout
// & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hF0F3F0F300030003;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h2020202000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .lut_mask = 64'h0CC00CC01DD11DD1;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N31
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X9_Y34_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [6] & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) #
// ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) )
// # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h2222DDDD000F000F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout & (
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h40FF00FF00FF00FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) #
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00AE00EE00A20022;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )
// # ((\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF0005CCCD;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y30_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y30_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C080C080C000C00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) #
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hCCCCCCCCC8CCC8CC;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
// ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y30_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F030B0F0FCF4F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # (\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout &
// (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) #
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0C0C0C5D0C0C0C5D;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y30_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout
// )) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hEEEEEEEEAEAEAEAE;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) #
// ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// ) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )
// )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0050FAFA0000AAAA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )
// ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h01F301F300F000F0;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y32_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// )))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))
// ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
// # ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1B33FFFF1B330303;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 .lut_mask = 64'h000FFFFF0000FFF0;
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y31_N56
dffeas \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout )) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q & ((!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 .lut_mask = 64'hA8A8A8A8ABABABAB;
defparam \u0|mm_interconnect_0|cmd_mux_003|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y31_N44
dffeas \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 .lut_mask = 64'h5FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000030303030;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h030203020F0A0F0A;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid .lut_mask = 64'hCCC0CCC000000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal18~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal18~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal18~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal18~0 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|router_001|Equal18~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal18~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal18~1_combout = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout & ( \u0|mm_interconnect_0|router_001|Equal18~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal18~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal18~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal18~1 .lut_mask = 64'h0000000000000003;
defparam \u0|mm_interconnect_0|router_001|Equal18~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y31_N41
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal18~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal18~1_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// \u0|mm_interconnect_0|router_001|Equal18~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_ARVALID
// [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datae(!\u0|mm_interconnect_0|router_001|Equal18~1_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .lut_mask = 64'h000000AA000000FF;
defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000005000500;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y36_N14
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y36_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y36_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y36_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y36_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFAFAFAFAAAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y36_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [1] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'hC000000080000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0055005503570357;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y36_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000A0A0A0A;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N29
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y36_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000000005F5F5F5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0404040444444444;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h51BF51BF40AE40AE;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h2033DFFF2000DFCC;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h1DF31DF30CE20CE2;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y35_N31
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// ) # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h5033AFFF5000AFCC;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h01F501F500F000F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout
// )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout
// )) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout
// )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000AAAF0005AAAF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55BB55BB44AA44AA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h02570257A2F7A2F7;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q $ ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q $
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D78282D7;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666AAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q &
// ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )))) ) ) )
// # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q
// $ (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00B7003F0084000C;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000033330C0C3F3F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N59
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0033003344774477;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout = !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))))
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h6AAA6AAA6AAA6AAA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ) #
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A000A000A;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1040154515451040;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) )
// ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h1100000011005050;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N19
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X9_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000C0F0C0F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0080000000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y36_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFE0FFE0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])
// # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used
// [0] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ) )
// )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N8
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFFFF0F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0])) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h000F000C0F0F0C0C;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h000FFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y36_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] $
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h05F505F5A5FFA5FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y36_N35
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .lut_mask = 64'h0000000033FFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout
// )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]
// & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout $ (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h009C009C23BF23BF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y36_N46
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0404040444444444;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N14
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF30F030F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h30C030C03ACA3ACA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .lut_mask = 64'h3000C0F03505C5F5;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCF30CF30FF00FF00;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 .lut_mask = 64'hAAAFAAAF00050005;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N4
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout &
// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0AA00AA01BB11BB1;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ))
// # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
// )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h2020D0D0202FD0DF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2000FFFF0000FFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y36_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q
// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q
// & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q
// & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00004505AAAAEFAF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h020202020A0A0A0A;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00F000F000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( ((\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF00110F1F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y36_N19
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout =
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))))
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h080A080A080A080A;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'h22222222AA22AA22;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5505550550005000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) #
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout
// )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F0F0B0F0B0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y36_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hA0A0A0A020A00000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q
// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h5D555D5508000800;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hCCCC0000C0000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) ) ) ) # (
// \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ) #
// (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .lut_mask = 64'h0000FFAA0055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y34_N59
dffeas \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( !\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout
// & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) )
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & (
// !\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .lut_mask = 64'hF0F0F5F5F0F0A0A0;
defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y34_N53
dffeas \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal19~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal19~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( (\u0|mm_interconnect_0|router_001|Equal7~0_combout & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal19~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal19~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router_001|Equal19~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N46
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal19~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// \u0|mm_interconnect_0|router_001|Equal19~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_ARVALID
// [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .lut_mask = 64'h00000A0A00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y31_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFF88888888;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N29
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y34_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y34_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y34_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]
// & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N31
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y34_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )
// )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0055555500000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00000000AFAFAFAF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00330033F0F3F0F3;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'hCCCCCCCC00CC00CC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h3333CFCF3030CCCC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y34_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y34_N2
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFD5807F2A;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h04FE04FEAE54AE54;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y34_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y34_N19
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0300FFFCA3A05F5C;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8080000000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F02DF0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h3272327222222222;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y34_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000F4F40404F4F4;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y34_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE44EE44E;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y34_N29
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y34_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h00000F0F50505F5F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y34_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y34_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y34_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y34_N17
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h00AA55FF0A0A5F5F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y34_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2121111133003300;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q
// $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout
// )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0440155115510440;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000404011005140;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N49
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h4545454555555555;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3303330300000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )
// )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00A500A500CC0033;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y34_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0303CFCF0303CFCF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FCECFCEC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0504050455445544;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg
// [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg
// [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & (
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0CFF0CFF333F333F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .lut_mask = 64'h000000005FFF5FFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used
// [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55F755F755FF55FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout
// & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout
// & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h11DD11DD013D013D;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFF0FFF0F5F0F5F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N22
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h10BA10BABA10BA10;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y34_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])))) ) )
// ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])))) ) )
// ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0003F0F3A0A35053;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hFF00FF0077887788;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hFF03FF0300030003;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout &
// ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout
// $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0AA00AA01BB11BB1;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]))) ) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]))) ) ) )
// # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h0101F1F1F10101F1;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h33333333B3333333;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N2
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h2333200022222222;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001FF01;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N2
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00F800F800000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]) # ((!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F1F0F1F00110011;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0C00AAAA3FFFAFAF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &
// ( \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .lut_mask = 64'h00FF00FF30FC30FC;
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N34
dffeas \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (
// !\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .lut_mask = 64'hCCCCCCCCCCCC0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y34_N44
dffeas \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y34_N23
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] )
// ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [0] & ( (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]
// & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [1])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'h5FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000050505050;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .lut_mask = 64'hA0A0A0A080808080;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N47
dffeas \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal13~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal13~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (((\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [16] & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [19])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19])) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [19])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal13~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal13~0 .lut_mask = 64'h0A000A004E444E44;
defparam \u0|mm_interconnect_0|router|Equal13~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N47
dffeas \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )
// # ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .lut_mask = 64'h00003333FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y22_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y23_N43
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: HPSINTERFACEHPS2FPGA_X32_Y24_N111
cyclonev_hps_interface_hps2fpga \u0|hps_0|fpga_interfaces|hps2fpga (
.arready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ),
.awready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),
.bvalid(\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.rlast(\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
.rvalid(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
.wready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.bid({\u0|mm_interconnect_0|rsp_mux|src_data [116],\u0|mm_interconnect_0|rsp_mux|src_data [115],\u0|mm_interconnect_0|rsp_mux|src_data [114],\u0|mm_interconnect_0|rsp_mux|src_data [113],\u0|mm_interconnect_0|rsp_mux|src_data [112],\u0|mm_interconnect_0|rsp_mux|src_data [111],
\u0|mm_interconnect_0|rsp_mux|src_data [110],\u0|mm_interconnect_0|rsp_mux|src_data [109],\u0|mm_interconnect_0|rsp_mux|src_data [108],\u0|mm_interconnect_0|rsp_mux|src_data [107],\u0|mm_interconnect_0|rsp_mux|src_data [106],\u0|mm_interconnect_0|rsp_mux|src_data [105]}),
.bresp({gnd,gnd}),
.port_size_config({gnd,gnd}),
.rdata({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ,
\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ,
\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ,
\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout }),
.rid({\u0|mm_interconnect_0|rsp_mux_001|src_data [116],\u0|mm_interconnect_0|rsp_mux_001|src_data [115],\u0|mm_interconnect_0|rsp_mux_001|src_data [114],\u0|mm_interconnect_0|rsp_mux_001|src_data [113],\u0|mm_interconnect_0|rsp_mux_001|src_data [112],
\u0|mm_interconnect_0|rsp_mux_001|src_data [111],\u0|mm_interconnect_0|rsp_mux_001|src_data [110],\u0|mm_interconnect_0|rsp_mux_001|src_data [109],\u0|mm_interconnect_0|rsp_mux_001|src_data [108],\u0|mm_interconnect_0|rsp_mux_001|src_data [107],
\u0|mm_interconnect_0|rsp_mux_001|src_data [106],\u0|mm_interconnect_0|rsp_mux_001|src_data [105]}),
.rresp({gnd,gnd}),
.arvalid(\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.awvalid(\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
.bready(\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.rready(\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.wlast(\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.wvalid(\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
.araddr(\u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ),
.arburst(\u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ),
.arcache(),
.arid(\u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ),
.arlen(\u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ),
.arlock(),
.arprot(),
.arsize(\u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ),
.awaddr(\u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ),
.awburst(\u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ),
.awcache(),
.awid(\u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ),
.awlen(\u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ),
.awlock(),
.awprot(),
.awsize(\u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ),
.wdata(\u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ),
.wid(),
.wstrb(\u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ));
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|hps2fpga .data_width = 32;
// synopsys translate_on
// Location: LABCELL_X22_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARID [11] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [11] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[14] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal20~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .lut_mask = 64'h0000000010111011;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y19_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [16]) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3 .lut_mask = 64'h0A0A0A0A5F5F5F5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal15~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal15~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (((\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [16] & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17])) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal15~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal15~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal15~0 .lut_mask = 64'h300030003A0A3A0A;
defparam \u0|mm_interconnect_0|router|Equal15~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal15~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal15~1_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|router|Equal15~0_combout & \u0|mm_interconnect_0|router|Equal14~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal15~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal15~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal15~1 .lut_mask = 64'h0000000003030303;
defparam \u0|mm_interconnect_0|router|Equal15~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 .lut_mask = 64'h000000000C0C0C0C;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 .lut_mask = 64'h0033003300000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 .lut_mask = 64'h00CC00CC00000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & (
// (\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 .lut_mask = 64'h1000100033003300;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] &
// \u0|hps_0|fpga_interfaces|h2f_AWLEN [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 .lut_mask = 64'h00AA00AAAAAAAAAA;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & (
// (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3])) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3])) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 .lut_mask = 64'hAA00A000A0000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 .lut_mask = 64'h00CC00CC33FF33FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 .lut_mask = 64'h0000000088888888;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 .lut_mask = 64'h2222222200000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout = ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 .lut_mask = 64'hAA00AA0000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])) ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])) ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 .lut_mask = 64'h0000FC30000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [0] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])))) ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [0] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])))) ) + ( !VCC ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 .lut_mask = 64'h0000FAD8000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & (
// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & ((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & (
// ((\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 .lut_mask = 64'h4F4F0000B0B0FFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout = (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [0])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0])))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] &
// (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// ((((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ))))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout &
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout
// )))))) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datag(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 .lut_mask = 64'h10110F0FDFDD0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y30_N38
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1])) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1])) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 .lut_mask = 64'h0000FC3000005555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1] = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] .lut_mask = 64'h0000F0F000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits[1] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits
// [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1])) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits
// [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1])) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 .lut_mask = 64'h0000FF00000005AF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) #
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout )))) ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( ((\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 .lut_mask = 64'h020057558AAADFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y30_N26
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]))) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2])) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]))) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2])) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 .lut_mask = 64'h0000FF0000001D1D;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [2])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [2]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 .lut_mask = 64'h0000FF0000000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout & (
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # (
// \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout
// & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout )))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout & (
// (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 .lut_mask = 64'h0A0A028A5F5F57DF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y28_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 .lut_mask = 64'h0000F3C0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 .lut_mask = 64'h0000D8D8000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout & ( ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ) #
// (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout & (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout & (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1 .lut_mask = 64'h0020D0F00F2FDFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y30_N44
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 .lut_mask = 64'h0000F5A0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5])) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// ((\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5])) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 .lut_mask = 64'h0000E4E4000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 .lut_mask = 64'h0000F3C0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [5])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ))
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 .lut_mask = 64'h0000BB88000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN
// [3] & ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] &
// ((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) # ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & !\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 .lut_mask = 64'hEA80EA80A800A800;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [5]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// (((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout )) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout & \u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// (((\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout )) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 .lut_mask = 64'h05350505C5F5F5F5;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y30_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 .lut_mask = 64'h0000D8D8000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) )
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]))
// # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]))))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 .lut_mask = 64'h084C084C3B7F3B7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y30_N23
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]))) ) + (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 .lut_mask = 64'h0000F5A0000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) )
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]))
// # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]))))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 .lut_mask = 64'h084C084C3B7F3B7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y30_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 .lut_mask = 64'h0000F5A000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) )
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]))
// # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]))))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 .lut_mask = 64'h084C084C3B7F3B7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y30_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [9])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26
// ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [9])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26
// ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 .lut_mask = 64'h0000FFFF00002727;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [9])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) )
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]))
// # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]))))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 .lut_mask = 64'h084C084C3B7F3B7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y30_N11
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [10])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [10])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [10]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 .lut_mask = 64'h0000F5A000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [10])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [10])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [10]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 .lut_mask = 64'h082A082A5D7F5D7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N26
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42
// ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42
// ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 .lut_mask = 64'h0000FFFF00000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [11])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 .lut_mask = 64'h202A202A757F757F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N5
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 .lut_mask = 64'h0000F5A000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [12])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 .lut_mask = 64'h082A082A5D7F5D7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[12] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[12] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34
// ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34
// ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 .lut_mask = 64'h0000FFFF00000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [13])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [13])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 .lut_mask = 64'h082A082A5D7F5D7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N29
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[13] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[13] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[13] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [14])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [14])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ))
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 .lut_mask = 64'h0000CFC000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [14])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [14])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 .lut_mask = 64'h082A082A5D7F5D7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N14
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[14] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[14] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[14] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30
// ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30
// ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 .lut_mask = 64'h0000FFFF00000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15])))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0])
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [15])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]))))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 .lut_mask = 64'h207020702F7F2F7F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y29_N44
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[15] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[15] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[15] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~2 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~2_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [13] & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [15] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ))))) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datag(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal6~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|router|Equal6~2 .lut_mask = 64'h0101000500000000;
defparam \u0|mm_interconnect_0|router|Equal6~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~2 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q )) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [8] & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [9]
// & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ))
// ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] & ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [9] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q )) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [8] & ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]
// & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst
// [9])) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [8]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [9]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [8]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~2 .lut_mask = 64'hFFA000A000A000A0;
defparam \u0|mm_interconnect_0|router|Equal7~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [6] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [6] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [7])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst
// [6]))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [7]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [6]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [7]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~1 .lut_mask = 64'hEA40EA4040404040;
defparam \u0|mm_interconnect_0|router|Equal7~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~3 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [14] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [14] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [14]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [12]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [12]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [14]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~3 .lut_mask = 64'hEA40EA4040404040;
defparam \u0|mm_interconnect_0|router|Equal7~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~4 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [10] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [10]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [11]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [11]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~4 .lut_mask = 64'hCAC0CAC00A000A00;
defparam \u0|mm_interconnect_0|router|Equal7~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~0_combout = ( \u0|mm_interconnect_0|router|Equal13~0_combout & ( \u0|mm_interconnect_0|router|Equal7~4_combout & ( (\u0|mm_interconnect_0|router|Equal7~0_combout & (\u0|mm_interconnect_0|router|Equal7~2_combout &
// (\u0|mm_interconnect_0|router|Equal7~1_combout & \u0|mm_interconnect_0|router|Equal7~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal7~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal7~2_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~3_combout ),
.datae(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal6~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router|Equal6~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal6~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal6~1_combout = ( \u0|mm_interconnect_0|router|Equal6~0_combout & ( \u0|mm_interconnect_0|router|Equal6~2_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal6~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal6~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal6~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|router|Equal6~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[103]~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[103]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( \u0|mm_interconnect_0|router|Equal6~1_combout & ( (\u0|mm_interconnect_0|router|Equal7~6_combout
// & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( !\u0|mm_interconnect_0|router|Equal6~1_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ) #
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ) # (!\u0|mm_interconnect_0|router|Equal7~6_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( !\u0|mm_interconnect_0|router|Equal6~1_combout & ( (!\u0|mm_interconnect_0|router|Equal7~6_combout ) #
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout $ (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[103]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[103]~0 .lut_mask = 64'hFFB4FFFC00000018;
defparam \u0|mm_interconnect_0|router|src_data[103]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y27_N31
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal14~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal14~1_combout = ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( (\u0|mm_interconnect_0|router|Equal7~7_combout & \u0|mm_interconnect_0|router|Equal7~6_combout ) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal7~7_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal14~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal14~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal14~1 .lut_mask = 64'h0000050500000505;
defparam \u0|mm_interconnect_0|router|Equal14~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal21~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal21~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout & \u0|mm_interconnect_0|router|Equal7~6_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal21~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal21~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal21~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router|Equal21~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal20~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal20~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|router|Equal7~6_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal20~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal20~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal20~0 .lut_mask = 64'h0000000001000100;
defparam \u0|mm_interconnect_0|router|Equal20~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[102]~6 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[102]~6_combout = ( !\u0|mm_interconnect_0|router|Equal20~0_combout & ( (!\u0|mm_interconnect_0|router|Equal6~1_combout & (!\u0|mm_interconnect_0|router|Equal14~1_combout &
// !\u0|mm_interconnect_0|router|Equal21~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal21~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[102]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[102]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[102]~6 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|router|src_data[102]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y27_N23
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|src_data[102]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout = ( \u0|mm_interconnect_0|router|Equal14~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2] ) ) # ( !\u0|mm_interconnect_0|router|Equal14~1_combout
// & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2] $ (((!\u0|mm_interconnect_0|router|Equal20~0_combout & (!\u0|mm_interconnect_0|router|Equal6~1_combout & !\u0|mm_interconnect_0|router|Equal21~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [2]),
.datab(!\u0|mm_interconnect_0|router|Equal20~0_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal21~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 .lut_mask = 64'h6AAA6AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[100]~2 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[100]~2_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout $
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[100]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[100]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[100]~2 .lut_mask = 64'h0000000002010201;
defparam \u0|mm_interconnect_0|router|src_data[100]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[100]~3 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[100]~3_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout $
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[100]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[100]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[100]~3 .lut_mask = 64'h0000000000060006;
defparam \u0|mm_interconnect_0|router|src_data[100]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[100]~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[100]~1_combout = ( \u0|mm_interconnect_0|router|Equal6~2_combout & ( ((\u0|mm_interconnect_0|router|Equal7~6_combout & (\u0|mm_interconnect_0|router|Equal15~0_combout &
// \u0|mm_interconnect_0|router|Equal14~0_combout ))) # (\u0|mm_interconnect_0|router|Equal6~0_combout ) ) ) # ( !\u0|mm_interconnect_0|router|Equal6~2_combout & ( (\u0|mm_interconnect_0|router|Equal7~6_combout &
// (\u0|mm_interconnect_0|router|Equal15~0_combout & \u0|mm_interconnect_0|router|Equal14~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[100]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[100]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[100]~1 .lut_mask = 64'h0101010101FF01FF;
defparam \u0|mm_interconnect_0|router|src_data[100]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[100]~7 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[100]~7_combout = ( \u0|mm_interconnect_0|router|src_data[100]~1_combout & ( (!\u0|mm_interconnect_0|router|src_data[100]~2_combout ) # (\u0|mm_interconnect_0|router|src_data[100]~3_combout ) ) ) # (
// !\u0|mm_interconnect_0|router|src_data[100]~1_combout & ( \u0|mm_interconnect_0|router|src_data[100]~3_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|src_data[100]~3_combout ),
.datad(!\u0|mm_interconnect_0|router|src_data[100]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|src_data[100]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[100]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[100]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[100]~7 .lut_mask = 64'h0F0F0F0FFF0FFF0F;
defparam \u0|mm_interconnect_0|router|src_data[100]~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y29_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|src_data[100]~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[104]~9 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[104]~9_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( (\u0|mm_interconnect_0|router|Equal7~6_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[104]~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[104]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[104]~9 .lut_mask = 64'h0000000000550055;
defparam \u0|mm_interconnect_0|router|src_data[104]~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y29_N29
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|src_data[104]~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4] $
// (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|router|Equal7~6_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4] ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 .lut_mask = 64'h55555555555A555A;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[101]~8 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[101]~8_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & \u0|mm_interconnect_0|router|Equal7~6_combout )) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (\u0|mm_interconnect_0|router|Equal7~6_combout &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[101]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[101]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[101]~8 .lut_mask = 64'h0400040001010101;
defparam \u0|mm_interconnect_0|router|src_data[101]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y29_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|src_data[101]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ) #
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout
// & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] $ ((((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( !\u0|mm_interconnect_0|router|Equal7~6_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( !\u0|mm_interconnect_0|router|Equal7~6_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1] ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [1]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 .lut_mask = 64'h00FF00FF08F705FA;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout & ( \u0|mm_interconnect_0|router|src_data[100]~1_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0] $ (((!\u0|mm_interconnect_0|router|src_data[100]~2_combout ) #
// (\u0|mm_interconnect_0|router|src_data[100]~3_combout ))))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout & ( !\u0|mm_interconnect_0|router|src_data[100]~1_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0] $ (\u0|mm_interconnect_0|router|src_data[100]~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router|src_data[100]~2_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [0]),
.datac(!\u0|mm_interconnect_0|router|src_data[100]~3_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ),
.dataf(!\u0|mm_interconnect_0|router|src_data[100]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 .lut_mask = 64'hC300000063000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # (!\u0|mm_interconnect_0|router|src_data[103]~0_combout $
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [3])))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datab(!\u0|mm_interconnect_0|router|src_data[103]~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id [3]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 .lut_mask = 64'h0A0A0A0A0A0A0E0B;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y27_N44
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|Equal15~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [9]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src9_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [9] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [9]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~0 .lut_mask = 64'h00FF00FF000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src9_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal15~0_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout & (\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout &
// \u0|mm_interconnect_0|router|Equal7~6_combout )) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~1 .lut_mask = 64'h0000000000050005;
defparam \u0|mm_interconnect_0|cmd_demux|src9_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y31_N47
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[9] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .lut_mask = 64'h00000000F0FFF0FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( \u0|mm_interconnect_0|router_001|Equal15~0_combout & ( ((\u0|mm_interconnect_0|router|Equal15~0_combout &
// (\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout & \u0|mm_interconnect_0|router|Equal7~6_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|router|Equal14~0_combout & (
// \u0|mm_interconnect_0|router_001|Equal15~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ) ) ) # ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( !\u0|mm_interconnect_0|router_001|Equal15~0_combout & (
// (\u0|mm_interconnect_0|router|Equal15~0_combout & (\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout & \u0|mm_interconnect_0|router|Equal7~6_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 .lut_mask = 64'h0000000355555557;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .lut_mask = 64'h00000F0FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h4C004C004C4C4C4C;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N14
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y32_N59
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2] ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3 .lut_mask = 64'h55555555FF00FF00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] &
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .lut_mask = 64'h55F555F500F000F0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))
// # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .lut_mask = 64'h2288228877DD77DD;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y28_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])
// # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) )
// ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2]))))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .lut_mask = 64'h208A208A75DF75DF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .lut_mask = 64'h0FF00FF000FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N25
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] $ (((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]) #
// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4] & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] $ (((!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]) # (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1 .lut_mask = 64'h0C480C483F7B3F7B;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [4] $ (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h9C9C9C9CCCCCCCCC;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hF000F303F505F707;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N14
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [5]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout $ ((((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 .lut_mask = 64'h20DF20DF00FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y29_N32
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6] ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout & \u0|hps_0|fpga_interfaces|h2f_AWLEN [3]) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [6]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4 .lut_mask = 64'h111111110F0F0F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout
// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout )) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .lut_mask = 64'h11BB11BBB11BB11B;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0800FFFF0000FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y30_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0F00F1F10000F1F1;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF000F000F000F000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal15~0_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|cmd_mux_009|src_payload [0]) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout &
// (!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout & ((\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]))) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout &
// (!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0])))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 .lut_mask = 64'h888D88DD000F00FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout = !\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y30_N14
dffeas \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q & ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout
// & (\u0|mm_interconnect_0|cmd_mux_009|src_payload [0] & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q & (
// \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout & (\u0|mm_interconnect_0|cmd_mux_009|src_payload [0] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q & ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout & (\u0|mm_interconnect_0|cmd_mux_009|src_payload [0] & (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q & ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout & ((!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ) # ((\u0|mm_interconnect_0|cmd_mux_009|src_payload [0] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 .lut_mask = 64'h5150010011001100;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y30_N23
dffeas \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y30_N20
dffeas \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 .lut_mask = 64'h3033303330303030;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y30_N29
dffeas \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout & (\u0|mm_interconnect_0|router|Equal15~0_combout &
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|mm_interconnect_0|router|Equal7~6_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0007000700770077;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hDDDDDDDDCCCCCCCC;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y25_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout =
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h54AE54AE54AE54AE;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3]))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h32DC32DC10FE10FE;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) )
// ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
// # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h4540BFBA0500FFFA;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4])) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h10FE10FEBA54BA54;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) )
// ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0500FFFAC5C03F3A;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N1
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F55555555;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y27_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y25_N46
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q )) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h11111D1D11111D1D;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y25_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h000033330C0C3F3F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y27_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h010D010DF1FDF1FD;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout & (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~4 .lut_mask = 64'h00000000AAABBBBB;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y27_N34
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router|Equal14~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src8_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal14~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal14~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal14~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal14~1 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|router_001|Equal14~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal14~2_combout = ( \u0|mm_interconnect_0|router_001|Equal14~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal14~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal14~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal14~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal14~2 .lut_mask = 64'h0000000000040004;
defparam \u0|mm_interconnect_0|router_001|Equal14~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y31_N32
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal14~2_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8] &
// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .lut_mask = 64'h00FF00FF000F000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y28_N1
dffeas \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout &
// (\u0|mm_interconnect_0|router|Equal14~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]) # (!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & (
// \u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & \u0|mm_interconnect_0|router|Equal14~1_combout )) ) ) ) # (
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & \u0|mm_interconnect_0|router|Equal14~1_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout &
// \u0|mm_interconnect_0|router|Equal14~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 .lut_mask = 64'h000A000F000A000E;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] &
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hA0A0A0A0AAAAAAAA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .lut_mask = 64'h0000000003030303;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y28_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y28_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y28_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [66] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y28_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q
// & ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))
// # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
// # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))
// # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) )
// )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h0B08F7F40B08F7F4;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N53
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )
// # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2] & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]
// & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h5044AFEE0044FFEE;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2] & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0000A0A000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h555C555CA5ACA5AC;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N19
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
// # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h1100FFEED1C03F2E;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y28_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h00000000000A000A;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h00300030F0F0F0F0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000FFFF005FCCFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00000000FAAAFAAA;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000CCDCCCDC;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h37053705FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) )
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h0FF30FF30CF00CF0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h085D085D2A7F2A7F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N53
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y26_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y28_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y28_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y28_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y26_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q )) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q &
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter
// [5] ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $
// (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout
// ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter
// [2] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout
// & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) #
// ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout
// & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ))) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q &
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00002200000022F0;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N7
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000DFDFDFDF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout
// & \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout )) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00A000A000F000F0;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q $
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q $
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2211221130300303;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter
// [4] ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & (
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout
// ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & (
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h5000055544444444;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y26_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q &
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q &
// !\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ) # (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h5554505055545050;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .lut_mask = 64'h5555555555FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y29_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [88] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y29_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .lut_mask = 64'h00330033FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N53
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .lut_mask = 64'hA080000000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q &
// (\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & !\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .lut_mask = 64'h0200000020222222;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0700070077007700;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout )) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00DF00DFFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout &
// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF30303030;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y28_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y28_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y28_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y28_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [68] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y28_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q &
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .lut_mask = 64'h00000000303F303F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout & (
// ((\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0000CFCF00CF30FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout &
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000F0F00000;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout & ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & ((\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout & ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q &
// ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout & (
// !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & ((\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) #
// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h0000151551511515;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout & (
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000F0FF0F0;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & (
// (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (
// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] &
// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (
// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] &
// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (
// !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .lut_mask = 64'h0F002F002F000F00;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0BBB0BBB00000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h01050105030F030F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & (
// (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .lut_mask = 64'h0030003030003000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .lut_mask = 64'h4F4F4F4F00000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] = ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .lut_mask = 64'h555F555F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))
// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5500550040004000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) #
// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h000000002222F2F2;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF35FF3500000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) #
// ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y28_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h00AA00AAFFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y28_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hBBBBBBBBBBBBBBBB;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] $ (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) )
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])
// # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h44BB44BB0F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y28_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hBFBFBFBF40404040;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hCC00CC55CC0FCC5F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout )) )
// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .lut_mask = 64'h408C408C73BF73BF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h20000000FFFFFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00350035FF35FF35;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h02EE02EE00CC00CC;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y28_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))))) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0A00F0F00A00F3F3;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y26_N50
dffeas \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q & ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0] &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) )
// ) # ( !\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q & ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0] &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) )
// ) # ( \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q & ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|src_payload [0] & (\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) )
// ) # ( !\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q & ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_008|src_payload [0] &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) )
// )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .lut_mask = 64'hFF13001313131313;
defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y28_N8
dffeas \u0|mm_interconnect_0|cmd_mux_008|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout & (\u0|mm_interconnect_0|router|Equal7~7_combout &
// (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]))) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal7~7_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|router|Equal7~7_combout & ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( (!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout &
// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & (\u0|mm_interconnect_0|router_001|Equal14~2_combout ))) # (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & (((\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout &
// \u0|mm_interconnect_0|router_001|Equal14~2_combout )) # (\u0|mm_interconnect_0|router|Equal7~6_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|router|Equal7~7_combout & ( \u0|mm_interconnect_0|router|Equal14~0_combout & (
// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|router|Equal7~7_combout & ( !\u0|mm_interconnect_0|router|Equal14~0_combout & (
// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|router|Equal7~7_combout & ( !\u0|mm_interconnect_0|router|Equal14~0_combout & (
// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(!\u0|mm_interconnect_0|router|Equal7~7_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .lut_mask = 64'h0303030303030357;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q & \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout & \u0|mm_interconnect_0|cmd_mux_008|src_payload [0]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout &
// ((!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ((\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .lut_mask = 64'h080D000F08080000;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y28_N53
dffeas \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|router_001|Equal14~2_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout &
// ((!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ) # (!\u0|mm_interconnect_0|router|Equal14~1_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal14~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .lut_mask = 64'h0000000022203333;
defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y28_N14
dffeas \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y28_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .lut_mask = 64'h000000003333FFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y28_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h303F303F707F707F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N59
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( ((!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hF000F000F555F555;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ) ) ) #
// ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h330033000F000F00;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout & (((\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1])))
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h02AA02AA02AA02AA;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout & (((!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout &
// (((\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1])))
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h19DF19DF19DF19DF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .lut_mask = 64'h1133113333333333;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y28_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used
// [1] ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y26_N58
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & ((\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout & \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~3 .lut_mask = 64'h00000000FF11FF15;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q & (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .lut_mask = 64'hCC00CC00CC000000;
defparam \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout = ( \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y23_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & \u0|mm_interconnect_0|router|Equal14~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 .lut_mask = 64'h0000000000000004;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h00000000000C000C;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y22_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h0FF00FF00CFC0CFC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h32DC32DC10FE10FE;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h10FE10FEDC32DC32;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N19
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0404FEFEAE0454FE;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] &
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888CCCCCCCC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0808F0F00808F0FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q
// & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h2A002A002A2A2A2A;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// & ((\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// & ((\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h00150015003F003F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y22_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h030303030F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])))) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0111FFFF0111DDDD;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &
// ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y22_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h2220222022002200;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000000044F444F4;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 .lut_mask = 64'h1122112200000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[33] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y22_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB
// [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[32] .lut_mask = 64'h03030303FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y22_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB
// [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[35] .lut_mask = 64'h05050505FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y23_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[87] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[88] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [88] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFF000000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 .lut_mask = 64'h2A2A2A2A22222222;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F030503050;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = (!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] &
// ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])))) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) # ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))))
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7350735073507350;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y22_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h408C408C73BF73BF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y22_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF05AF05AF0F0F0F0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))))
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] &
// ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF000F033F055F077;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y22_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y22_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout )) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h55555555D5555555;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00FF00FF35353535;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h10FA10FA00AA00AA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00000000FFA0FFA0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h04040404CCCCCCCC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// & !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000ABAAABAA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout )))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) #
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout )))) )
// )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h50735073FFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0D08F7F20500FFFA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y22_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y22_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h202F202F707F707F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h0E020D01020E010D;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666AAAAAAAA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000AC5C00005C5C;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y22_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00AA00AA00F000F0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) )
// ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) )
// ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0208070D070D0208;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000220000007250;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000AFFFAFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00CF00CF00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y22_N49
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y22_N19
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h303030303F3F3F3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FAEAFAEA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y22_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0080000000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N55
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) #
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~5 .lut_mask = 64'h0000F0F50000F0F7;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[32] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[87] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) ) #
// ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE
// [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[88] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [87] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y29_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[35] .lut_mask = 64'h5555555577777777;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[34] .lut_mask = 64'h5555555555FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 .lut_mask = 64'hA800000000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $ (((\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .lut_mask = 64'h0505090500000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y27_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout & (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h02570257AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y29_N14
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y27_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (
// !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .lut_mask = 64'h000000FFFF00FFFF;
defparam \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]))) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h000000005F5F4C4C;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h44FF44FF33773377;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .lut_mask = 64'hF0C0F0C000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout &
// (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) # (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & (
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) # (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) #
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ) #
// (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~12 .lut_mask = 64'hFCFCFC00A8A8A800;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY
// [0] & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y18_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y18_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h1F1F1F1F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h55AA55AA50FA50FA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h50AF50AF44EE44EE;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h4040BFBF5500FFAA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]
// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEF40EF40E;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y17_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y17_N19
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h1100FFEEB1A05F4E;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout
// ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout
// & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0030FCFC0000CCCC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y17_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y17_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y17_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h0D08080D07020207;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00E2002E002200EE;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3FFF3FFFC000C000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555000500050;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0408070B070B0408;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0500000005000C0C;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0F050F050F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5511551100000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y17_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h05050505AFAFAFAF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FAEAFAEA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & (
// (\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout & (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & (
// \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & (
// (\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0505555504044444;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .lut_mask = 64'hAA00AA0088008800;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] $ (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .lut_mask = 64'h000008A2000000AA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout
// ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y19_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y27_N28
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[15] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|Equal21~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[15] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[15] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src15_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15] & ( (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [15]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~0 .lut_mask = 64'h0022002200330033;
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src15_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout & (\u0|mm_interconnect_0|router|Equal7~6_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~1 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux|src15_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000001010;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h00FF00FFFA0AFA0A;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h0000FFFFD8D87272;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFD85072FA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )
// ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h0A0AF5F55F0AF5A0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N25
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h4400BBFF7430B8FC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .lut_mask = 64'h0000000011011101;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout &
// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h0011001100FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000FAFA1155FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h02FA02FA00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0F0F0F0F0A000A00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h222A222A222A222A;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h3030303031303130;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout )))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout )))) )
// )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h50735073FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h3F333F330F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h484848487B7B7B7B;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h22DD22DD0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hFF00FF005FA05FA0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )))) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [1]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hFFFF0000111F111F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .lut_mask = 64'h11BB11BBB11BB11B;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0])) )
// )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .lut_mask = 64'h0030003030003000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [87] = (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [0] & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [88] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .lut_mask = 64'h0F0F0F0F3F3F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .lut_mask = 64'h555555555F5F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .lut_mask = 64'h00330033FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .lut_mask = 64'h55005500F500F500;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y21_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h2220222022002200;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) # ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000000075307530;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF53FF5300000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h08000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q
// ) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
.datag(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0A00F0F00A00F3F3;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ((\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (((\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]))) ) ) ) #
// ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000005F0000135F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y21_N43
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .lut_mask = 64'h0000000033FF33FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h447744774C7F4C7F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h000E000E00EE00EE;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h330033003F003F00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout & (
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0CFF0CFF333F333F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y21_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h085D085D2A7F2A7F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y21_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y21_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ))))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h3202310102320131;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5F5F5F5FA0A0A0A0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h3210103210103232;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3C3CCCCCCCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F000F000A0A0A0A;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )))) )
// ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )))) )
// ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0048007B007B0048;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000202011003120;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N37
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000FF3FFF3F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00CC00CC000C000C;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout
// & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FE00FE00AA00AA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCCCFCCCFCCCFCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y21_N52
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ) #
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~2 .lut_mask = 64'h4445444544454455;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y24_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout & ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .lut_mask = 64'h507050D050505050;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF00FF00FFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal17~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal17~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal17~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal17~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal17~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|router_001|Equal17~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal17~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal17~1_combout = ( \u0|mm_interconnect_0|router_001|Equal17~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|mm_interconnect_0|router_001|Equal1~1_combout
// & (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal17~0_combout ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal17~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal17~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal17~1 .lut_mask = 64'h0000000000000002;
defparam \u0|mm_interconnect_0|router_001|Equal17~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y31_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal17~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & ( \u0|mm_interconnect_0|router_001|Equal17~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & ( \u0|mm_interconnect_0|router_001|Equal17~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q )) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal17~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .lut_mask = 64'h0000000003000303;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal17~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal17~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal17~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal17~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal17~0 .lut_mask = 64'h0000000000000505;
defparam \u0|mm_interconnect_0|router|Equal17~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y27_N49
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|Equal17~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src11_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11] & ( (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .lut_mask = 64'h0022002200330033;
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (
// (\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|mm_interconnect_0|router|Equal14~0_combout
// ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datae(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y24_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ) # (\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h000000000FFF0FFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000CDCCCDCC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000300030;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y24_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h33CF33CF30CC30CC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]
// $ (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) #
// ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h00FF00FFE22EE22E;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $ (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2]) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h33333333C333AAAA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h02FE02FECE32CE32;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N19
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [6] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [6] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h1010FEFEBA1054FE;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8080000000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] &
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hCC00CC00CCCCCCCC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h20A020A030F030F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7755775533003300;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] $ (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout = (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout )) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3]))))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .lut_mask = 64'h478B478B03CF03CF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hB4F0B4F0B4F0B4F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hCC00CC55CC0FCC5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout &
// ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ))
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y25_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout &
// ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0000FFFF8000FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
.datag(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0C00F0F00C00F5F5;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & (
// \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) )
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) )
// ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) )
// ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000151515151515;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[88] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[87] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [87] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFF000000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[32] .lut_mask = 64'h333333333F3F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[33] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[34] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 .lut_mask = 64'h0330033000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout )) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 .lut_mask = 64'h00A000A0F0F0F0F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000FFF00077FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) )
// )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C080C0808080808;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] &
// (((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000000022F222F2;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF47FF4700000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
// # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y24_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FF00FF00C000C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h3030303030F030F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h775577557F5F7F5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y24_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h02EE02EE00CC00CC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y24_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y24_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5] & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h00000F0F50505F5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y24_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y24_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout = (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3]))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ))))
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC0C0000000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y24_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q
// $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q
// $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y24_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3C3CCCCCCCCCCCCC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y24_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )
// # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y24_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0202000013021100;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00FF00FF003F003F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0000F0000000F0F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y24_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] $ (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33CC33CCFF00FF00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ) )
// ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h3003003322222222;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y24_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) #
// ((\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~0 .lut_mask = 64'h5050505151515151;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~1 .lut_mask = 64'h3030303030333133;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout &
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout & ((!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout & (
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout & ((!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout & ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ((!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) #
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout & ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) #
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~10 .lut_mask = 64'hFFAACC88F0A0C080;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N41
dffeas \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (
// ((\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) #
// (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (
// ((\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) #
// (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .lut_mask = 64'h5755755500000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF33333333;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N41
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h5555AAAA5050FAFA;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N53
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h5500AAFF5050FAFA;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N17
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3])) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h4040BFBF5500FFAA;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y32_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h04EE04EE00AA00AA;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y32_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N55
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y32_N14
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .lut_mask = 64'h0055005555555555;
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N47
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h04370437CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) #
// (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .lut_mask = 64'h00000000330F330F;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55F755F755FF55FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N8
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout = (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & (((\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0])))
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .lut_mask = 64'h070F070F070F070F;
defparam \u0|mm_interconnect_0|link_start_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N47
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0A0A5F5F00AA55FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N11
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y32_N29
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]
// & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N38
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [6] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h3030CFCF5500FFAA;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y32_N19
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N35
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y32_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y32_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0000333300CC33FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N41
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter
// [4] ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout & (
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout & (
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout & (
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout & (
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q )) #
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4505155540001050;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N44
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter
// [5] ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $
// (((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout
// ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter
// [4] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3])))
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout )) )
// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout )))) #
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h000000001DD12EE2;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N14
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & (
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout
// & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0202020200003300;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N49
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y32_N53
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000FF5FFF5F;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout
// ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000CF00CF00;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q $
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q $
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4411441150500505;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N20
dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N44
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N17
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & (
// (!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) #
// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FAFAEAEA;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ))
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0FAF0FAF0FAF0FA;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y32_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q & (
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0080000000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N20
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N13
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q & (\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout & ((\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & (
// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q & \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout )) ) ) ) # (
// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~8 .lut_mask = 64'h3333333301010103;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N38
dffeas \u0|mm_interconnect_0|cmd_mux|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .lut_mask = 64'h00000000000D000D;
defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout &
// ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7 .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) # ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .lut_mask = 64'h55005500F5F0F5F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout )) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] $ (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout )) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout )) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF5FFF5FF0A000A00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ))) #
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) ) )
// )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 .lut_mask = 64'hFF11FF1F0011001F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h2020202000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout
// & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [5]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout &
// ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout
// & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout )) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout )) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout & (
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [34] = ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [2])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[34] .lut_mask = 64'h5577557755775577;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h7520752055005500;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ) #
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ) # ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'hAAA8EEEC00000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h1100110013001300;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[33] .lut_mask = 64'h0F0F3F3F0F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[35] .lut_mask = 64'h5555555577777777;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .lut_mask = 64'h55555F5F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y26_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] &
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 .lut_mask = 64'h0000000066006600;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[87] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[88] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux|src_data [87] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|src_data [87]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 .lut_mask = 64'h0CCC0CCC00CC00CC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[103]~4 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[103]~4_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[103]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[103]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[103]~4 .lut_mask = 64'h0000000023272327;
defparam \u0|mm_interconnect_0|router|src_data[103]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout = ( !\u0|mm_interconnect_0|router|src_data[103]~4_combout & ( !\u0|mm_interconnect_0|router|src_data[103]~5_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|src_data[103]~5_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|src_data[103]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~2 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y27_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .lut_mask = 64'h4444444455555555;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (!\u0|mm_interconnect_0|router|src_data[103]~5_combout & (!\u0|mm_interconnect_0|router|src_data[103]~4_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|router|src_data[103]~5_combout ),
.datac(!\u0|mm_interconnect_0|router|src_data[103]~4_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h0000004000FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1])))) ) ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0007FFFF0007F0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_payload [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) )
// ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3030303020002000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) #
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000000050DC50DC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF53FF5300000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
// ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h55FF55FF00FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h55AA55AA50FA50FA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $
// (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h44BB44BB50FA50FA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) )
// ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
// # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h4540BFBA0500FFFA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEF40EF40E;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N25
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) )
// ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
// # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// )))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h3530CFCA0500FFFA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h000000001F001F00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000ECECECEC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & (
// (!\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0202020200000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((!\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00000000CCCECCCE;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ( ((\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h55575557FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0F000F00FF00FF00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ) #
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hAAA8AAA8AAA8AAA8;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// ((\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) )
// ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|last_cycle~0 .lut_mask = 64'h555500115F5F0013;
defparam \u0|mm_interconnect_0|cmd_mux|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ) # (((\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout &
// \u0|mm_interconnect_0|cmd_mux|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q &
// (!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout & ((!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|update_grant~0 .lut_mask = 64'hA080A080AFBFAFBF;
defparam \u0|mm_interconnect_0|cmd_mux|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N29
dffeas \u0|mm_interconnect_0|cmd_mux|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .lut_mask = 64'h88888888AAAAAAAA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00530053FF53FF53;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h332A332A33003300;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y26_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y26_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y26_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00E200D1002E001D;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5F5FA0A0FFFF0000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout = !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $
// (((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h6A6A6A6A6A6A6A6A;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout )))) )
// ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q
// & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0E02020E020E020E;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h7F7F7F7F80808080;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0A0A0A0A0F000F00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q )))) ) )
// ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0440155115510440;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 .lut_mask = 64'hA080000000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y26_N13
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y26_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 .lut_mask = 64'h00000F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000088888888;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & (((!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 .lut_mask = 64'h000000000080AA2A;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y26_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0A5F0A5F2A7F2A7F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q & ( ((!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h888888888F8F8F8F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h4747474700000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout )) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h10101010F0F0F0F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout = (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1])))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] $ (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0])))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h43F743F743F743F7;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 .lut_mask = 64'h1515151555555555;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y26_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y26_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q & (\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout
// & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q & \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~6 .lut_mask = 64'h0F0F00050F0F0007;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hCCCC0000CCCCCCCC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y33_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .lut_mask = 64'h0BF70BF708F408F4;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0A000A0000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )
// ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h00CCFF3330FCFC30;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N31
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h3000CFFF30AACFAA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h10FA10FA00AA00AA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h51F351F300000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal7~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal7~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal7~1 .lut_mask = 64'h0000000080808080;
defparam \u0|mm_interconnect_0|router_001|Equal7~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal7~2_combout = ( \u0|mm_interconnect_0|router_001|Equal7~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout &
// \u0|mm_interconnect_0|router_001|Equal1~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal7~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal7~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal7~2 .lut_mask = 64'h0000000001010101;
defparam \u0|mm_interconnect_0|router_001|Equal7~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y31_N11
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|Equal7~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4] &
// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .lut_mask = 64'h0F0F0F0F03030303;
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( \u0|mm_interconnect_0|router_001|Equal7~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout &
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~9 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~9_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & \u0|mm_interconnect_0|router|Equal7~8_combout ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|Equal7~8_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~9 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|router|Equal7~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y27_N11
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|Equal7~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src4_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .lut_mask = 64'h5050505055555555;
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|WideOr1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout = ( \u0|mm_interconnect_0|router|Equal7~8_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) # (!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|router|Equal7~8_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( !\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ) ) ) # ( \u0|mm_interconnect_0|router|Equal7~8_combout & (
// !\u0|mm_interconnect_0|router|Equal7~6_combout & ( !\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|router|Equal7~8_combout & ( !\u0|mm_interconnect_0|router|Equal7~6_combout & (
// !\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|router|Equal7~8_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|WideOr1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|WideOr1 .lut_mask = 64'hF0F0F0F0F0F0F0E0;
defparam \u0|mm_interconnect_0|cmd_mux_004|WideOr1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h050F050F00000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y32_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) )
// # ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] .lut_mask = 64'h00000F0FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y32_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h33333333550F550F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) #
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h00F000F0FFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y30_N20
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .lut_mask = 64'h0500050009000500;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY
// [0] & ( (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0 .lut_mask = 64'h05050505AFAFAFAF;
defparam \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout = (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout & \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .lut_mask = 64'h00000F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h130013005F005F00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00DF00DFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y30_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h447744774C7F4C7F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCEEEEEEEE;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N20
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0])) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0055004455554444;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N35
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h083B083B4C7F4C7F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y30_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y30_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0033003344774477;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y30_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0033003344774477;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ))))
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0437043704370437;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N2
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) #
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0048007B007B0048;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000404000007340;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N49
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00C800C800FA00FA;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4411441150500505;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FF00FF0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0C000A0A030F0A0A;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CF03CF0F0F0F0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout = !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ))))
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h6CCC6CCC6CCC6CCC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0F000F000A0A0A0A;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000008000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N19
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~7 .lut_mask = 64'h00000000F0F1F3F3;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & ( \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout &
// (!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) #
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) #
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~11 .lut_mask = 64'hFFAAF0A0CC88C080;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y19_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y19_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[32] .lut_mask = 64'h05050505FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [87] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) ) ) #
// ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE
// [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_018|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_018|src_data [88])
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'h8888888888888888;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 .lut_mask = 64'h8800000080000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout = (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y16_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y19_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 .lut_mask = 64'h000033330000FFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &
// !\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000C0C0C0C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q &
// (((\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout &
// ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout & (\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1])))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h010D010D03070307;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 .lut_mask = 64'h00006000FF00FF00;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h0000FFFFFFAA00AA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y19_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))
// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) #
// ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h0000FFFFCCAA33AA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y19_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))
// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) #
// ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]
// & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))
// # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h3202CEFE0202FEFE;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y19_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y19_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h393939397D287D28;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y19_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y19_N25
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]
// & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]
// & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [6] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h3000CFFF3A0ACAFA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout
// & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'hA000000000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )
// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h10FC10FC00CC00CC;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y19_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4]) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h00000F0F00F00FFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y19_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y19_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h5353535300FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y19_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y19_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00000F0F50505F5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y19_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])
// ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])
// ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000F000F0000FFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q & (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q $
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q $
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]
// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ))) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q &
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000A0CC5FCC;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout = !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]
// & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78F078F078F078F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h6C6C6C6CCCCCCCCC;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout )) )
// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00FC00FC00300030;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout
// $ (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q )))) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h000000003C553CAA;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout &
// ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q )))) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000000300030AA;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000AFFFAFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q &
// (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q &
// (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) #
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000BBB0BBB0;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y19_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1])) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout & (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] &
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .lut_mask = 64'h000020000000D0F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout & ( \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout = (\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y19_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h505F505F707F707F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout &
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & (
// (\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1110111055505550;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h11FF11FF00000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ) #
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) # (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q
// & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0000FFFF0000AAA8;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y19_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y19_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y19_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 .lut_mask = 64'h00C000C000000000;
defparam \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y23_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout = (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q &
// !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ))
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~9 .lut_mask = 64'h0500050005000500;
defparam \u0|mm_interconnect_0|rsp_mux|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout & ( \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout & ( (\u0|mm_interconnect_0|rsp_mux|WideOr1~combout &
// \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout & ( \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout & ( (\u0|mm_interconnect_0|rsp_mux|WideOr1~combout & \u0|hps_0|fpga_interfaces|h2f_BREADY
// [0]) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout & ( (\u0|mm_interconnect_0|rsp_mux|WideOr1~combout & (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] &
// ((!\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~10_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout & (
// (\u0|mm_interconnect_0|rsp_mux|WideOr1~combout & \u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted .lut_mask = 64'h0303030203030303;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout = ( !\u0|mm_interconnect_0|router|src_data[103]~5_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & !\u0|mm_interconnect_0|router|src_data[103]~4_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|src_data[103]~4_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|src_data[103]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~7 .lut_mask = 64'h5050505000000000;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout & (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] &
// \u0|mm_interconnect_0|router|Equal15~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|router|Equal15~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~6 .lut_mask = 64'h0000000000050005;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout = ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( (\u0|mm_interconnect_0|router|Equal7~7_combout & (\u0|mm_interconnect_0|router|Equal7~6_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|router|Equal7~7_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~5 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))))
// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout
// & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ) # ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// (!\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ) # ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// (!\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ) # ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~1 .lut_mask = 64'hEAEAEA00EA00EA00;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|router|Equal16~0_combout &
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (\u0|mm_interconnect_0|router|Equal16~0_combout & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0])) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|Equal16~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~3 .lut_mask = 64'h00050005000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( \u0|mm_interconnect_0|router|Equal17~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( \u0|mm_interconnect_0|router|Equal17~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal17~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~4 .lut_mask = 64'h0000000003033333;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & \u0|mm_interconnect_0|router|Equal13~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~9 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] &
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hA0A0A0A0F0F0F0F0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N11
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2])) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [88] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N53
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N20
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [32]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[35] .lut_mask = 64'h3333333377777777;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout = (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ))))
.dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .lut_mask = 64'h0028002800280028;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .lut_mask = 64'h00A000A0AAAAAAAA;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y32_N38
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h050505050F0F0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000FFCC005FFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y32_N50
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N23
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5400540044004400;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h000000002F222F22;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF35FF3500000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) #
// ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y32_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0BBB00000BBB0000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & \u0|mm_interconnect_0|router|Equal7~8_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~8_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~8 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~8 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ) #
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) )
// ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ) #
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) )
// # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ) #
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~2 .lut_mask = 64'hFCCCFCCCA8880000;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout & (
// (\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout & (!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout & !\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout &
// (\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout & (!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout & !\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~3 .lut_mask = 64'h0000000020003000;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & (
// (!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) # ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout & \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout & ((!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ) # (\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) #
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout & ( !\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & (
// (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 .lut_mask = 64'h000FFFF0000DFFF2;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y28_N35
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0_combout = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0] $
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0 .lut_mask = 64'h5AA55AA55AA55AA5;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y28_N31
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]
// ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 .lut_mask = 64'h2020FBFB0000FFFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y28_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y27_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router|Equal20~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[14] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src14_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14] & ( (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [14]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~0 .lut_mask = 64'h000A000A000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src14_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (\u0|mm_interconnect_0|router|Equal7~6_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~1 .lut_mask = 64'h0000000000000004;
defparam \u0|mm_interconnect_0|cmd_demux|src14_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout &
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) # (\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h000011550000135F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [116] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) ) #
// ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11]
// & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .lut_mask = 64'h0000555533337777;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N28
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [116] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h555555550000FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .lut_mask = 64'hCCCCCCCC00000000;
defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & (
// \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .lut_mask = 64'h000000FF555555FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal8~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal8~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal7~0_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal8~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal8~0 .lut_mask = 64'h0000000000020002;
defparam \u0|mm_interconnect_0|router_001|Equal8~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N35
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[19] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal8~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|Equal8~0_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q
// )) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .lut_mask = 64'h0500050005050505;
defparam \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y21_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .lut_mask = 64'h4474447488B888B8;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout
// & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .lut_mask = 64'h4844484448447B77;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]
// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCC3CCC3CCCCCCCCC;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF0F5F0F500050005;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h44884488478B478B;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N25
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]
// & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]
// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h0F11F0110011FF11;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000003000300;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y20_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout &
// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] &
// !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000050505050;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y22_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .lut_mask = 64'h00F000F0F0F0F0F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFEE44EE44;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFAC0C5CFC;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0808080800000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEAE54AE54;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N19
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout = (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))))
// # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .lut_mask = 64'h0044FFEEA0E45F4E;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout
// & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) )
// ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))))
// ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h01BB01BB00AA00AA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))
// ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00CC00CC01CF01CF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h00FF00FFE44EE44E;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y21_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFF0FFF0FFF00FF00;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y22_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y22_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))
// # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y22_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used
// [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2230220311301103;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) )
// # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $
// (((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h77FF77FF88008800;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout )))
// ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555005000500;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1200123312331200;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout )))) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000C0000022E2;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N49
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y20_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F5FFF5FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] )
// )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q &
// ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5050505010101010;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) )
// # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CCCCCCCCC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ))) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q )))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000E22E000022EE;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y20_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q &
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout
// )))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FCECFCEC;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0505050555555555;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0FBF0FBF0FFF0FFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])) #
// (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q &
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h000000003F2A3F2A;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0F0F5F5F00000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h5050FFFF0F0F5F5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .lut_mask = 64'h003F003F00FF00FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout = (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout &
// (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00BB00BB0B4F0B4F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h050F050F00000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout = (\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0404040404040404;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout = (\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q &
// !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .lut_mask = 64'h0500050005000500;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y21_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y21_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y21_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFAFAFAFAAAAAAAAA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .lut_mask = 64'h8080000000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00E400CC00F000F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001AAAB0001FFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y21_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))
// ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3230323000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) #
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFE00FE00FF00FF00;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout
// & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout )
// ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout
// & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00800000FFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y21_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hF0F0F0F0F0A0F0A0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0101010101FF01FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hAAFAAAFAFAFAFAFA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h33FF33FF00CC00CC;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (((!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0000CCCC2033ECFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'hAEAFAAAF0C0F000F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h30AA30AA00AA00AA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0F000F00EE00CC00;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (
// (\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q & (
// !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .lut_mask = 64'h0000FFFF0055AAFF;
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y31_N41
dffeas \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( (!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .lut_mask = 64'hF0F0F3F3F0F0C0C0;
defparam \u0|mm_interconnect_0|cmd_mux_019|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y31_N5
dffeas \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_019|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y21_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .lut_mask = 64'hA000000080000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .lut_mask = 64'hF0C0F0C000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N46
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]))
// # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N10
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout &
// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000500050;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000AAA0AAA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h30CF30CF22EE22EE;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h2200DDFF3030FCFC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N26
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF022EE22EE;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y21_N19
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0F00F0FF2222EEEE;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ))) ) )
// # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )))) )
// )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00F100F101F101F1;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFC30FC30;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y21_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h550055FF0F000FFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y21_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y19_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y19_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000000FF550055FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q )) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h3003300322221111;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CF03CF0F0F0F0F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33FF33FFCC00CC00;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4411005550505050;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3030303033003300;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q
// )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1020132313231020;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000220010103210;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N37
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N41
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3303330300000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y19_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y19_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout )) ) )
// ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FCFCF8F8;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCECECECECECECECE;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N46
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y23_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .lut_mask = 64'h0000555500005555;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N58
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .lut_mask = 64'h88AA000088AA88AA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & (
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .lut_mask = 64'h000000FF333333FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y23_N1
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y23_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N34
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y23_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & (
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N55
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] )
// ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_channel[16]~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout
// & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_channel[16]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_channel[16]~1 .lut_mask = 64'h0000000040404000;
defparam \u0|mm_interconnect_0|router_001|src_channel[16]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N4
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16] & ( \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16] & ( \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),
.dataf(!\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .lut_mask = 64'h0000000030303333;
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000000FF00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F0F0000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout = (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel
// [16])))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 .lut_mask = 64'h0C0F0C0F0C0F0C0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h478B478B44884488;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N14
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])))) ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])))) ) ) ) #
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0005FF05CC053305;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]
// & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hA5F0A5F0F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hCCDDCCDD00110011;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [4] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h01CD01CDCD01CD01;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N31
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout
// & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h3305CC050005FF05;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00800000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))
// ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F02DF0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001CCCD;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N55
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y33_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .lut_mask = 64'h54BA54BA10FE10FE;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .lut_mask = 64'h4055BFFF4000BFAA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h2020202000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ))
// # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) )
// ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h5050AFAF5C5CACAC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y33_N19
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h5000AFFF50CCAFCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// ) # (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout
// & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000CCCC0202EEEE;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) )
// ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3020302020202020;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N37
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N29
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFCFCFCFCCCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000E4CC0000F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]) #
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout
// )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00EF00EF00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ( ((\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h00FF03FF00000303;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .lut_mask = 64'hF000F000F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55BB55BB44AA44AA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y33_N14
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h2727272700FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000AAA0AAA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00550055CCDDCCDD;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N29
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 .lut_mask = 64'h0505555555555555;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout = (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used
// [0] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h1111111111111111;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y33_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CF0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4105410555550000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N14
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66AA66AAAAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5550555005000500;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q )))) ) )
// ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout
// $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0048007B007B0048;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000C0002200E2;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h3303330333333333;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0C000C000F000F00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter
// [3] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h4411441150500505;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFE0FFE0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0F000F000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h11DD11DD013D013D;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFFF030F030;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h5744574444444444;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y33_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
// # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1B1BFF033333FF03;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 .lut_mask = 64'h00FF00FF30FC30FC;
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y33_N7
dffeas \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout = ( \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (((!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q )))) #
// (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ((!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & (
// !\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 .lut_mask = 64'hFF00FF00FD01FD01;
defparam \u0|mm_interconnect_0|cmd_mux_016|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y31_N14
dffeas \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y33_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]
// & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [1] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [2]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [3]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 .lut_mask = 64'h7F7FFFFF7FFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000050505050;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1515151515001500;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1])))
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h02AA02AA02AA02AA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ) #
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h1919BFBF1919BFBF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid .lut_mask = 64'hCCC0CCC000000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N13
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N16
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .lut_mask = 64'h0C0CAEAE0000AAAA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ) #
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .lut_mask = 64'hEEEE0E0E00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N53
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [116])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q )))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h4477447744774477;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y25_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [116] = (!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ((\u0|hps_0|fpga_interfaces|h2f_AWID [11])))) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [1] & (((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [11])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N7
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_009|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|rsp_demux_009|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .lut_mask = 64'hAAA0AAA000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N25
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N13
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_channel[2]~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_channel[2]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_channel[2]~0 .lut_mask = 64'h0000080000000000;
defparam \u0|mm_interconnect_0|router_001|src_channel[2]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N20
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout = ( \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 .lut_mask = 64'h0000000000F300F3;
defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y34_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2] &
// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 .lut_mask = 64'h00FF00FF000F000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N46
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFA0A0A0A0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .lut_mask = 64'h55AA55AA30303030;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h5500AAFF03030303;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]
// & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hA5F0A5F0F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .lut_mask = 64'hF0F5F0F500050005;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0F0FF0F000330033;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y36_N19
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]
// & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h0F11F0110011FF11;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h08FF00FF00FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F0F0700080F0000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # ((\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF0011F0F1;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y36_N55
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q
// )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3020302030003000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout &
// ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) #
// (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout &
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F0E0E0F0F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]
// & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [2] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [3]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .lut_mask = 64'h7F7FFFFF7FFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFFCCCC0C0C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y36_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .lut_mask = 64'hF000F000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h0000FFFFFCFC0C0C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h0000FFFFF5A05F0A;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h00D8FF720050FFFA;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y36_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h333A333ACC3ACC3A;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y36_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N19
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h1010FEFEBA1054FE;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hA000000000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FF00FF02220222;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y36_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
// # ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0A00CCCC5FFFCFCF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & ((\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .lut_mask = 64'h00FF00FF50FA50FA;
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y31_N53
dffeas \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal3~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal3~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal3~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal3~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|router_001|Equal3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal3~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal3~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|mm_interconnect_0|router_001|Equal3~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datab(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal3~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal3~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal3~1 .lut_mask = 64'h0000000000020002;
defparam \u0|mm_interconnect_0|router_001|Equal3~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[103]~5 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[103]~5_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &
// (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR
// [17]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])))) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// !\u0|mm_interconnect_0|router_001|Equal2~1_combout ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_data[103]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[103]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[103]~5 .lut_mask = 64'hFFFFC183CC11C001;
defparam \u0|mm_interconnect_0|router_001|src_data[103]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal3~1_combout & ( \u0|mm_interconnect_0|router_001|src_data[103]~5_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|router_001|Equal3~1_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|src_data[103]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .lut_mask = 64'h0000000000000B0B;
defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q )) #
// (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (((!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q & !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q & ((!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .lut_mask = 64'hAAA0AAA0ABA3ABA3;
defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y31_N5
dffeas \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ( ((\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) #
// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F0F1F1F00001111;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y36_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000C000C0C0C0C0C;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000030300000303;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))
// ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F020F0F0FDF0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y36_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout
// & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000FFFF00A0A0A0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout & \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y34_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1313131313001300;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0303FFFF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y34_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h3030FFFF0F0F3F3F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y34_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .lut_mask = 64'h070707070F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used
// [0] ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h005500550000FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h043704378CBF8CBF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0033003344774477;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q & (
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2230220311301103;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FFF0FFFF000F000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q
// )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2133210011331100;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )))) ) )
// ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N2
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000088003000B8;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N13
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000FF5FFF5F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00AA00AA000A000A;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y36_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFE0FFE0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00000000F0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout )))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout )))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h3355335503350335;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y36_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ( ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F3F0F3F00330033;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y36_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N28
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y27_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[116] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N13
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [116] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .lut_mask = 64'hF0C0F0C000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N13
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y31_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0033003300000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .lut_mask = 64'hCCCCCCCC0C0C0C0C;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q
// & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [4] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .lut_mask = 64'h5000AFFF4444EEEE;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [2])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 .lut_mask = 64'h04FE04FEF40EF40E;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N13
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))
// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 .lut_mask = 64'h000CFFFCAA0C55FC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8080000000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )
// )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FF00FF02220222;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AA55AA50FA50FA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $
// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .lut_mask = 64'h50AF50AF44EE44EE;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550055FF55;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y31_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y31_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y31_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h2727272700FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y31_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h00000F0F33333333;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q &
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &
// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )
// # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q &
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0040115100400040;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N25
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000F300F300;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FA05FA0FF00FF00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q
// $ ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q
// $ ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000B78484B7;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0FF00FF0FF00FF00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q & \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ) )
// ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h2211111130303030;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (
// ((\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0F000F0F000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter
// [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4])))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q
// $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout
// )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout )))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h000000001DD12EE2;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N31
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000EEECEEEC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFCCFFCC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N31
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout &
// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 .lut_mask = 64'hC4C4CCCC00C400CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N31
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y36_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal11~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal11~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal3~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal11~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal11~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router_001|Equal11~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N23
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal11~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .lut_mask = 64'h0000000000DD00DD;
defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000000303;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y37_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y37_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y37_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001FF01;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y37_N25
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y37_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y37_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y37_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h003300330C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0F0F0F0F000F000F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h5050505050FF50FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .lut_mask = 64'h0077007700FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout )))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55DF55DF55FF55FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFF00FF00FFF0FFF0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h32CE32CE02FE02FE;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y37_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h0FF00FF022EE22EE;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y37_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y37_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y37_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y37_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h447744770C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .lut_mask = 64'h2200DDFF7250D8FA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y37_N1
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y37_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0303030300FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00D8008D00720027;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout = !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))))
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h6CCC6CCC6CCC6CCC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ))))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ))))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h3120110013023322;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3030303033003300;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout $
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1040154515451040;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000220000007250;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0F050F0500000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y37_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y37_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y37_N10
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFC8FFC8;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout & (
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used
// [0]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0000DDDD0D0D2F2F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .lut_mask = 64'hC0C0C0C0CCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA0AFA0A;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y37_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFD85072FA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h1010FCFC0000CCCC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y37_N2
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h3333202000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFAAAFAAAFAAAFAAA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y37_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q
// & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [1]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .lut_mask = 64'h8000000080000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5450105055550000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF00FF00EF00EF00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFCCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y37_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )
// ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [3]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .lut_mask = 64'h7F7FFFFF7FFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFAFFFAFFF0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h2288228872D872D8;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout
// )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout
// )))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h3035C0C50005F0F5;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hAA5AAA5AAAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hFF03FF0300030003;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) #
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h01AB01ABAB01AB01;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ))) ) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ))) ) ) )
// # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h0101F1F1F10101F1;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00FF00FF80FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.datag(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F550F0F0F1D0F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000FF00000AFFAA;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0808FF007F7FFF0F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & ((\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &
// ( \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .lut_mask = 64'h00FF00FF44EE44EE;
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y34_N17
dffeas \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q & ( (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q & (
// (!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .lut_mask = 64'hFBFBFBFB01010101;
defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N44
dffeas \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y37_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout )) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F1F0F1F00110011;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y37_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y35_N1
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h1515151500000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout = (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0F000F000F000F00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0000000077707770;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h03FF03FF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg
// [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h737373731F1F1F1F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout = (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~58 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~58 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~58 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~58 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .lut_mask = 64'hAA88AA8800000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal9~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal9~0_combout = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datae(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal9~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal9~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal9~0 .lut_mask = 64'h0000000000000100;
defparam \u0|mm_interconnect_0|router_001|Equal9~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N44
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal9~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal9~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|mm_interconnect_0|router_001|Equal9~0_combout
// )) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|router_001|Equal9~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .lut_mask = 64'h0044004400550055;
defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFF0FFF0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q
// & ( (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q
// & ( (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg
// [2])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .lut_mask = 64'h7FFF7FFF7FFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000003030303;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000022222222;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .lut_mask = 64'h0505050500000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])))
// ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h1DD11DD10CC00CC0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h2200DD00220FDD0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h99AA99AAAAAAAAAA;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout
// & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) )
// )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .lut_mask = 64'hFF05FF0500050005;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h01CD01CDCD01CD01;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) ) )
// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant
// [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) )
// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h5503AA030003FF03;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & (
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h40FF00FF00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout &
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000BF800000AAAA;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q
// ))) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F04BF0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF0003AAAB;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .lut_mask = 64'hCCCCCCCC0C0C0C0C;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFEE44EE44;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h31DF31DF20CE20CE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h00D8FF720050FFFA;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h10FE10FEBA54BA54;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y35_N7
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .lut_mask = 64'h0202FEFEF2020EFE;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00CC00CC10FC10FC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C080C0808080808;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hCCC8CCC8CCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout &
// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout &
// ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F000F000F005F55;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFCFFFCFFCCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h5444544474447444;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0A00CCCC5FFFCFCF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q & ((!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout )) #
// (\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .lut_mask = 64'h05FF05FF00FA00FA;
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N23
dffeas \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) # (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout
// & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) ) )
// ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .lut_mask = 64'hF0F0A0A0F0F0F5F5;
defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y35_N26
dffeas \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y35_N16
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000004C4C4C4C;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F5F0F5F00550055;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00F000F000FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h043704378CBF8CBF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0033003344774477;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h5410450110540145;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000B87400007474;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CF03CF0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5050505055005500;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N59
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ))
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0440155115510440;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000404011005140;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000AFFFAFFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0C000C000F000F00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FAEAFAEA;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout )))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55DF55DF55FF55FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFF0FFF0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000C0C0C0C;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0054005454545454;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg
// [0] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1])) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]))))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h445544551D0F1D0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout = (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y28_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [116] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) ) ) #
// ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .lut_mask = 64'h000000FF0F0F0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N22
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .lut_mask = 64'hF000F000A000A000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 .lut_mask = 64'hA020AA22A0A0AAAA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 .lut_mask = 64'h0000000000F30051;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [116] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout & ( ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116] .lut_mask = 64'hFFFFFFFFFFDFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N22
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N49
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [115] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[115] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N49
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h05050505AFAFAFAF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout = (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N1
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .lut_mask = 64'h030703070F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N25
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q & (
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 .lut_mask = 64'hF3005100FF005500;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N22
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~55 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N46
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y30_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [115] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [10]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & (
// \u0|hps_0|fpga_interfaces|h2f_AWID [10] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[115] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N31
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout & ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) )
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout &
// ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 .lut_mask = 64'hFF0033005F001300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N19
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 .lut_mask = 64'h0023000000230023;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N35
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y21_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y23_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q )))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y23_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [10]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[115] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 .lut_mask = 64'hDDDD0D0D00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[115] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N31
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y25_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[115] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N10
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N58
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N56
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[115] .lut_mask = 64'h000000FF333333FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N7
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N44
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout &
// !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 .lut_mask = 64'h0000F0F0CC00FCF0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N22
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout &
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 .lut_mask = 64'hAAAA00AAA0A000A0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [10] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [10]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[115] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N29
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y23_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[115] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N31
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] )
// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1] ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q &
// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q & \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [115] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [10] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [10] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[115] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N25
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [115] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [10] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [10]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [10]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[115] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N49
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [115]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [115]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [115] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ) #
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115] .lut_mask = 64'hFFEFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[114] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N22
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y23_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[114] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q &
// \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[114] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y25_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y27_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARID [9] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [9] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[114] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y29_N31
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [114] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q & ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q & (
// !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N29
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[114] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N28
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N19
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N13
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout &
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q & !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & (
// ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q & !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 .lut_mask = 64'h2F0F2F0F22002200;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N22
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] )
// ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N31
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N26
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout &
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 .lut_mask = 64'hCCCC0C0CCC000C00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N16
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y23_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N43
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout = (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y20_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q )))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 .lut_mask = 64'hD000D000D0D0D0D0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N28
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N55
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y26_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[114] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N52
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y26_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y33_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h2277227722772277;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N53
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q & ( (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 .lut_mask = 64'h000000001FFF1FFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~53 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )))) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ) # ((\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 .lut_mask = 64'hCF450000CFCF0000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[114] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N37
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout = (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N5
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~54 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) #
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout & (
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 .lut_mask = 64'hF7F700F700000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y32_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [114])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )) ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout &
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout & \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 .lut_mask = 64'h1111010100110001;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARID [9] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [9] & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[114] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N40
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [114] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [9]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[114] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y24_N22
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [114] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [114] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout & (
// (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114] .lut_mask = 64'hFFFFFFF7FFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q
// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]
// & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])))
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0 .lut_mask = 64'h000D000D07070707;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y22_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 .lut_mask = 64'h00280000AAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout =
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF0FFF0FFF0FFF0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h00F000F0FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h088808880CCC0CCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0F0F0F0FFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|src_payload [0] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout
// & ( (\u0|mm_interconnect_0|cmd_mux_015|src_payload [0] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (
// !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &
// (((\u0|mm_interconnect_0|cmd_mux_015|src_payload [0] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout &
// ( !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 .lut_mask = 64'hAAAAAA0303030303;
defparam \u0|mm_interconnect_0|cmd_mux_015|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y21_N14
dffeas \u0|mm_interconnect_0|cmd_mux_015|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[113] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N25
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y23_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[113] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N19
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout = ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[113] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y24_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [113] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[113] .lut_mask = 64'h0000333355557777;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N22
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 .lut_mask = 64'h0057005700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~51 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N25
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[113] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N1
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y28_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [113] ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout
// ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 .lut_mask = 64'h88088888AA0AAAAA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [8] & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N28
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) ) #
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 .lut_mask = 64'h003F003F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~52 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N19
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) #
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout &
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 .lut_mask = 64'hCCCC44440CCC0444;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout = (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N22
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y32_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N19
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 .lut_mask = 64'h0301000003010301;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N43
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[113] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N46
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y25_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [8] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[113] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N52
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [113]))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q & \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ))
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q &
// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y25_N46
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y23_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h2277227722772277;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [113] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [8]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[113] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N19
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y29_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N58
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y21_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N19
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N55
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 .lut_mask = 64'hCC0CCC0C44044404;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N22
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [113] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [8]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [8]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [8] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[113] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N35
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N43
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & (
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q )) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 .lut_mask = 64'h0A0A0A0AFF0A0A0A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8])
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N29
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q & !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q &
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 .lut_mask = 64'hF0F05050C0C04040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [113] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout & ( (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113] .lut_mask = 64'hFFFFFFFFFFFFF7FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46
// ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [16])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46
// ))
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 .lut_mask = 64'h0000FFFF0000303F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout = SUM(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54 = CARRY(( GND ) + ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]))) ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 .lut_mask = 64'h0000F5A000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout & (
// (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[17] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[17] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[17] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1 .lut_mask = 64'h00FF00FF55555555;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal13~1 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal13~1_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & \u0|mm_interconnect_0|router|Equal13~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal13~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal13~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal13~1 .lut_mask = 64'h0000000000110011;
defparam \u0|mm_interconnect_0|router|Equal13~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y29_N37
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router|Equal13~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src7_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7] & ( (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & (\u0|hps_0|fpga_interfaces|h2f_WVALID [0] & \u0|hps_0|fpga_interfaces|h2f_AWVALID [0])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .lut_mask = 64'h000A000A000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (\u0|mm_interconnect_0|router|Equal13~0_combout & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ((\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0007000700770077;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N26
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y32_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N38
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y32_N11
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N29
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q &
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q & ( ((!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q & (
// (!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hCC00CC00CF0FCF0F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_RREADY [0])))
// # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & (\u0|hps_0|fpga_interfaces|h2f_BREADY [0])) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0F550F5500000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0F0F3F3F00000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & (
// ((\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h757575751F1F1F1F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N23
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] &
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q & !\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|rp_valid .lut_mask = 64'hAA00AA0088008800;
defparam \u0|mm_interconnect_0|link_start_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N17
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [112] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[112] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N16
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N35
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N19
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q )) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 .lut_mask = 64'h00F00000AAFAAAAA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N31
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N35
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q )))
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout &
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 .lut_mask = 64'hCCCC00CCC0C000C0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y23_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q )))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N43
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y22_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N22
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N34
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N13
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y23_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [112] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [7]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[112] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N52
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y29_N43
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 .lut_mask = 64'hDD0DDD0D00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[112] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N13
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y25_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[112] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N28
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y25_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q & (
// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q & (
// !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [112] = (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & (\u0|hps_0|fpga_interfaces|h2f_AWID [7]))) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] &
// (((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [7])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [7])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[112] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N16
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARID [7] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [7] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [7] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[112] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N16
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [112] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[112] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N10
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N7
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q & ( ((\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q & (
// (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N19
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N19
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y33_N44
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~49 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [7] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[112] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N46
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y27_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout
// & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout )))) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 .lut_mask = 64'h88CC88CC080C88CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N28
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout = (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y33_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N31
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 .lut_mask = 64'h0555055515551555;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~50 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [112] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [7]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [7]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[112] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N46
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N35
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) #
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 .lut_mask = 64'hAAAA22220AAA0222;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 .lut_mask = 64'h0000000000F30051;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [112] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ) #
// ((\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112] .lut_mask = 64'hFFFFFFFFEFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N1
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y33_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N16
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~47 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N31
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// (\u0|hps_0|fpga_interfaces|h2f_ARID [6] & \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [6] &
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [6] & \u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[111] .lut_mask = 64'h003300330033FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N13
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0303CFCF0303CFCF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y31_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N4
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [111] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 .lut_mask = 64'hC4C400C4CCCC00CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N25
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [6] & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N25
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) ) #
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 .lut_mask = 64'h003F003F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~48 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout = (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N32
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y30_N38
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &
// \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[111] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N31
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) #
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 .lut_mask = 64'hCCCC0C0C44CC040C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 .lut_mask = 64'h0000000000CF0045;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N38
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N58
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [6]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[111] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N13
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y29_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]))
// # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q )))
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y22_N55
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y23_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [6] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N22
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 .lut_mask = 64'hF050F05030103010;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N14
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [111] = (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ((\u0|hps_0|fpga_interfaces|h2f_AWID [6])))) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]
// & (((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [6])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [6])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[111] .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N25
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N23
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y34_N11
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N16
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N49
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & (
// ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 .lut_mask = 64'h08FF08FF08080808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N25
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N31
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q & (
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 .lut_mask = 64'hF0F03030A0A02020;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & (
// (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] &
// \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[111] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N31
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[111] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N16
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N46
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q &
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[111] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N40
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [6] & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[111] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N52
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [111] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [111] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [6]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [6]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & (
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [6] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[111] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N25
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] )
// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1] ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111] & (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [111] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [6] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [6]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [6]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[111] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [111]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[111] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [111]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [111] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ) #
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111] .lut_mask = 64'hFEFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[35] .lut_mask = 64'h3333333333FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y24_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h04370437CCFFCCFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h00000F0C0F0C0F0C;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] &
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q & !\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid .lut_mask = 64'hA0A0A0A080808080;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|src1_valid .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_011|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[110] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N19
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N4
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y24_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & (
// (\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5] &
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) )
// ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[110] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q &
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N22
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N20
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N8
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y34_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N31
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[110] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N53
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout = (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]))
// # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N32
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout &
// (((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 .lut_mask = 64'h00AA00AAC0EAC0EA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ) #
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 .lut_mask = 64'hFAFA00FA00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & (
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] &
// \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[110] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N22
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] )
// ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1] ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[110] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y23_N16
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q & ( ((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q & (
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y27_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [5] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[110] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N49
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [110] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y25_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & (
// (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] &
// \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[110] .lut_mask = 64'h005500550055FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y23_N46
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q & \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ))
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q &
// \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y22_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q )))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h4477447744774477;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N58
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y23_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N28
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y29_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [5]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [5]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [5] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[110] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N58
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y29_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y23_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q )
// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ))) # (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 .lut_mask = 64'h0ACE0ACE00CC00CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 .lut_mask = 64'hF531F53100000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N16
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~46 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout & (
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 .lut_mask = 64'hFF3F551500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5])
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N31
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~45 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N19
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y31_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [110])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y28_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [110] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [5]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & (
// \u0|hps_0|fpga_interfaces|h2f_AWID [5] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[110] .lut_mask = 64'h0000555500FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [110] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y28_N43
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout & ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) )
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout &
// ((\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 .lut_mask = 64'hFF0033005F001300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout = (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [5])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A0A5F5F0A0A5F5F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N28
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y31_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [5] & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N4
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout &
// \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 .lut_mask = 64'h0300010003030101;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [110] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout & ( ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ) #
// ((\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110] .lut_mask = 64'hFFFFFFFFFFFFDFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWLEN [2] & \u0|hps_0|fpga_interfaces|h2f_AWLEN [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 .lut_mask = 64'h0A000A00F5FFF5FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y29_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout $
// (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5] & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout $ (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0 .lut_mask = 64'h0AA00AA05FF55FF5;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (
// (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N17
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout )) )
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N44
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .lut_mask = 64'h40B040B04FBF4FBF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N23
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF0F0F0F03CF03CF0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout &
// (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) )
// ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hFF05FF3700050037;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N38
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]
// & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h00000000C000C000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) )
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h05F505F5F505F505;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N47
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00008000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N32
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00350035FF35FF35;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0C0C0C0CFFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y32_N29
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout
// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5])))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h04FE04FEF40EF40E;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000300030;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h444444444C4C4C4C;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00000000FFC0FFC0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])))) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h5500550055105510;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ( ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout )) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0F3F0033FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y32_N38
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))) ) ) # (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// ((\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A00F0F00A00F3F3;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_payload [0] & ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) #
// ( \u0|mm_interconnect_0|cmd_mux_007|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & (!\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q )) #
// (\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q & !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 .lut_mask = 64'h88888BBB00000FFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 .lut_mask = 64'h000000005F5F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y33_N38
dffeas \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1_combout = ( !\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y33_N44
dffeas \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ) ) ) # (
// \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]
// & ( !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0] & ( (!\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout & \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 .lut_mask = 64'h0A0A0F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y33_N26
dffeas \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [4] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [4] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[109] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N55
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N47
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N2
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N41
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q )))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q &
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 .lut_mask = 64'h44F444F400F000F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N31
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N38
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y27_N41
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q & (
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 .lut_mask = 64'hCCCC0C0C88880808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y23_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N22
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N47
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[109] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N25
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N25
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N49
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 .lut_mask = 64'hDD00DD000D000D00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [109] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[109] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[109] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y23_N13
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y23_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q & (((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q )))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q & (((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 .lut_mask = 64'h111F111F111F111F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [4] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[109] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N16
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N5
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [109] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [4] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [4] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[109] .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N7
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [109] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [4]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [4]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [4] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[109] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N37
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y28_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [109] ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h555555550000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y28_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N14
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y33_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h2277227722772277;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~43 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [4])
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y31_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [109])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N38
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 .lut_mask = 64'hAF002300FF003300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y35_N52
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y31_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N25
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used
// [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0000FFFF0F0F0F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y33_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y33_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N25
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N56
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) ) #
// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 .lut_mask = 64'h003F003F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~44 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout & (
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 .lut_mask = 64'hFF3F551500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 .lut_mask = 64'h0000000033031101;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[109] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y25_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N47
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [109] = (!\u0|hps_0|fpga_interfaces|h2f_ARID [4] & (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (\u0|hps_0|fpga_interfaces|h2f_AWID [4]))) # (\u0|hps_0|fpga_interfaces|h2f_ARID [4] &
// (((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])))
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[109] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N22
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ))
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [109] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ) # ((\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109] .lut_mask = 64'hFFFFEFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y34_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N11
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[108] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N41
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N14
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q &
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q & (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q & !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 .lut_mask = 64'h7530753055005500;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N19
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout &
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 .lut_mask = 64'hAAAA0A0A88880808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N13
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y37_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 .lut_mask = 64'h1115111555555555;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~42 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[108] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N46
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h333333330F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N20
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q & (
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 .lut_mask = 64'hCC440C04CCCC0C0C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[108] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N58
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y28_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h30303F3F30303F3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y28_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y31_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N16
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y33_N50
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 .lut_mask = 64'h0000555500005555;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N16
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 .lut_mask = 64'h050F050F070F070F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~41 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout & (
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 .lut_mask = 64'hDFDF00DF00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N41
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N55
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N52
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )) ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout &
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 .lut_mask = 64'h0505010100050001;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y22_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N4
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [3] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y23_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q )))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y23_N56
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout = (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N34
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [108] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [3]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[108] .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00330033FF33FF33;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N56
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 .lut_mask = 64'hF0FF505500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [108] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[108] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [108])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q )))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h2277227722772277;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y25_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[108] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N22
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[108] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y23_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108])) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q )))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [3] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[108] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N29
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N59
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [108] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [3] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[108] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [108])) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [108] = (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARID [3]))) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] &
// (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [3])) # (\u0|hps_0|fpga_interfaces|h2f_AWID [3])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [3]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[108] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [108]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[108] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [108]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [108] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ) #
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ) # ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108] .lut_mask = 64'hFEFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N13
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y23_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y23_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [107] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[107] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N5
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]))
// # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N58
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N13
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout )))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 .lut_mask = 64'hDD00DD000D000D00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[107] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N25
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ))
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N5
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[107] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N25
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [107] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & (
// (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] &
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) )
// ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[107] .lut_mask = 64'h000F000F000FFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y23_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107])) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q )))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q &
// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q & \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 .lut_mask = 64'h050505FF050505FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N50
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y25_N10
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [2] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N25
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y28_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N8
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[107] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N37
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N35
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y33_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) #
// ((!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q & !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q &
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 .lut_mask = 64'h0A000A00CECCCECC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ) # (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ) #
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 .lut_mask = 64'hFAFA00FA00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [107] = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [2]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & (
// \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[107] .lut_mask = 64'h000000FF333333FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N55
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [107] ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h555555550000FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[107] .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N28
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N11
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N34
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y33_N38
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y33_N44
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N13
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N7
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 .lut_mask = 64'h0057005700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~40 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[107] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N43
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q &
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 .lut_mask = 64'hA0A0F0F020A030F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [107] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [2] & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [2] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [2]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[107] .lut_mask = 64'h003300330033FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N43
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y28_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [107] ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0F0F0F0F0000FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y28_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y33_N5
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y33_N25
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00005555AAAAFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 .lut_mask = 64'h000000005F7F5F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~39 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h05050505F5F5F5F5;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y31_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 .lut_mask = 64'h8C8C008CCCCC00CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y31_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [107])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q )))
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N28
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout )) ) ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout &
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout & \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 .lut_mask = 64'h0505000501010001;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [107] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ) # (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout )) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107] .lut_mask = 64'hFFFFFFFFFFBFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [1])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N22
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N46
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y23_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N16
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [1]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[106] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N8
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [1] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N28
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 .lut_mask = 64'hD000D000D0D0D0D0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y24_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWID [1] & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[106] .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y24_N13
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [106] ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N8
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[106] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00F00FFF00F00FFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y24_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q & \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N5
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[106] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N22
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N5
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N17
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y34_N29
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N25
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q )))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q &
// ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 .lut_mask = 64'h44F444F400F000F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N35
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N2
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout &
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 .lut_mask = 64'hAAAA0A0A88880808;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARID [1] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [1] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[106] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y23_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [106] = (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_AWID [1] & (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]))) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] &
// (((\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [1])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[106] .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N13
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N25
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 .lut_mask = 64'h0037003700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~37 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N37
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y31_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [106]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y30_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [106] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARID [1]) # (\u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & (
// \u0|hps_0|fpga_interfaces|h2f_AWID [1] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[106] .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y25_N31
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N17
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )))) ) )
// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 .lut_mask = 64'hFF0033005F001300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N40
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N40
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N16
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [1] & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N22
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y33_N23
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q &
// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~38 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[106] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N10
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout )))) ) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 .lut_mask = 64'hDD00DD000D00DD00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y32_N53
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y32_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [106])) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y31_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 .lut_mask = 64'h0045000000450045;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [1])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[106] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N58
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [106] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[106] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [106]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[106] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [106])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q )))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [106]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N53
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q & (
// (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q & (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q & (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 .lut_mask = 64'h000055550F0F5F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [106] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ) # (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout )) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106] .lut_mask = 64'hFFFFFBFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y22_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y22_N37
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y23_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N25
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y23_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 .lut_mask = 64'h0000333300003333;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y23_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y23_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y27_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[105] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N28
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &
// ((!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q )))) #
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q )))) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 .lut_mask = 64'h00CC00CCA0ECA0EC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 .lut_mask = 64'hF5F5313100000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[105] .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y23_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y23_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q & ( ((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q )) # (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q & (
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N25
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[105] .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N19
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y30_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [105])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N41
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N34
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y31_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [105])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y31_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N41
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout = (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N13
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N26
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~35 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout & (
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 .lut_mask = 64'hFF5F331300000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N32
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout = (\u0|hps_0|fpga_interfaces|h2f_ARID [0] & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N55
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[105] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N7
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N25
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y33_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N19
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y33_N49
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 .lut_mask = 64'h001F001F00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~36 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N11
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y31_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q & (
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q & (
// !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 .lut_mask = 64'hF5003100FF003300;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 .lut_mask = 64'h000000000A0F0203;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[105] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y25_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y25_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[105] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y27_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [105])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q )))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N25
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q & (
// !\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N31
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N2
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[105] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N20
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N23
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y34_N8
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y34_N13
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y29_N29
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ) # ((!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout &
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 .lut_mask = 64'h00CCF0FC0000F0F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [0])
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y31_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y31_N38
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y27_N5
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q &
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q & (
// !\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 .lut_mask = 64'hF0F000F0A0A000A0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (
// (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0] &
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [0] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) )
// ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[105] .lut_mask = 64'h003300330033FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N1
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h0F0F0F0F55555555;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[105] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y23_N25
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N28
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q )) # (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q & (
// (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data [105] = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ) # (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout )) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105] .lut_mask = 64'hFFFFFBFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout = (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [0])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N55
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y31_N3
cyclonev_lcell_comb \u0|link_start|data_out~feeder (
// Equation(s):
// \u0|link_start|data_out~feeder_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|link_start|data_out~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|link_start|data_out~feeder .extended_lut = "off";
defparam \u0|link_start|data_out~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|link_start|data_out~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant
// [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[81] .lut_mask = 64'h30FF30FF30303030;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N20
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [81]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N35
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y32_N38
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y32_N41
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_007|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_007|src_data [88]) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h222222220F000F00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[86] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [86] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [86] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h0F030F030C000C00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N29
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) #
// (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) #
// (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &
// ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [1])))) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 .lut_mask = 64'h0404040C0CCC0CCC;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]))))
// ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1 .lut_mask = 64'hA888A88888888888;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2])) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ((\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 .lut_mask = 64'h707070708F8F8F8F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 .lut_mask = 64'h3B3B3B3B00000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ) )
// ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2 .lut_mask = 64'h00FF00FF0FF00FF0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 .lut_mask = 64'h00000000AAAA0000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 .lut_mask = 64'hAAAA000000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ) + ( VCC ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout & ((\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARBURST [0])))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout ) # ((!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|hps_0|fpga_interfaces|h2f_ARBURST [1])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 .lut_mask = 64'h0F080F0807000700;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ) + ( VCC ) + ( !VCC ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1 .lut_mask = 64'hAFAF000005050000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [80] = (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout )))) #
// (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout
// ))))
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[80] .lut_mask = 64'h7350735073507350;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N23
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [87] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [87] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_007|src_data [88])))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h8F808F8080808080;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_007|src_data [80])) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|src_data [80]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000E4E4E4E4;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N2
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [86] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [86] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000A000A050F050F;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N5
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [86] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [86] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h0F030F030C000C00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N10
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3])) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & (\u0|hps_0|fpga_interfaces|h2f_ARBURST [1] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout & (
// (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout )))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 .lut_mask = 64'h888A888A00020002;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout )) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout )) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ))))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 .lut_mask = 64'h80A280A280808080;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[79] .lut_mask = 64'h7755775533003300;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N44
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [79] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [79] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [79]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0F030F030C000C00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N8
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ))) ) ) )
// # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h222222AA272727AF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N55
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) )
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) )
// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0003F0F35053F0F3;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N13
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [81] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [81] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h0A0F0A0F0A000A00;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N53
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h00335533FF33FF33;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] &
// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]
// & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 .lut_mask = 64'h00000000000000FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout & (
// (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout )) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 .lut_mask = 64'h80808080A2A2A2A2;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 = CARRY(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout = SUM(( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ) + ( VCC ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout & ( \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout & (
// \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout & ( !\u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARBURST [0] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 .lut_mask = 64'hF0F0000080008000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[82] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N29
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_007|src_data [86])))))
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|src_data [86]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0047004700470047;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y32_N26
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y32_N17
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y32_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_007|src_data [82] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [82] & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [82]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N13
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h111B111BBBBBBBBB;
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N32
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .lut_mask = 64'h2222222200000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N30
cyclonev_lcell_comb \u0|link_start|always0~0 (
// Equation(s):
// \u0|link_start|always0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|link_start|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|link_start|always0~0 .extended_lut = "off";
defparam \u0|link_start|always0~0 .lut_mask = 64'h0000000080008000;
defparam \u0|link_start|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y31_N5
dffeas \u0|link_start|data_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|link_start|data_out~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|link_start|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|link_start|data_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|link_start|data_out .is_wysiwyg = "true";
defparam \u0|link_start|data_out .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y27_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y28_N32
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[86] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N26
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y29_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y29_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_data [87] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_008|src_data [88])))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h0088008850D850D8;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_008|src_data [86])) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000E4E4E4E4;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N55
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_data [88] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [88] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_008|src_data [87])))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hD580D58080808080;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_008|src_data [86] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h00550055000F000F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N41
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [80] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ) )
// ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ) #
// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[80] .lut_mask = 64'h3333BBBB0000AAAA;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N29
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[79] .lut_mask = 64'h7755775533003300;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|cmd_mux_008|src_data [86] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00AA00AA00F000F0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_008|src_data [79] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_data [79]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y28_N16
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h00FF55FF03030303;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_008|src_data [80] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_data [80]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N38
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]
// & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0505FFFF00330033;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N55
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[81] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & !\u0|mm_interconnect_0|cmd_mux_008|src_data [81]) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_data [81]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h0C0C0C0C0F000F00;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N35
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h1F1F1F1F00FF00FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N53
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[82] .lut_mask = 64'h30FF30FF30303030;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N20
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y28_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_008|src_data [86] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|src_data [86]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h00550055000F000F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y28_N28
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y28_N2
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_008|src_data [82] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_data [82] & (
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_data [82]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y28_N50
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h101F101FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y28_N14
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N12
cyclonev_lcell_comb \u0|auto_start|always0~0 (
// Equation(s):
// \u0|auto_start|always0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] &
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|auto_start|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|auto_start|always0~0 .extended_lut = "off";
defparam \u0|auto_start|always0~0 .lut_mask = 64'h0000000080008000;
defparam \u0|auto_start|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y28_N29
dffeas \u0|auto_start|data_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|auto_start|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|auto_start|data_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|auto_start|data_out .is_wysiwyg = "true";
defparam \u0|auto_start|data_out .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector2~0_combout = (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & \A_SPW_TOP|SPW|RX|counter_neg [0])))
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector2~0 .lut_mask = 64'h0080008000800080;
defparam \A_SPW_TOP|SPW|RX|Selector2~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector2~1_combout = (!\A_SPW_TOP|SPW|RX|Selector2~0_combout & ((\A_SPW_TOP|SPW|RX|counter_neg [4]))) # (\A_SPW_TOP|SPW|RX|Selector2~0_combout & (\A_SPW_TOP|SPW|RX|counter_neg [3]))
.dataa(!\A_SPW_TOP|SPW|RX|Selector2~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector2~1 .lut_mask = 64'h11BB11BB11BB11BB;
defparam \A_SPW_TOP|SPW|RX|Selector2~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N38
dffeas \A_SPW_TOP|SPW|RX|counter_neg[4] (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|Selector2~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|counter_neg [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector3~0_combout = ( !\A_SPW_TOP|SPW|RX|is_control~q & ( (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & \A_SPW_TOP|SPW|RX|counter_neg [2]))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|is_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector3~0 .lut_mask = 64'h0080008000000000;
defparam \A_SPW_TOP|SPW|RX|Selector3~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector3~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector3~1_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( ((\A_SPW_TOP|SPW|RX|counter_neg [3] & ((!\A_SPW_TOP|SPW|RX|Selector2~0_combout ) # (\A_SPW_TOP|SPW|RX|counter_neg [4])))) # (\A_SPW_TOP|SPW|RX|Selector3~0_combout ) ) ) # (
// !\A_SPW_TOP|SPW|RX|counter_neg [0] & ( (\A_SPW_TOP|SPW|RX|counter_neg [3] & ((!\A_SPW_TOP|SPW|RX|Selector2~0_combout ) # (\A_SPW_TOP|SPW|RX|counter_neg [4]))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|Selector2~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datac(!\A_SPW_TOP|SPW|RX|Selector3~0_combout ),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector3~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector3~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector3~1 .lut_mask = 64'h223322332F3F2F3F;
defparam \A_SPW_TOP|SPW|RX|Selector3~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|counter_neg[3] (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|Selector3~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|counter_neg [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector1~0_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (((\A_SPW_TOP|SPW|RX|counter_neg [2]) # (\A_SPW_TOP|SPW|RX|counter_neg [1])) # (\A_SPW_TOP|SPW|RX|counter_neg [4])) #
// (\A_SPW_TOP|SPW|RX|counter_neg [3]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [5] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [3] & (\A_SPW_TOP|SPW|RX|counter_neg [4] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] &
// !\A_SPW_TOP|SPW|RX|counter_neg [2]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( !\A_SPW_TOP|SPW|RX|counter_neg [0] ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datae(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector1~0 .lut_mask = 64'h0000FFFF20007FFF;
defparam \A_SPW_TOP|SPW|RX|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|counter_neg[5] (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|Selector1~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|counter_neg [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y14_N53
dffeas \A_SPW_TOP|SPW|RX|control_bit_found (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\din_a~input_o ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_bit_found~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_bit_found .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_bit_found .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~1_combout = ( \A_SPW_TOP|SPW|RX|is_control~q & ( (!\A_SPW_TOP|SPW|RX|counter_neg [2] & ((!\A_SPW_TOP|SPW|RX|counter_neg [5] & ((!\A_SPW_TOP|SPW|RX|counter_neg [1]) # (\A_SPW_TOP|SPW|RX|control_bit_found~q ))) #
// (\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [1])))) # (\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [1]))) ) ) # ( !\A_SPW_TOP|SPW|RX|is_control~q & (
// (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [1] & \A_SPW_TOP|SPW|RX|control_bit_found~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datad(!\A_SPW_TOP|SPW|RX|control_bit_found~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|is_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~1 .lut_mask = 64'h00080008868E868E;
defparam \A_SPW_TOP|SPW|RX|Selector0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~0_combout = ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( (\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & ((!\A_SPW_TOP|SPW|RX|counter_neg [2]) # (!\A_SPW_TOP|SPW|RX|counter_neg [5])))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~0 .lut_mask = 64'h5400540000000000;
defparam \A_SPW_TOP|SPW|RX|Selector0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector0~2_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( \A_SPW_TOP|SPW|RX|counter_neg [3] & ( (\A_SPW_TOP|SPW|RX|is_control~q & !\A_SPW_TOP|SPW|RX|Selector0~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & (
// \A_SPW_TOP|SPW|RX|counter_neg [3] & ( (\A_SPW_TOP|SPW|RX|is_control~q & !\A_SPW_TOP|SPW|RX|Selector0~0_combout ) ) ) ) # ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( (\A_SPW_TOP|SPW|RX|is_control~q &
// !\A_SPW_TOP|SPW|RX|Selector0~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( (!\A_SPW_TOP|SPW|RX|Selector0~0_combout & (((\A_SPW_TOP|SPW|RX|is_control~q )))) # (\A_SPW_TOP|SPW|RX|Selector0~0_combout &
// (\A_SPW_TOP|SPW|RX|Selector0~1_combout & ((\A_SPW_TOP|SPW|RX|counter_neg [0])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|Selector0~1_combout ),
.datab(!\A_SPW_TOP|SPW|RX|is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datad(!\A_SPW_TOP|SPW|RX|Selector0~0_combout ),
.datae(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector0~2 .lut_mask = 64'h3305330033003300;
defparam \A_SPW_TOP|SPW|RX|Selector0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N44
dffeas \A_SPW_TOP|SPW|RX|is_control (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|Selector0~2_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|is_control~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|is_control .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|is_control .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always2~0_combout = LCELL(( \A_SPW_TOP|SPW|RX|always3~0_combout & ( (\A_SPW_TOP|SPW|RX|always2~1_combout & !\A_SPW_TOP|SPW|RX|counter_neg [1]) ) ))
.dataa(!\A_SPW_TOP|SPW|RX|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always2~0 .lut_mask = 64'h0000000044444444;
defparam \A_SPW_TOP|SPW|RX|always2~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data_p~0_combout = ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] & (\A_SPW_TOP|SPW|RX|counter_neg [0] &
// !\A_SPW_TOP|SPW|RX|counter_neg [3]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datae(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|ready_data_p~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data_p~0 .lut_mask = 64'h0000000008000000;
defparam \A_SPW_TOP|SPW|RX|ready_data_p~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data_p~combout = LCELL(( \A_SPW_TOP|SPW|RX|always3~0_combout & ( \A_SPW_TOP|SPW|RX|ready_data_p~0_combout & ( !\A_SPW_TOP|SPW|RX|always2~0_combout ) ) ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|always2~0_combout ),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|ready_data_p~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data_p .lut_mask = 64'h000000000000F0F0;
defparam \A_SPW_TOP|SPW|RX|ready_data_p .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data_p_r~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout = ( \A_SPW_TOP|SPW|RX|ready_data~combout & ( (!\A_SPW_TOP|SPW|RX|is_control~q ) # (\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|ready_data~combout & ( (\A_SPW_TOP|SPW|RX|ready_data_p~combout
// & ((!\A_SPW_TOP|SPW|RX|is_control~q ) # (\A_SPW_TOP|SPW|RX|ready_data_p_r~q ))) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.datad(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|ready_data~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .lut_mask = 64'h0C0F0C0FCCFFCCFF;
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N56
dffeas \A_SPW_TOP|SPW|RX|ready_data_p_r (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|ready_data_p_r .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_control_p_r~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout = (!\A_SPW_TOP|SPW|RX|always1~0_combout & (\A_SPW_TOP|SPW|RX|always2~0_combout & ((\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) # (\A_SPW_TOP|SPW|RX|is_control~q )))) # (\A_SPW_TOP|SPW|RX|always1~0_combout &
// (((\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) # (\A_SPW_TOP|SPW|RX|is_control~q )))
.dataa(!\A_SPW_TOP|SPW|RX|always1~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|always2~0_combout ),
.datad(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r~0 .lut_mask = 64'h135F135F135F135F;
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N26
dffeas \A_SPW_TOP|SPW|RX|ready_control_p_r (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|ready_control_p_r .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_control~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_control~0_combout = ((\A_SPW_TOP|SPW|RX|last_is_control~q & !\A_SPW_TOP|SPW|RX|ready_data_p_r~q )) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datad(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|last_is_control~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .lut_mask = 64'h30FF30FF30FF30FF;
defparam \A_SPW_TOP|SPW|RX|last_is_control~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_control~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_control~feeder_combout = ( \A_SPW_TOP|SPW|RX|last_is_control~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|last_is_control~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|last_is_control~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_control~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_control~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|last_is_control~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y14_N38
dffeas \A_SPW_TOP|SPW|RX|last_is_control (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|last_is_control~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|last_is_control~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_control .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_is_control .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y14_N32
dffeas \A_SPW_TOP|SPW|RX|bit_c_0 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\din_a~input_o ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_c_0~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_0 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_r[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_r[0]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_c_0~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|bit_c_0~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|control_r[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_r[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|control_r[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y18_N2
dffeas \A_SPW_TOP|SPW|RX|control_r[0] (
.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
.d(\A_SPW_TOP|SPW|RX|control_r[0]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_r [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y18_N56
dffeas \A_SPW_TOP|SPW|RX|control_p_r[0] (
.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_r [0]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_p_r [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N26
dffeas \A_SPW_TOP|SPW|RX|control[0] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_p_r [0]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N53
dffeas \A_SPW_TOP|SPW|RX|control_l_r[0] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control [0]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_l_r [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_l_r[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y14_N1
dffeas \A_SPW_TOP|SPW|RX|bit_c_1 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\din_a~input_o ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_c_1~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_1 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_1 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_r[1]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_c_1~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|bit_c_1~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|control_r[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y18_N47
dffeas \A_SPW_TOP|SPW|RX|control_r[1] (
.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
.d(\A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y18_N28
dffeas \A_SPW_TOP|SPW|RX|control_p_r[1] (
.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_r [1]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_p_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|control[1] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_p_r [1]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N35
dffeas \A_SPW_TOP|SPW|RX|control_l_r[1] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control [1]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_l_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_l_r[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y14_N37
dffeas \A_SPW_TOP|SPW|RX|bit_c_2 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_c_0~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_c_2~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_2 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_2 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_r[2]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_r[2]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_c_2~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|bit_c_2~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|control_r[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_r[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|control_r[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y18_N43
dffeas \A_SPW_TOP|SPW|RX|control_r[2] (
.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
.d(\A_SPW_TOP|SPW|RX|control_r[2]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y18_N49
dffeas \A_SPW_TOP|SPW|RX|control_p_r[2] (
.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_r [2]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_p_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N17
dffeas \A_SPW_TOP|SPW|RX|control[2] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_p_r [2]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N49
dffeas \A_SPW_TOP|SPW|RX|control_l_r[2] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control [2]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_l_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_l_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_l_r[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always8~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always8~0_combout = ( \A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [0] & ( (!\A_SPW_TOP|SPW|RX|control [1] & ((!\A_SPW_TOP|SPW|RX|control_l_r [0]) # ((!\A_SPW_TOP|SPW|RX|control_l_r [1]) # (!\A_SPW_TOP|SPW|RX|control_l_r
// [2])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control_l_r [0]),
.datab(!\A_SPW_TOP|SPW|RX|control [1]),
.datac(!\A_SPW_TOP|SPW|RX|control_l_r [1]),
.datad(!\A_SPW_TOP|SPW|RX|control_l_r [2]),
.datae(!\A_SPW_TOP|SPW|RX|control [2]),
.dataf(!\A_SPW_TOP|SPW|RX|control [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always8~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always8~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always8~0 .lut_mask = 64'h0000CCC800000000;
defparam \A_SPW_TOP|SPW|RX|always8~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always11~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always11~0_combout = ( \A_SPW_TOP|SPW|RX|always8~0_combout & ( \A_SPW_TOP|SPW|RX|last_is_control~q ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|always8~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always11~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always11~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always11~0 .lut_mask = 64'h0000000033333333;
defparam \A_SPW_TOP|SPW|RX|always11~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N44
dffeas \A_SPW_TOP|SPW|RX|rx_got_fct_fsm (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|always11~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_fct_fsm .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_data~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_data~0_combout = ( \A_SPW_TOP|SPW|RX|control [1] & ( (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ((!\A_SPW_TOP|SPW|RX|control [0]) # (!\A_SPW_TOP|SPW|RX|control [2]))) ) ) # ( !\A_SPW_TOP|SPW|RX|control [1] & (
// !\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [0]),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datad(!\A_SPW_TOP|SPW|RX|control [2]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|control [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|last_is_data~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_data~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_data~0 .lut_mask = 64'hF0F0F0F0F0A0F0A0;
defparam \A_SPW_TOP|SPW|RX|last_is_data~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_data~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_data~1_combout = (\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|last_is_data~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_data~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_data~1 .lut_mask = 64'h33FF33FF33FF33FF;
defparam \A_SPW_TOP|SPW|RX|last_is_data~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y14_N41
dffeas \A_SPW_TOP|SPW|RX|last_is_data (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|last_is_data~0_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|last_is_data~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|last_is_data~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_is_data .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|last_is_timec~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|last_is_timec~0_combout = ( \A_SPW_TOP|SPW|RX|control [1] & ( (\A_SPW_TOP|SPW|RX|control [0] & (!\A_SPW_TOP|SPW|RX|ready_control_p_r~q & \A_SPW_TOP|SPW|RX|control [2])) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [0]),
.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|control [2]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|control [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|last_is_timec~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .lut_mask = 64'h0000000000440044;
defparam \A_SPW_TOP|SPW|RX|last_is_timec~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y14_N59
dffeas \A_SPW_TOP|SPW|RX|last_is_timec (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|last_is_timec~0_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|last_is_data~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_is_timec .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_is_timec .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_nchar~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout = ( \A_SPW_TOP|SPW|RX|rx_got_nchar~q & ( ((\A_SPW_TOP|SPW|RX|last_is_timec~q ) # (\A_SPW_TOP|SPW|RX|last_is_control~q )) # (\A_SPW_TOP|SPW|RX|last_is_data~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_nchar~q & (
// \A_SPW_TOP|SPW|RX|last_is_data~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~0 .lut_mask = 64'h555555557F7F7F7F;
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|rx_got_nchar (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_nchar .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_time_code~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout = ((\A_SPW_TOP|SPW|RX|last_is_control~q & \A_SPW_TOP|SPW|RX|rx_got_time_code~q )) # (\A_SPW_TOP|SPW|RX|last_is_timec~q )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.datad(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code~0 .lut_mask = 64'h0F3F0F3F0F3F0F3F;
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N56
dffeas \A_SPW_TOP|SPW|RX|rx_got_time_code (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_time_code .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always0~0_combout = ( !\A_SPW_TOP|SPW|RX|rx_error~q & ( !\A_SPW_TOP|SPW|RX|rx_got_time_code~q & ( (!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q & !\A_SPW_TOP|SPW|RX|rx_got_nchar~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always0~0 .lut_mask = 64'hA0A0000000000000;
defparam \A_SPW_TOP|SPW|FSM|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y8_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~2_combout = ( !\A_SPW_TOP|SPW|FSM|after64us [10] & ( !\A_SPW_TOP|SPW|FSM|after64us [11] & ( (\A_SPW_TOP|SPW|FSM|after64us [9] & (!\A_SPW_TOP|SPW|FSM|after64us [7] & !\A_SPW_TOP|SPW|FSM|after64us [8])) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [7]),
.datad(!\A_SPW_TOP|SPW|FSM|after64us [8]),
.datae(!\A_SPW_TOP|SPW|FSM|after64us [10]),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~2 .lut_mask = 64'h5000000000000000;
defparam \A_SPW_TOP|SPW|FSM|Equal2~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_got_null~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_got_null~0_combout = ( \A_SPW_TOP|SPW|RX|rx_got_null~q & ( (\A_SPW_TOP|SPW|RX|last_is_timec~q ) # (\A_SPW_TOP|SPW|RX|last_is_control~q ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_got_null~q & ( (\A_SPW_TOP|SPW|RX|last_is_control~q &
// !\A_SPW_TOP|SPW|RX|last_is_timec~q ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_got_null~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .lut_mask = 64'h303030303F3F3F3F;
defparam \A_SPW_TOP|SPW|RX|rx_got_null~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|rx_got_null (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_got_null~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_null .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_null .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~2_combout = ( \din_a~input_o & ( \A_SPW_TOP|SPW|RX|rx_got_null~q ) ) # ( !\din_a~input_o & ( (\A_SPW_TOP|SPW|RX|rx_got_null~q & \sin_a~input_o ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.datac(!\sin_a~input_o ),
.datad(gnd),
.datae(gnd),
.dataf(!\din_a~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~2 .lut_mask = 64'h0303030333333333;
defparam \A_SPW_TOP|SPW|FSM|Selector4~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y13_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~1_combout = ( \A_SPW_TOP|SPW|FSM|Equal0~0_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & (\A_SPW_TOP|SPW|FSM|Equal0~1_combout & \A_SPW_TOP|SPW|FSM|Equal0~2_combout
// )) ) ) ) # ( \A_SPW_TOP|SPW|FSM|Equal0~0_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & ((!\A_SPW_TOP|SPW|FSM|always0~0_combout ) # ((\A_SPW_TOP|SPW|FSM|Equal0~1_combout &
// \A_SPW_TOP|SPW|FSM|Equal0~2_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~0_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & !\A_SPW_TOP|SPW|FSM|always0~0_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datab(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~1 .lut_mask = 64'h4444444500000005;
defparam \A_SPW_TOP|SPW|FSM|Selector4~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y13_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always2~0_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( \A_SPW_TOP|SPW|FSM|Selector4~2_combout & ( (\A_SPW_TOP|SPW|FSM|always0~0_combout & ((!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ) # ((!\A_SPW_TOP|SPW|FSM|Equal0~0_combout )
// # (!\A_SPW_TOP|SPW|FSM|Equal0~2_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|Selector4~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|always2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always2~0 .lut_mask = 64'h0000000000003332;
defparam \A_SPW_TOP|SPW|FSM|always2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always0~1_combout = ( !\A_SPW_TOP|SPW|RX|rx_got_nchar~q & ( (!\A_SPW_TOP|SPW|RX|rx_got_time_code~q & !\A_SPW_TOP|SPW|RX|rx_error~q ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|always0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always0~1 .lut_mask = 64'hA0A0A0A000000000;
defparam \A_SPW_TOP|SPW|FSM|always0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector2~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector2~2_combout = ( \A_SPW_TOP|SPW|FSM|always0~1_combout & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ) # ((!\A_SPW_TOP|SPW|FSM|Selector4~2_combout & !\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q )) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector2~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector2~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector2~2 .lut_mask = 64'h00000000EECCEECC;
defparam \A_SPW_TOP|SPW|FSM|Selector2~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector2~1_combout = ( \A_SPW_TOP|SPW|FSM|Selector2~2_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( (\A_SPW_TOP|SPW|FSM|Equal0~1_combout & (\A_SPW_TOP|SPW|FSM|Equal0~2_combout & \A_SPW_TOP|SPW|FSM|Equal0~0_combout )) ) )
// ) # ( !\A_SPW_TOP|SPW|FSM|Selector2~2_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q ) ) # ( \A_SPW_TOP|SPW|FSM|Selector2~2_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( (\A_SPW_TOP|SPW|FSM|Equal0~1_combout &
// (\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & (\A_SPW_TOP|SPW|FSM|Equal0~2_combout & \A_SPW_TOP|SPW|FSM|Equal0~0_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector2~2_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q & (
// \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Selector2~2_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector2~1 .lut_mask = 64'h33330001FFFF0005;
defparam \A_SPW_TOP|SPW|FSM|Selector2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~6_combout = ( \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~6 .lut_mask = 64'h000000000F0F0F0F;
defparam \A_SPW_TOP|SPW|FSM|Selector4~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~0_combout = ( \A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & ( \A_SPW_TOP|SPW|FSM|Selector4~6_combout ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~2_combout & (
// \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & ( \A_SPW_TOP|SPW|FSM|Selector4~6_combout ) ) ) # ( \A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & ( (\A_SPW_TOP|SPW|FSM|Selector4~6_combout &
// (\A_SPW_TOP|SPW|FSM|always0~1_combout & ((!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ) # (!\A_SPW_TOP|SPW|FSM|Equal0~1_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & (
// (\A_SPW_TOP|SPW|FSM|Selector4~6_combout & \A_SPW_TOP|SPW|FSM|always0~1_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Selector4~6_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~0 .lut_mask = 64'h0033003233333333;
defparam \A_SPW_TOP|SPW|FSM|Selector4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout = (\u0|hps_0|fpga_interfaces|h2f_WDATA [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [81] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & (
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & (
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[81] .lut_mask = 64'h3300FFFF33003300;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y29_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[86] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y29_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y29_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [88] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [88] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_009|src_data [87])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h1D111D110C000C00;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N46
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y29_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [80] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ) # ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[80] .lut_mask = 64'h55005500F5F0F5F0;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [88] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [88] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_009|src_data [87])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_data [87]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hE222E222C000C000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & \u0|mm_interconnect_0|cmd_mux_009|src_data [86]) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0505050500550055;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// !\u0|mm_interconnect_0|cmd_mux_009|src_data [86]) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h4444444455005500;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N55
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[79] .lut_mask = 64'h55F555F500F000F0;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N29
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_009|src_data [79]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [79]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N14
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & (
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout &
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h222722272227AAAF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N49
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout &
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [80] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [80] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])
// # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [80]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00BB00BB00880088;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N16
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ))))
// ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1] & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h04040437CCCCCCFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N19
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] &
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]
// & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_009|src_data [81]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [81]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y29_N25
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h000C333FCCCCFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout = (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y29_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout &
// !\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [82] = ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout
// & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[82] .lut_mask = 64'h00AA00AAF0FAF0FA;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y28_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N22
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_009|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000022772277;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y29_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_009|src_data [82] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_data [82] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_data [82]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h05270527AFAFAFAF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N17
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N15
cyclonev_lcell_comb \u0|link_disable|always0~0 (
// Equation(s):
// \u0|link_disable|always0~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg
// [3]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|link_disable|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|link_disable|always0~0 .extended_lut = "off";
defparam \u0|link_disable|always0~0 .lut_mask = 64'h0800080000000000;
defparam \u0|link_disable|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N53
dffeas \u0|link_disable|data_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|link_disable|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|link_disable|data_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|link_disable|data_out .is_wysiwyg = "true";
defparam \u0|link_disable|data_out .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~3_combout = (!\u0|link_disable|data_out~q & (((\u0|auto_start|data_out~q & \A_SPW_TOP|SPW|RX|rx_got_null~q )) # (\u0|link_start|data_out~q )))
.dataa(!\u0|auto_start|data_out~q ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.datac(!\u0|link_disable|data_out~q ),
.datad(!\u0|link_start|data_out~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~3 .lut_mask = 64'h10F010F010F010F0;
defparam \A_SPW_TOP|SPW|FSM|Selector4~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~4_combout = ( \A_SPW_TOP|SPW|FSM|always0~0_combout & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.run~q & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & ((!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ) #
// (!\A_SPW_TOP|SPW|FSM|Selector4~3_combout )))) ) ) # ( !\A_SPW_TOP|SPW|FSM|always0~0_combout & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.run~q & (!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q )) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datad(!\A_SPW_TOP|SPW|FSM|Selector4~3_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~4 .lut_mask = 64'h080808080A080A08;
defparam \A_SPW_TOP|SPW|FSM|Selector4~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector4~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector4~5_combout = ( \A_SPW_TOP|SPW|FSM|Selector4~0_combout & ( \A_SPW_TOP|SPW|FSM|Selector4~4_combout & ( \A_SPW_TOP|SPW|FSM|always2~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector4~0_combout & (
// \A_SPW_TOP|SPW|FSM|Selector4~4_combout & ( ((!\A_SPW_TOP|SPW|FSM|Selector4~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & !\A_SPW_TOP|SPW|FSM|Selector2~1_combout ))) # (\A_SPW_TOP|SPW|FSM|always2~0_combout ) ) ) ) # (
// \A_SPW_TOP|SPW|FSM|Selector4~0_combout & ( !\A_SPW_TOP|SPW|FSM|Selector4~4_combout & ( \A_SPW_TOP|SPW|FSM|always2~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector4~0_combout & ( !\A_SPW_TOP|SPW|FSM|Selector4~4_combout & (
// \A_SPW_TOP|SPW|FSM|always2~0_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector4~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datac(!\A_SPW_TOP|SPW|FSM|always2~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Selector2~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Selector4~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector4~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector4~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector4~5 .lut_mask = 64'h0F0F0F0F2F0F0F0F;
defparam \A_SPW_TOP|SPW|FSM|Selector4~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N41
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.connecting (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|Selector4~5_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.connecting .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.connecting .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector2~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector2~5_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( (!\A_SPW_TOP|SPW|RX|rx_got_time_code~q & (!\A_SPW_TOP|SPW|RX|rx_error~q & (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q & \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ))) ) ) # (
// !\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
.datab(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datac(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
.datad(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector2~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector2~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector2~5 .lut_mask = 64'h00FF00FF00800080;
defparam \A_SPW_TOP|SPW|FSM|Selector2~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector2~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector2~3_combout = ( \u0|link_start|data_out~q & ( \A_SPW_TOP|SPW|RX|rx_got_null~q & ( (!\u0|link_disable|data_out~q ) # ((\sin_a~input_o & \A_SPW_TOP|SPW|FSM|state_fsm.started~q )) ) ) ) # ( !\u0|link_start|data_out~q & (
// \A_SPW_TOP|SPW|RX|rx_got_null~q & ( (!\sin_a~input_o & (((!\u0|link_disable|data_out~q & \u0|auto_start|data_out~q )))) # (\sin_a~input_o & (((!\u0|link_disable|data_out~q & \u0|auto_start|data_out~q )) # (\A_SPW_TOP|SPW|FSM|state_fsm.started~q ))) )
// ) ) # ( \u0|link_start|data_out~q & ( !\A_SPW_TOP|SPW|RX|rx_got_null~q & ( !\u0|link_disable|data_out~q ) ) )
.dataa(!\sin_a~input_o ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datac(!\u0|link_disable|data_out~q ),
.datad(!\u0|auto_start|data_out~q ),
.datae(!\u0|link_start|data_out~q ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector2~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector2~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector2~3 .lut_mask = 64'h0000F0F011F1F1F1;
defparam \A_SPW_TOP|SPW|FSM|Selector2~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector2~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector2~4_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.ready~q & ( \din_a~input_o & ( (!\A_SPW_TOP|SPW|FSM|Selector2~3_combout & (\A_SPW_TOP|SPW|FSM|always0~0_combout & ((!\A_SPW_TOP|SPW|RX|rx_got_null~q ) #
// (!\A_SPW_TOP|SPW|FSM|state_fsm.started~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & ( \din_a~input_o & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q ) ) ) # ( \A_SPW_TOP|SPW|FSM|state_fsm.ready~q & ( !\din_a~input_o & (
// (!\A_SPW_TOP|SPW|FSM|Selector2~3_combout & \A_SPW_TOP|SPW|FSM|always0~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & ( !\din_a~input_o & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector2~3_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.datac(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datae(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.dataf(!\din_a~input_o ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector2~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector2~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector2~4 .lut_mask = 64'hFF000A0AFF000A08;
defparam \A_SPW_TOP|SPW|FSM|Selector2~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector2~0_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( \A_SPW_TOP|SPW|FSM|Selector2~4_combout & ( (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout & \A_SPW_TOP|SPW|FSM|Selector2~5_combout ) ) ) ) # (
// !\A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( \A_SPW_TOP|SPW|FSM|Selector2~4_combout & ( (!\A_SPW_TOP|SPW|FSM|Equal0~3_combout & (((\A_SPW_TOP|SPW|FSM|Selector2~5_combout )))) # (\A_SPW_TOP|SPW|FSM|Equal0~3_combout &
// (!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ((\A_SPW_TOP|SPW|FSM|Selector2~5_combout ) # (\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datab(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datad(!\A_SPW_TOP|SPW|FSM|Selector2~5_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|Selector2~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector2~0 .lut_mask = 64'h0000000010FC00CC;
defparam \A_SPW_TOP|SPW|FSM|Selector2~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N32
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.ready (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|Selector2~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.ready .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.ready .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector3~0_combout = ( \u0|link_start|data_out~q & ( \A_SPW_TOP|SPW|RX|rx_got_null~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & (\A_SPW_TOP|SPW|FSM|always0~0_combout & !\u0|link_disable|data_out~q )) ) ) ) # (
// !\u0|link_start|data_out~q & ( \A_SPW_TOP|SPW|RX|rx_got_null~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & (\A_SPW_TOP|SPW|FSM|always0~0_combout & (\u0|auto_start|data_out~q & !\u0|link_disable|data_out~q ))) ) ) ) # ( \u0|link_start|data_out~q & (
// !\A_SPW_TOP|SPW|RX|rx_got_null~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & (\A_SPW_TOP|SPW|FSM|always0~0_combout & !\u0|link_disable|data_out~q )) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.datab(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datac(!\u0|auto_start|data_out~q ),
.datad(!\u0|link_disable|data_out~q ),
.datae(!\u0|link_start|data_out~q ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector3~0 .lut_mask = 64'h0000110001001100;
defparam \A_SPW_TOP|SPW|FSM|Selector3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector3~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector3~1_combout = ( \A_SPW_TOP|SPW|FSM|Selector4~0_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( \A_SPW_TOP|SPW|FSM|Selector3~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector4~0_combout & (
// \A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( ((\A_SPW_TOP|SPW|FSM|Selector4~4_combout & (!\A_SPW_TOP|SPW|FSM|Selector4~1_combout & !\A_SPW_TOP|SPW|FSM|Selector2~1_combout ))) # (\A_SPW_TOP|SPW|FSM|Selector3~0_combout ) ) ) ) # (
// \A_SPW_TOP|SPW|FSM|Selector4~0_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( \A_SPW_TOP|SPW|FSM|Selector3~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Selector4~0_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q & (
// (\A_SPW_TOP|SPW|FSM|Selector3~0_combout & ((!\A_SPW_TOP|SPW|FSM|Selector4~4_combout ) # ((\A_SPW_TOP|SPW|FSM|Selector2~1_combout ) # (\A_SPW_TOP|SPW|FSM|Selector4~1_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector3~0_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Selector4~4_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Selector4~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Selector2~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Selector4~0_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector3~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector3~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector3~1 .lut_mask = 64'h4555555575555555;
defparam \A_SPW_TOP|SPW|FSM|Selector3~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N17
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.started (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|Selector3~1_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.started .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.started .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector1~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector1~2_combout = ( !\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q & ( !\A_SPW_TOP|SPW|RX|rx_got_time_code~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|rx_got_time_code~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector1~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector1~2 .lut_mask = 64'hF0F0F0F000000000;
defparam \A_SPW_TOP|SPW|FSM|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector1~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector1~1_combout = ( \A_SPW_TOP|SPW|FSM|Equal0~0_combout & ( !\A_SPW_TOP|SPW|RX|rx_error~q & ( (\A_SPW_TOP|SPW|FSM|Selector1~2_combout & (!\A_SPW_TOP|SPW|RX|rx_got_nchar~q & ((!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ) #
// (!\A_SPW_TOP|SPW|FSM|Equal0~1_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~0_combout & ( !\A_SPW_TOP|SPW|RX|rx_error~q & ( (\A_SPW_TOP|SPW|FSM|Selector1~2_combout & !\A_SPW_TOP|SPW|RX|rx_got_nchar~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector1~2_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datad(!\A_SPW_TOP|SPW|RX|rx_got_nchar~q ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector1~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector1~1 .lut_mask = 64'h5500540000000000;
defparam \A_SPW_TOP|SPW|FSM|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~13_combout = ( !\db_system_spwulight_b|aux_pb~q & ( (!\A_SPW_TOP|SPW|FSM|Selector4~2_combout ) # ((!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ) # (!\A_SPW_TOP|SPW|FSM|Selector1~1_combout )) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Selector1~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\db_system_spwulight_b|aux_pb~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~13 .lut_mask = 64'hFEFEFEFE00000000;
defparam \A_SPW_TOP|SPW|FSM|after128us~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~29 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~29_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|SPW|FSM|Add0~30 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~29_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~30 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~29 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~29 .lut_mask = 64'h0000000000000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~8 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~8_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~29_sumout & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout &
// (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & !\A_SPW_TOP|SPW|FSM|always2~1_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datab(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datad(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~29_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~8 .lut_mask = 64'h0000000000000800;
defparam \A_SPW_TOP|SPW|FSM|after128us~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N17
dffeas \A_SPW_TOP|SPW|FSM|after128us[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~8_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~25 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~25_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~30 ))
// \A_SPW_TOP|SPW|FSM|Add0~26 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [1] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~30 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~30 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~25_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~26 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~25 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add0~25 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~21 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~21_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~26 ))
// \A_SPW_TOP|SPW|FSM|Add0~22 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [2] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~26 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~26 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~21_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~22 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~6 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~6_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~21_sumout & ( (!\A_SPW_TOP|SPW|FSM|always2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & (!\A_SPW_TOP|SPW|FSM|after128us [11]
// & !\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datad(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~6 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|after128us~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N32
dffeas \A_SPW_TOP|SPW|FSM|after128us[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~6_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~17 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~17_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~22 ))
// \A_SPW_TOP|SPW|FSM|Add0~18 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [3] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~22 ))
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [3]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~22 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~17_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~18 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~17 .lut_mask = 64'h0000FFFF00005555;
defparam \A_SPW_TOP|SPW|FSM|Add0~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~5_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~17_sumout & ( (!\A_SPW_TOP|SPW|FSM|always2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q &
// (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout & !\A_SPW_TOP|SPW|FSM|after128us [11]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~17_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~5 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|after128us~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N35
dffeas \A_SPW_TOP|SPW|FSM|after128us[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~5_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~13 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~13_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~18 ))
// \A_SPW_TOP|SPW|FSM|Add0~14 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [4] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~18 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~18 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~13_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~9_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~14 ))
// \A_SPW_TOP|SPW|FSM|Add0~10 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [5] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~9_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~3_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( !\A_SPW_TOP|SPW|FSM|after128us [11] & ( (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q &
// (!\A_SPW_TOP|SPW|FSM|always2~1_combout & \A_SPW_TOP|SPW|FSM|Add0~9_sumout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Add0~9_sumout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~3 .lut_mask = 64'h0000002000000000;
defparam \A_SPW_TOP|SPW|FSM|after128us~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N50
dffeas \A_SPW_TOP|SPW|FSM|after128us[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~3_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~5 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~5_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~10 ))
// \A_SPW_TOP|SPW|FSM|Add0~6 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [6] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~5_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~2_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( !\A_SPW_TOP|SPW|FSM|after128us [11] & ( (!\A_SPW_TOP|SPW|FSM|always2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & (\A_SPW_TOP|SPW|FSM|Add0~5_sumout
// & !\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Add0~5_sumout ),
.datad(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~2 .lut_mask = 64'h0000020000000000;
defparam \A_SPW_TOP|SPW|FSM|after128us~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N5
dffeas \A_SPW_TOP|SPW|FSM|after128us[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~2_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~1_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~6 ))
// \A_SPW_TOP|SPW|FSM|Add0~2 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [7] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [7]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~1_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~2 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~1_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( !\A_SPW_TOP|SPW|FSM|after128us [11] & ( (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout & (\A_SPW_TOP|SPW|FSM|Add0~1_sumout &
// (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & !\A_SPW_TOP|SPW|FSM|always2~1_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Add0~1_sumout ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datad(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~1 .lut_mask = 64'h0000020000000000;
defparam \A_SPW_TOP|SPW|FSM|after128us~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N59
dffeas \A_SPW_TOP|SPW|FSM|after128us[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~1_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~45 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~45_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~2 ))
// \A_SPW_TOP|SPW|FSM|Add0~46 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [8] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~2 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~2 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~45_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~46 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~45 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~45 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~45 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~12 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~12_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~45_sumout & ( (!\A_SPW_TOP|SPW|FSM|always2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q &
// (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout & !\A_SPW_TOP|SPW|FSM|after128us [11]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~45_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~12 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|after128us~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N29
dffeas \A_SPW_TOP|SPW|FSM|after128us[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~12_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~41 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~41_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~46 ))
// \A_SPW_TOP|SPW|FSM|Add0~42 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [9] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~46 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~46 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~41_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~42 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~41 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~41 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~41 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~11 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~11_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~41_sumout & ( (!\A_SPW_TOP|SPW|FSM|always2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & (!\A_SPW_TOP|SPW|FSM|after128us
// [11] & !\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datad(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~41_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~11 .lut_mask = 64'h0000000000002000;
defparam \A_SPW_TOP|SPW|FSM|after128us~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N26
dffeas \A_SPW_TOP|SPW|FSM|after128us[9] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~11_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~37 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~37_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~42 ))
// \A_SPW_TOP|SPW|FSM|Add0~38 = CARRY(( \A_SPW_TOP|SPW|FSM|after128us [10] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~42 ))
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|after128us [10]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~42 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~37_sumout ),
.cout(\A_SPW_TOP|SPW|FSM|Add0~38 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~37 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~37 .lut_mask = 64'h0000FFFF00003333;
defparam \A_SPW_TOP|SPW|FSM|Add0~37 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~10 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~10_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~37_sumout & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout &
// (!\A_SPW_TOP|SPW|FSM|always2~1_combout & \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datab(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~37_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~10 .lut_mask = 64'h0000000000000080;
defparam \A_SPW_TOP|SPW|FSM|after128us~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N14
dffeas \A_SPW_TOP|SPW|FSM|after128us[10] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~10_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [10]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~2_combout = ( !\A_SPW_TOP|SPW|FSM|after128us [9] & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & (\A_SPW_TOP|SPW|FSM|after128us [10] & !\A_SPW_TOP|SPW|FSM|after128us [8])) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [10]),
.datad(!\A_SPW_TOP|SPW|FSM|after128us [8]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~2 .lut_mask = 64'h0A000A0000000000;
defparam \A_SPW_TOP|SPW|FSM|Equal0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~3_combout = (\A_SPW_TOP|SPW|FSM|Equal0~0_combout & (\A_SPW_TOP|SPW|FSM|Equal0~2_combout & \A_SPW_TOP|SPW|FSM|Equal0~1_combout ))
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~3 .lut_mask = 64'h0005000500050005;
defparam \A_SPW_TOP|SPW|FSM|Equal0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector1~0_combout = ( \A_SPW_TOP|SPW|FSM|Equal2~1_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & ( (!\A_SPW_TOP|SPW|FSM|Equal2~2_combout & (\A_SPW_TOP|SPW|FSM|always0~0_combout & ((!\A_SPW_TOP|SPW|FSM|Equal0~3_combout
// )))) # (\A_SPW_TOP|SPW|FSM|Equal2~2_combout & ((!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ) # ((\A_SPW_TOP|SPW|FSM|always0~0_combout & !\A_SPW_TOP|SPW|FSM|Equal0~3_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal2~1_combout & (
// \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & ( (\A_SPW_TOP|SPW|FSM|always0~0_combout & !\A_SPW_TOP|SPW|FSM|Equal0~3_combout ) ) ) ) # ( \A_SPW_TOP|SPW|FSM|Equal2~1_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & (
// (\A_SPW_TOP|SPW|FSM|Equal2~2_combout & !\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal2~1_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector1~0 .lut_mask = 64'h0000505033007350;
defparam \A_SPW_TOP|SPW|FSM|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N53
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.error_wait (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|Selector1~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_wait .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_wait .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|always2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|always2~1_combout = ( !\A_SPW_TOP|SPW|FSM|state_fsm.started~q & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q & !\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|always2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|always2~1 .lut_mask = 64'h8888888800000000;
defparam \A_SPW_TOP|SPW|FSM|always2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~4 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~4_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( !\A_SPW_TOP|SPW|FSM|after128us [11] & ( (!\A_SPW_TOP|SPW|FSM|always2~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & (\A_SPW_TOP|SPW|FSM|Add0~13_sumout
// & !\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Add0~13_sumout ),
.datad(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~4 .lut_mask = 64'h0000020000000000;
defparam \A_SPW_TOP|SPW|FSM|after128us~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N8
dffeas \A_SPW_TOP|SPW|FSM|after128us[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~4_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~0_combout = ( \A_SPW_TOP|SPW|FSM|after128us [6] & ( \A_SPW_TOP|SPW|FSM|after128us [2] & ( (\A_SPW_TOP|SPW|FSM|after128us [4] & (\A_SPW_TOP|SPW|FSM|after128us [7] & (\A_SPW_TOP|SPW|FSM|after128us [3] &
// \A_SPW_TOP|SPW|FSM|after128us [5]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [4]),
.datab(!\A_SPW_TOP|SPW|FSM|after128us [7]),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [3]),
.datad(!\A_SPW_TOP|SPW|FSM|after128us [5]),
.datae(!\A_SPW_TOP|SPW|FSM|after128us [6]),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|SPW|FSM|Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us[3]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us[3]~0_combout = ( \A_SPW_TOP|SPW|FSM|after128us [8] & ( \A_SPW_TOP|SPW|FSM|after128us [9] & ( \A_SPW_TOP|SPW|FSM|after128us [10] ) ) ) # ( !\A_SPW_TOP|SPW|FSM|after128us [8] & ( \A_SPW_TOP|SPW|FSM|after128us [9] & (
// \A_SPW_TOP|SPW|FSM|after128us [10] ) ) ) # ( \A_SPW_TOP|SPW|FSM|after128us [8] & ( !\A_SPW_TOP|SPW|FSM|after128us [9] & ( \A_SPW_TOP|SPW|FSM|after128us [10] ) ) ) # ( !\A_SPW_TOP|SPW|FSM|after128us [8] & ( !\A_SPW_TOP|SPW|FSM|after128us [9] & (
// (\A_SPW_TOP|SPW|FSM|Equal0~0_combout & (\A_SPW_TOP|SPW|FSM|Equal0~1_combout & \A_SPW_TOP|SPW|FSM|after128us [10])) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [10]),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|FSM|after128us [8]),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[3]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us[3]~0 .lut_mask = 64'h01010F0F0F0F0F0F;
defparam \A_SPW_TOP|SPW|FSM|after128us[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y10_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Add0~33 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Add0~33_sumout = SUM(( \A_SPW_TOP|SPW|FSM|after128us [11] ) + ( GND ) + ( \A_SPW_TOP|SPW|FSM|Add0~38 ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|SPW|FSM|Add0~38 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|SPW|FSM|Add0~33_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Add0~33 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Add0~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \A_SPW_TOP|SPW|FSM|Add0~33 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~9 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~9_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~33_sumout & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout & (!\A_SPW_TOP|SPW|FSM|always2~1_combout
// & \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datab(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~9 .lut_mask = 64'h0000000000000080;
defparam \A_SPW_TOP|SPW|FSM|after128us~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N20
dffeas \A_SPW_TOP|SPW|FSM|after128us[11] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|after128us~9_combout ),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [11]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after128us~7 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after128us~7_combout = ( \A_SPW_TOP|SPW|FSM|after128us~13_combout & ( \A_SPW_TOP|SPW|FSM|Add0~25_sumout & ( (!\A_SPW_TOP|SPW|FSM|after128us [11] & (!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout &
// (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & !\A_SPW_TOP|SPW|FSM|always2~1_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after128us [11]),
.datab(!\A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datad(!\A_SPW_TOP|SPW|FSM|always2~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|after128us~13_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|Add0~25_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after128us~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after128us~7 .lut_mask = 64'h0000000000000800;
defparam \A_SPW_TOP|SPW|FSM|after128us~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y10_N41
dffeas \A_SPW_TOP|SPW|FSM|after128us[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after128us~7_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after128us [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after128us[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after128us[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal0~1_combout = ( \A_SPW_TOP|SPW|FSM|after128us [0] & ( \A_SPW_TOP|SPW|FSM|after128us [1] ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|after128us [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|after128us [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal0~1 .lut_mask = 64'h0000000033333333;
defparam \A_SPW_TOP|SPW|FSM|Equal0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector0~0_combout = ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & ( \A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.started~q & ((!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) #
// ((\A_SPW_TOP|SPW|FSM|Equal0~1_combout & \A_SPW_TOP|SPW|FSM|Equal0~0_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & ( !\A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( (!\A_SPW_TOP|SPW|FSM|state_fsm.started~q &
// !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector0~0 .lut_mask = 64'hC0C00000C0C40000;
defparam \A_SPW_TOP|SPW|FSM|Selector0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector0~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector0~1_combout = ( \A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( (!\A_SPW_TOP|SPW|FSM|always0~1_combout ) # ((\A_SPW_TOP|SPW|FSM|Equal0~1_combout & \A_SPW_TOP|SPW|FSM|Equal0~0_combout ))
// ) ) ) # ( !\A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( !\A_SPW_TOP|SPW|FSM|always0~1_combout ) ) ) # ( \A_SPW_TOP|SPW|FSM|Equal0~2_combout & ( !\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & (
// (\A_SPW_TOP|SPW|FSM|Equal0~1_combout & (\A_SPW_TOP|SPW|FSM|state_fsm.started~q & \A_SPW_TOP|SPW|FSM|Equal0~0_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal0~1_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal0~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Equal0~2_combout ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector0~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector0~1 .lut_mask = 64'h00000101FF00FF05;
defparam \A_SPW_TOP|SPW|FSM|Selector0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector0~2 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector0~2_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q & ( !\A_SPW_TOP|SPW|FSM|Selector0~1_combout & ( (\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout & (\A_SPW_TOP|SPW|FSM|Selector5~1_combout & ((\A_SPW_TOP|SPW|FSM|Selector0~0_combout
// ) # (\A_SPW_TOP|SPW|FSM|always0~0_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.run~q & ( !\A_SPW_TOP|SPW|FSM|Selector0~1_combout & ( (\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout & ((\A_SPW_TOP|SPW|FSM|Selector0~0_combout ) #
// (\A_SPW_TOP|SPW|FSM|always0~0_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|always0~0_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|Selector5~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Selector0~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|Selector0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector0~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector0~2 .lut_mask = 64'h1133010300000000;
defparam \A_SPW_TOP|SPW|FSM|Selector0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N26
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.error_reset (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|Selector0~2_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.error_reset .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us[8]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout = ( !\A_SPW_TOP|SPW|FSM|after64us [10] & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & ( (!\A_SPW_TOP|SPW|FSM|after64us [11] & (!\db_system_spwulight_b|aux_pb~q & ((\u0|auto_start|data_out~q ) #
// (\u0|link_start|data_out~q )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [11]),
.datab(!\u0|link_start|data_out~q ),
.datac(!\u0|auto_start|data_out~q ),
.datad(!\db_system_spwulight_b|aux_pb~q ),
.datae(!\A_SPW_TOP|SPW|FSM|after64us [10]),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[8]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us[8]~0 .lut_mask = 64'h2A00000000000000;
defparam \A_SPW_TOP|SPW|FSM|after64us[8]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~7 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~7_combout = ( \A_SPW_TOP|SPW|FSM|Add1~25_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [0]) #
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~25_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~7 .lut_mask = 64'h000000000000AFAE;
defparam \A_SPW_TOP|SPW|FSM|after64us~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N2
dffeas \A_SPW_TOP|SPW|FSM|after64us[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~7_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~0_combout = ( \A_SPW_TOP|SPW|FSM|after64us [4] & ( \A_SPW_TOP|SPW|FSM|after64us [3] & ( (\A_SPW_TOP|SPW|FSM|after64us [1] & (\A_SPW_TOP|SPW|FSM|after64us [5] & (\A_SPW_TOP|SPW|FSM|after64us [2] & \A_SPW_TOP|SPW|FSM|after64us
// [6]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [1]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [5]),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [2]),
.datad(!\A_SPW_TOP|SPW|FSM|after64us [6]),
.datae(!\A_SPW_TOP|SPW|FSM|after64us [4]),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|SPW|FSM|Equal2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~12 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~12_combout = ( \A_SPW_TOP|SPW|FSM|Add1~45_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [0]) #
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~45_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~12 .lut_mask = 64'h000000000000AAFE;
defparam \A_SPW_TOP|SPW|FSM|after64us~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N5
dffeas \A_SPW_TOP|SPW|FSM|after64us[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|after64us~12_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Equal2~3 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Equal2~3_combout = ( !\A_SPW_TOP|SPW|FSM|after64us [7] & ( !\A_SPW_TOP|SPW|FSM|after64us [8] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|FSM|after64us [7]),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Equal2~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Equal2~3 .lut_mask = 64'hFFFF000000000000;
defparam \A_SPW_TOP|SPW|FSM|Equal2~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~8 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~8_combout = ( \A_SPW_TOP|SPW|FSM|Add1~29_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ) #
// (!\A_SPW_TOP|SPW|FSM|after64us [0])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datab(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datad(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~29_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~8 .lut_mask = 64'h000000000000F5F4;
defparam \A_SPW_TOP|SPW|FSM|after64us~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N53
dffeas \A_SPW_TOP|SPW|FSM|after64us[9] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|after64us~8_combout ),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y8_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|after64us~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|after64us~1_combout = ( \A_SPW_TOP|SPW|FSM|Add1~1_sumout & ( \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout & ( (!\A_SPW_TOP|SPW|FSM|after64us [9]) # ((\A_SPW_TOP|SPW|FSM|Equal2~3_combout & ((!\A_SPW_TOP|SPW|FSM|after64us [0]) #
// (!\A_SPW_TOP|SPW|FSM|Equal2~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [9]),
.datab(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datac(!\A_SPW_TOP|SPW|FSM|Equal2~3_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|Add1~1_sumout ),
.dataf(!\A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|after64us~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|after64us~1 .lut_mask = 64'h000000000000AFAE;
defparam \A_SPW_TOP|SPW|FSM|after64us~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y8_N8
dffeas \A_SPW_TOP|SPW|FSM|after64us[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|after64us~1_combout ),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|after64us [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|after64us[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|after64us[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|rx_resetn~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout = ((\A_SPW_TOP|SPW|FSM|after64us [0] & (\A_SPW_TOP|SPW|FSM|Equal2~0_combout & \A_SPW_TOP|SPW|FSM|Equal2~2_combout ))) # (\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q )
.dataa(!\A_SPW_TOP|SPW|FSM|after64us [0]),
.datab(!\A_SPW_TOP|SPW|FSM|Equal2~0_combout ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal2~2_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|rx_resetn~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|rx_resetn~0 .lut_mask = 64'h0F1F0F1F0F1F0F1F;
defparam \A_SPW_TOP|SPW|FSM|rx_resetn~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N35
dffeas \A_SPW_TOP|SPW|FSM|rx_resetn (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|rx_resetn .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|rx_resetn .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|WideOr7~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|WideOr7~0_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [3] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] &
// !\A_SPW_TOP|SPW|RX|counter_neg [2]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [3] & ((!\A_SPW_TOP|SPW|RX|counter_neg [1] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] $
// (!\A_SPW_TOP|SPW|RX|counter_neg [2]))) # (\A_SPW_TOP|SPW|RX|counter_neg [1] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] & !\A_SPW_TOP|SPW|RX|counter_neg [2])))) # (\A_SPW_TOP|SPW|RX|counter_neg [3] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] &
// (!\A_SPW_TOP|SPW|RX|counter_neg [5] & !\A_SPW_TOP|SPW|RX|counter_neg [2]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( !\A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [3] & (!\A_SPW_TOP|SPW|RX|counter_neg [1] &
// (!\A_SPW_TOP|SPW|RX|counter_neg [5] & !\A_SPW_TOP|SPW|RX|counter_neg [2]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datae(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|WideOr7~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|WideOr7~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|WideOr7~0 .lut_mask = 64'h8000000068808000;
defparam \A_SPW_TOP|SPW|RX|WideOr7~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N56
dffeas \A_SPW_TOP|SPW|RX|counter_neg[0] (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|WideOr7~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|counter_neg [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector5~1_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( (\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & !\A_SPW_TOP|SPW|RX|counter_neg [3]))) ) ) # (
// !\A_SPW_TOP|SPW|RX|counter_neg [5] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [0] & (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [4] & !\A_SPW_TOP|SPW|RX|counter_neg [3]))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector5~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector5~1 .lut_mask = 64'h8000800040004000;
defparam \A_SPW_TOP|SPW|RX|Selector5~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector5~0_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [5] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [3] & !\A_SPW_TOP|SPW|RX|counter_neg [4])) ) ) ) # (
// !\A_SPW_TOP|SPW|RX|counter_neg [5] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( (!\A_SPW_TOP|SPW|RX|counter_neg [3] & !\A_SPW_TOP|SPW|RX|counter_neg [4]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [5] & ( !\A_SPW_TOP|SPW|RX|counter_neg [0] & (
// (!\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [3] & !\A_SPW_TOP|SPW|RX|counter_neg [4])) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datae(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector5~0 .lut_mask = 64'hA0000000F000A000;
defparam \A_SPW_TOP|SPW|RX|Selector5~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector5~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector5~2_combout = ( \A_SPW_TOP|SPW|RX|is_control~q & ( \A_SPW_TOP|SPW|RX|always2~1_combout & ( (\A_SPW_TOP|SPW|RX|counter_neg [1]) # (\A_SPW_TOP|SPW|RX|Selector5~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|is_control~q & (
// \A_SPW_TOP|SPW|RX|always2~1_combout & ( ((\A_SPW_TOP|SPW|RX|Selector5~1_combout & \A_SPW_TOP|SPW|RX|Selector5~0_combout )) # (\A_SPW_TOP|SPW|RX|counter_neg [1]) ) ) ) # ( \A_SPW_TOP|SPW|RX|is_control~q & ( !\A_SPW_TOP|SPW|RX|always2~1_combout & (
// (!\A_SPW_TOP|SPW|RX|Selector5~0_combout & ((\A_SPW_TOP|SPW|RX|counter_neg [1]))) # (\A_SPW_TOP|SPW|RX|Selector5~0_combout & (\A_SPW_TOP|SPW|RX|Selector5~1_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|RX|is_control~q & ( !\A_SPW_TOP|SPW|RX|always2~1_combout &
// ( (!\A_SPW_TOP|SPW|RX|Selector5~0_combout & ((\A_SPW_TOP|SPW|RX|counter_neg [1]))) # (\A_SPW_TOP|SPW|RX|Selector5~0_combout & (\A_SPW_TOP|SPW|RX|Selector5~1_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|Selector5~1_combout ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|Selector5~0_combout ),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datae(!\A_SPW_TOP|SPW|RX|is_control~q ),
.dataf(!\A_SPW_TOP|SPW|RX|always2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector5~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector5~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector5~2 .lut_mask = 64'h05F505F505FF0FFF;
defparam \A_SPW_TOP|SPW|RX|Selector5~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N47
dffeas \A_SPW_TOP|SPW|RX|counter_neg[1] (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|Selector5~2_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|counter_neg [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|Selector4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|Selector4~0_combout = ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & ( \A_SPW_TOP|SPW|RX|counter_neg [2] ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( \A_SPW_TOP|SPW|RX|counter_neg [0] & (
// (!\A_SPW_TOP|SPW|RX|counter_neg [5] & ((!\A_SPW_TOP|SPW|RX|counter_neg [3] & ((\A_SPW_TOP|SPW|RX|counter_neg [1]))) # (\A_SPW_TOP|SPW|RX|counter_neg [3] & (\A_SPW_TOP|SPW|RX|counter_neg [2])))) # (\A_SPW_TOP|SPW|RX|counter_neg [5] &
// (\A_SPW_TOP|SPW|RX|counter_neg [2])) ) ) ) # ( \A_SPW_TOP|SPW|RX|counter_neg [4] & ( !\A_SPW_TOP|SPW|RX|counter_neg [0] & ( \A_SPW_TOP|SPW|RX|counter_neg [2] ) ) ) # ( !\A_SPW_TOP|SPW|RX|counter_neg [4] & ( !\A_SPW_TOP|SPW|RX|counter_neg [0] & (
// \A_SPW_TOP|SPW|RX|counter_neg [2] ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datae(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|Selector4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|Selector4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|Selector4~0 .lut_mask = 64'h5555555535555555;
defparam \A_SPW_TOP|SPW|RX|Selector4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N29
dffeas \A_SPW_TOP|SPW|RX|counter_neg[2] (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|Selector4~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|counter_neg [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|counter_neg[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|counter_neg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always2~1_combout = ( !\A_SPW_TOP|SPW|RX|counter_neg [3] & ( (\A_SPW_TOP|SPW|RX|counter_neg [2] & (!\A_SPW_TOP|SPW|RX|counter_neg [5] & (\A_SPW_TOP|SPW|RX|counter_neg [0] & !\A_SPW_TOP|SPW|RX|counter_neg [4]))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|counter_neg [2]),
.datab(!\A_SPW_TOP|SPW|RX|counter_neg [5]),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [0]),
.datad(!\A_SPW_TOP|SPW|RX|counter_neg [4]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|counter_neg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always2~1 .lut_mask = 64'h0400040000000000;
defparam \A_SPW_TOP|SPW|RX|always2~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always1~0_combout = LCELL(( !\A_SPW_TOP|SPW|RX|always3~0_combout & ( (\A_SPW_TOP|SPW|RX|always2~1_combout & !\A_SPW_TOP|SPW|RX|counter_neg [1]) ) ))
.dataa(!\A_SPW_TOP|SPW|RX|always2~1_combout ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|counter_neg [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always1~0 .lut_mask = 64'h5050505000000000;
defparam \A_SPW_TOP|SPW|RX|always1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|ready_data (
// Equation(s):
// \A_SPW_TOP|SPW|RX|ready_data~combout = LCELL(( !\A_SPW_TOP|SPW|RX|always3~0_combout & ( \A_SPW_TOP|SPW|RX|ready_data_p~0_combout & ( !\A_SPW_TOP|SPW|RX|always1~0_combout ) ) ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|always1~0_combout ),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|ready_data_p~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|ready_data .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|ready_data .lut_mask = 64'h00000000F0F00000;
defparam \A_SPW_TOP|SPW|RX|ready_data .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N14
dffeas \A_SPW_TOP|SPW|RX|bit_d_0 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\din_a~input_o ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_0~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_0 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_2~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_2~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_0~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|bit_d_0~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|bit_d_2~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_2~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_2~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_2~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N50
dffeas \A_SPW_TOP|SPW|RX|bit_d_2 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|bit_d_2~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_2~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_2 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_2 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N14
dffeas \A_SPW_TOP|SPW|RX|dta_timec[5] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_2~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode[7]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode[7]~0_combout = ( \A_SPW_TOP|SPW|RX|control [1] & ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( (\A_SPW_TOP|SPW|RX|control [0] & (\A_SPW_TOP|SPW|RX|control [2] & \A_SPW_TOP|SPW|RX|ready_data_p_r~q )) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [0]),
.datab(!\A_SPW_TOP|SPW|RX|control [2]),
.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|RX|control [1]),
.dataf(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[7]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode[7]~0 .lut_mask = 64'h0000010100000000;
defparam \A_SPW_TOP|SPW|RX|timecode[7]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y14_N53
dffeas \A_SPW_TOP|SPW|RX|timecode[5] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [5]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y14_N2
dffeas \A_SPW_TOP|SPW|RX|bit_d_4 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_2~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_4~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_4 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_4 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N29
dffeas \A_SPW_TOP|SPW|RX|dta_timec[3] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_4~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N47
dffeas \A_SPW_TOP|SPW|RX|timecode[3] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [3]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y14_N17
dffeas \A_SPW_TOP|SPW|RX|bit_d_1 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\din_a~input_o ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_1~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_1 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_1 .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y14_N5
dffeas \A_SPW_TOP|SPW|RX|bit_d_3 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_1~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_3~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_3 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_3 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N26
dffeas \A_SPW_TOP|SPW|RX|dta_timec[4] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_3~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode[4]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode[4]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [4] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|timecode[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|timecode[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y14_N46
dffeas \A_SPW_TOP|SPW|RX|timecode[4] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|timecode[4]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N17
dffeas \A_SPW_TOP|SPW|RX|dta_timec[6] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_1~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|timecode[6]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|timecode[6]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [6] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|timecode[6]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|timecode[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|timecode[6]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y14_N43
dffeas \A_SPW_TOP|SPW|RX|timecode[6] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|timecode[6]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N56
dffeas \A_SPW_TOP|SPW|RX|dta_timec[7] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_0~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N49
dffeas \A_SPW_TOP|SPW|RX|timecode[7] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [7]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N5
dffeas \A_SPW_TOP|SPW|RX|bit_d_5 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_3~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_5~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_5 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_5 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N35
dffeas \A_SPW_TOP|SPW|RX|dta_timec[2] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_5~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N44
dffeas \A_SPW_TOP|SPW|RX|timecode[2] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [2]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~0_combout = ( \A_SPW_TOP|SPW|RX|timecode [7] & ( \A_SPW_TOP|SPW|RX|timecode [2] & ( !\A_SPW_TOP|SPW|RX|timecode [5] $ (!\A_SPW_TOP|SPW|RX|timecode [3] $ (!\A_SPW_TOP|SPW|RX|timecode [4] $ (!\A_SPW_TOP|SPW|RX|timecode [6]))) ) )
// ) # ( !\A_SPW_TOP|SPW|RX|timecode [7] & ( \A_SPW_TOP|SPW|RX|timecode [2] & ( !\A_SPW_TOP|SPW|RX|timecode [5] $ (!\A_SPW_TOP|SPW|RX|timecode [3] $ (!\A_SPW_TOP|SPW|RX|timecode [4] $ (\A_SPW_TOP|SPW|RX|timecode [6]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|timecode
// [7] & ( !\A_SPW_TOP|SPW|RX|timecode [2] & ( !\A_SPW_TOP|SPW|RX|timecode [5] $ (!\A_SPW_TOP|SPW|RX|timecode [3] $ (!\A_SPW_TOP|SPW|RX|timecode [4] $ (\A_SPW_TOP|SPW|RX|timecode [6]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode [7] & (
// !\A_SPW_TOP|SPW|RX|timecode [2] & ( !\A_SPW_TOP|SPW|RX|timecode [5] $ (!\A_SPW_TOP|SPW|RX|timecode [3] $ (!\A_SPW_TOP|SPW|RX|timecode [4] $ (!\A_SPW_TOP|SPW|RX|timecode [6]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|timecode [5]),
.datab(!\A_SPW_TOP|SPW|RX|timecode [3]),
.datac(!\A_SPW_TOP|SPW|RX|timecode [4]),
.datad(!\A_SPW_TOP|SPW|RX|timecode [6]),
.datae(!\A_SPW_TOP|SPW|RX|timecode [7]),
.dataf(!\A_SPW_TOP|SPW|RX|timecode [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~0 .lut_mask = 64'h6996966996696996;
defparam \A_SPW_TOP|SPW|RX|always9~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y14_N11
dffeas \A_SPW_TOP|SPW|RX|last_was_control (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|last_is_control~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|last_is_data~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|last_was_control~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_was_control .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_was_control .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N5
dffeas \A_SPW_TOP|SPW|RX|last_was_timec (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|last_is_data~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|last_was_timec~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_was_timec .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_was_timec .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~1_combout = ( \A_SPW_TOP|SPW|RX|last_was_timec~q & ( (\A_SPW_TOP|SPW|RX|last_is_control~q & !\A_SPW_TOP|SPW|RX|last_was_control~q ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|last_was_control~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|last_was_timec~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~1 .lut_mask = 64'h0000000050505050;
defparam \A_SPW_TOP|SPW|RX|rx_error~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y14_N41
dffeas \A_SPW_TOP|SPW|RX|bit_d_7 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_5~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_7~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_7 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_7 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|dta_timec[0] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_7~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|timecode[0] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [0]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y14_N29
dffeas \A_SPW_TOP|SPW|RX|bit_d_6 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_4~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_6~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_6 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_6 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N32
dffeas \A_SPW_TOP|SPW|RX|dta_timec[1] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_6~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N23
dffeas \A_SPW_TOP|SPW|RX|timecode[1] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [1]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|timecode [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|timecode[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|timecode[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y14_N13
dffeas \A_SPW_TOP|SPW|RX|bit_c_3 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_c_1~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_c_3~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_c_3 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_c_3 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|control_r[3]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|control_r[3]~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_c_3~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|bit_c_3~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|control_r[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|control_r[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|control_r[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y18_N5
dffeas \A_SPW_TOP|SPW|RX|control_r[3] (
.clk(\A_SPW_TOP|SPW|RX|always1~0_combout ),
.d(\A_SPW_TOP|SPW|RX|control_r[3]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_r[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_r[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y18_N8
dffeas \A_SPW_TOP|SPW|RX|control_p_r[3] (
.clk(\A_SPW_TOP|SPW|RX|always2~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_r [3]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control_p_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control_p_r[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control_p_r[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y14_N23
dffeas \A_SPW_TOP|SPW|RX|control[3] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|control_p_r [3]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|control [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|control[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|control[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~2_combout = ( \A_SPW_TOP|SPW|RX|timecode [1] & ( \A_SPW_TOP|SPW|RX|control [3] & ( (\A_SPW_TOP|SPW|RX|rx_error~1_combout & (!\A_SPW_TOP|SPW|RX|always9~0_combout $ (!\A_SPW_TOP|SPW|RX|timecode [0] $ (!\A_SPW_TOP|SPW|RX|control
// [2])))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode [1] & ( \A_SPW_TOP|SPW|RX|control [3] & ( (\A_SPW_TOP|SPW|RX|rx_error~1_combout & (!\A_SPW_TOP|SPW|RX|always9~0_combout $ (!\A_SPW_TOP|SPW|RX|timecode [0] $ (\A_SPW_TOP|SPW|RX|control [2])))) ) ) ) # (
// \A_SPW_TOP|SPW|RX|timecode [1] & ( !\A_SPW_TOP|SPW|RX|control [3] & ( (\A_SPW_TOP|SPW|RX|rx_error~1_combout & (!\A_SPW_TOP|SPW|RX|always9~0_combout $ (!\A_SPW_TOP|SPW|RX|timecode [0] $ (\A_SPW_TOP|SPW|RX|control [2])))) ) ) ) # (
// !\A_SPW_TOP|SPW|RX|timecode [1] & ( !\A_SPW_TOP|SPW|RX|control [3] & ( (\A_SPW_TOP|SPW|RX|rx_error~1_combout & (!\A_SPW_TOP|SPW|RX|always9~0_combout $ (!\A_SPW_TOP|SPW|RX|timecode [0] $ (!\A_SPW_TOP|SPW|RX|control [2])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|always9~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_error~1_combout ),
.datac(!\A_SPW_TOP|SPW|RX|timecode [0]),
.datad(!\A_SPW_TOP|SPW|RX|control [2]),
.datae(!\A_SPW_TOP|SPW|RX|timecode [1]),
.dataf(!\A_SPW_TOP|SPW|RX|control [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~2 .lut_mask = 64'h2112122112212112;
defparam \A_SPW_TOP|SPW|RX|rx_error~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~6 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~6_combout = (\A_SPW_TOP|SPW|RX|last_is_data~q & !\A_SPW_TOP|SPW|RX|last_is_control~q )
.dataa(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~6 .lut_mask = 64'h4444444444444444;
defparam \A_SPW_TOP|SPW|RX|rx_error~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~4 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~4_combout = ( !\A_SPW_TOP|SPW|RX|last_was_control~q & ( !\A_SPW_TOP|SPW|RX|last_was_timec~q ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|last_was_timec~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|last_was_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~4 .lut_mask = 64'hFF00FF0000000000;
defparam \A_SPW_TOP|SPW|RX|rx_error~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [5] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N53
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[5] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(\A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data[9]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data[9]~0_combout = ( !\A_SPW_TOP|SPW|RX|ready_control_p_r~q & ( (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & ((!\A_SPW_TOP|SPW|RX|control [1]) # ((!\A_SPW_TOP|SPW|RX|control [0]) # (!\A_SPW_TOP|SPW|RX|control [2])))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(!\A_SPW_TOP|SPW|RX|control [1]),
.datac(!\A_SPW_TOP|SPW|RX|control [0]),
.datad(!\A_SPW_TOP|SPW|RX|control [2]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[9]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data[9]~0 .lut_mask = 64'h5554555400000000;
defparam \A_SPW_TOP|SPW|RX|data[9]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y14_N29
dffeas \A_SPW_TOP|SPW|RX|data[5] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y14_N41
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[3] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [3]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N17
dffeas \A_SPW_TOP|SPW|RX|data[3] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[4] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [4]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N53
dffeas \A_SPW_TOP|SPW|RX|data[4] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [6] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N44
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[6] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(\A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N50
dffeas \A_SPW_TOP|SPW|RX|data[6] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[2] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(\A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N38
dffeas \A_SPW_TOP|SPW|RX|data[2] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y14_N29
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[7] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [7]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N32
dffeas \A_SPW_TOP|SPW|RX|data[7] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~4 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~4_combout = ( \A_SPW_TOP|SPW|RX|data [2] & ( \A_SPW_TOP|SPW|RX|data [7] & ( !\A_SPW_TOP|SPW|RX|data [5] $ (!\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [4] $ (!\A_SPW_TOP|SPW|RX|data [6]))) ) ) ) # (
// !\A_SPW_TOP|SPW|RX|data [2] & ( \A_SPW_TOP|SPW|RX|data [7] & ( !\A_SPW_TOP|SPW|RX|data [5] $ (!\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [4] $ (\A_SPW_TOP|SPW|RX|data [6]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|data [2] & ( !\A_SPW_TOP|SPW|RX|data [7]
// & ( !\A_SPW_TOP|SPW|RX|data [5] $ (!\A_SPW_TOP|SPW|RX|data [3] $ (!\A_SPW_TOP|SPW|RX|data [4] $ (\A_SPW_TOP|SPW|RX|data [6]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [2] & ( !\A_SPW_TOP|SPW|RX|data [7] & ( !\A_SPW_TOP|SPW|RX|data [5] $ (!\A_SPW_TOP|SPW|RX|data
// [3] $ (!\A_SPW_TOP|SPW|RX|data [4] $ (!\A_SPW_TOP|SPW|RX|data [6]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|data [5]),
.datab(!\A_SPW_TOP|SPW|RX|data [3]),
.datac(!\A_SPW_TOP|SPW|RX|data [4]),
.datad(!\A_SPW_TOP|SPW|RX|data [6]),
.datae(!\A_SPW_TOP|SPW|RX|data [2]),
.dataf(!\A_SPW_TOP|SPW|RX|data [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~4 .lut_mask = 64'h6996966996696996;
defparam \A_SPW_TOP|SPW|RX|always9~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|last_was_data (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|last_is_data~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|last_is_data~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|last_was_data~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|last_was_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|last_was_data .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N14
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[0] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(\A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N11
dffeas \A_SPW_TOP|SPW|RX|data[0] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N23
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[1] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(\A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|data[1] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~5 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~5_combout = ( \A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [3] $ (!\A_SPW_TOP|SPW|RX|data [0] $ (!\A_SPW_TOP|SPW|RX|data [1])) ) ) # ( !\A_SPW_TOP|SPW|RX|control [2] & ( !\A_SPW_TOP|SPW|RX|control [3] $
// (!\A_SPW_TOP|SPW|RX|data [0] $ (\A_SPW_TOP|SPW|RX|data [1])) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [3]),
.datab(!\A_SPW_TOP|SPW|RX|data [0]),
.datac(!\A_SPW_TOP|SPW|RX|data [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|control [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~5 .lut_mask = 64'h6969696996969696;
defparam \A_SPW_TOP|SPW|RX|always9~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~7 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~7_combout = ( \A_SPW_TOP|SPW|RX|last_was_data~q & ( \A_SPW_TOP|SPW|RX|always9~5_combout & ( (\A_SPW_TOP|SPW|RX|rx_error~4_combout & (\A_SPW_TOP|SPW|RX|last_is_control~q & \A_SPW_TOP|SPW|RX|always9~4_combout )) ) ) ) # (
// !\A_SPW_TOP|SPW|RX|last_was_data~q & ( \A_SPW_TOP|SPW|RX|always9~5_combout & ( (\A_SPW_TOP|SPW|RX|rx_error~4_combout & (\A_SPW_TOP|SPW|RX|last_is_control~q & \A_SPW_TOP|SPW|RX|rx_error~q )) ) ) ) # ( \A_SPW_TOP|SPW|RX|last_was_data~q & (
// !\A_SPW_TOP|SPW|RX|always9~5_combout & ( (\A_SPW_TOP|SPW|RX|rx_error~4_combout & (\A_SPW_TOP|SPW|RX|last_is_control~q & !\A_SPW_TOP|SPW|RX|always9~4_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_was_data~q & ( !\A_SPW_TOP|SPW|RX|always9~5_combout & (
// (\A_SPW_TOP|SPW|RX|rx_error~4_combout & (\A_SPW_TOP|SPW|RX|last_is_control~q & \A_SPW_TOP|SPW|RX|rx_error~q )) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_error~4_combout ),
.datab(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datad(!\A_SPW_TOP|SPW|RX|always9~4_combout ),
.datae(!\A_SPW_TOP|SPW|RX|last_was_data~q ),
.dataf(!\A_SPW_TOP|SPW|RX|always9~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~7 .lut_mask = 64'h0101110001010011;
defparam \A_SPW_TOP|SPW|RX|rx_error~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~6 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~6_combout = ( \A_SPW_TOP|SPW|RX|control [3] & ( !\A_SPW_TOP|SPW|RX|control_l_r [0] $ (!\A_SPW_TOP|SPW|RX|control [2] $ (!\A_SPW_TOP|SPW|RX|control_l_r [1])) ) ) # ( !\A_SPW_TOP|SPW|RX|control [3] & (
// !\A_SPW_TOP|SPW|RX|control_l_r [0] $ (!\A_SPW_TOP|SPW|RX|control [2] $ (\A_SPW_TOP|SPW|RX|control_l_r [1])) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control_l_r [0]),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|control [2]),
.datad(!\A_SPW_TOP|SPW|RX|control_l_r [1]),
.datae(!\A_SPW_TOP|SPW|RX|control [3]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~6 .lut_mask = 64'h5AA5A55A5AA5A55A;
defparam \A_SPW_TOP|SPW|RX|always9~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~8 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~8_combout = ( \A_SPW_TOP|SPW|RX|last_is_data~q & ( (\A_SPW_TOP|SPW|RX|last_was_control~q & (!\A_SPW_TOP|SPW|RX|always9~6_combout & \A_SPW_TOP|SPW|RX|last_is_control~q )) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_data~q & (
// (!\A_SPW_TOP|SPW|RX|last_is_control~q & (\A_SPW_TOP|SPW|RX|rx_error~q )) # (\A_SPW_TOP|SPW|RX|last_is_control~q & (((\A_SPW_TOP|SPW|RX|last_was_control~q & !\A_SPW_TOP|SPW|RX|always9~6_combout )))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datab(!\A_SPW_TOP|SPW|RX|last_was_control~q ),
.datac(!\A_SPW_TOP|SPW|RX|always9~6_combout ),
.datad(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~8 .lut_mask = 64'h5530553000300030;
defparam \A_SPW_TOP|SPW|RX|rx_error~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N23
dffeas \A_SPW_TOP|SPW|RX|bit_d_8 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_6~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_8~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_8 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_8 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N58
dffeas \A_SPW_TOP|SPW|RX|dta_timec[8] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_8~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[8] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y14_N35
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[8] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|dta_timec [8]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data[8]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data[8]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [8] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|data[8]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[8]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|data[8]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y14_N44
dffeas \A_SPW_TOP|SPW|RX|data[8] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|data[8]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|bit_d_9~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout = ( \A_SPW_TOP|SPW|RX|bit_d_7~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|bit_d_7~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|bit_d_9~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y14_N2
dffeas \A_SPW_TOP|SPW|RX|bit_d_9 (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|bit_d_9~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|bit_d_9 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|bit_d_9 .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y14_N10
dffeas \A_SPW_TOP|SPW|RX|dta_timec[9] (
.clk(\A_SPW_TOP|SPW|RX|ready_data~combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|bit_d_9~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec [9] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y14_N2
dffeas \A_SPW_TOP|SPW|RX|dta_timec_p[9] (
.clk(\A_SPW_TOP|SPW|RX|ready_data_p~combout ),
.d(\A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|dta_timec_p [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|dta_timec_p[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data[9]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data[9]~feeder_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [9] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|data[9]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[9]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|data[9]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y14_N47
dffeas \A_SPW_TOP|SPW|RX|data[9] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|data[9]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~3_combout = ( \A_SPW_TOP|SPW|RX|data [9] & ( \A_SPW_TOP|SPW|RX|last_was_control~q & ( !\A_SPW_TOP|SPW|RX|control [0] $ (!\A_SPW_TOP|SPW|RX|data [8] $ (\A_SPW_TOP|SPW|RX|control [1])) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data [9] & (
// \A_SPW_TOP|SPW|RX|last_was_control~q & ( !\A_SPW_TOP|SPW|RX|control [0] $ (!\A_SPW_TOP|SPW|RX|data [8] $ (!\A_SPW_TOP|SPW|RX|control [1])) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [0]),
.datab(!\A_SPW_TOP|SPW|RX|data [8]),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|control [1]),
.datae(!\A_SPW_TOP|SPW|RX|data [9]),
.dataf(!\A_SPW_TOP|SPW|RX|last_was_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~3 .lut_mask = 64'h0000000099666699;
defparam \A_SPW_TOP|SPW|RX|rx_error~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder_combout = ( \A_SPW_TOP|SPW|RX|data [4] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|data [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|data_l_r[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y14_N35
dffeas \A_SPW_TOP|SPW|RX|data_l_r[4] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|data_l_r[4]~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N41
dffeas \A_SPW_TOP|SPW|RX|data_l_r[7] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|data [7]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N58
dffeas \A_SPW_TOP|SPW|RX|data_l_r[6] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|data [6]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N56
dffeas \A_SPW_TOP|SPW|RX|data_l_r[3] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|data [3]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N26
dffeas \A_SPW_TOP|SPW|RX|data_l_r[5] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|data [5]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~2_combout = ( \A_SPW_TOP|SPW|RX|data_l_r [3] & ( \A_SPW_TOP|SPW|RX|data_l_r [5] & ( !\A_SPW_TOP|SPW|RX|data_l_r [4] $ (!\A_SPW_TOP|SPW|RX|data_l_r [7] $ (!\A_SPW_TOP|SPW|RX|data_l_r [6] $ (!\A_SPW_TOP|SPW|RX|data [0]))) ) ) ) #
// ( !\A_SPW_TOP|SPW|RX|data_l_r [3] & ( \A_SPW_TOP|SPW|RX|data_l_r [5] & ( !\A_SPW_TOP|SPW|RX|data_l_r [4] $ (!\A_SPW_TOP|SPW|RX|data_l_r [7] $ (!\A_SPW_TOP|SPW|RX|data_l_r [6] $ (\A_SPW_TOP|SPW|RX|data [0]))) ) ) ) # ( \A_SPW_TOP|SPW|RX|data_l_r [3] & (
// !\A_SPW_TOP|SPW|RX|data_l_r [5] & ( !\A_SPW_TOP|SPW|RX|data_l_r [4] $ (!\A_SPW_TOP|SPW|RX|data_l_r [7] $ (!\A_SPW_TOP|SPW|RX|data_l_r [6] $ (\A_SPW_TOP|SPW|RX|data [0]))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data_l_r [3] & ( !\A_SPW_TOP|SPW|RX|data_l_r [5] & (
// !\A_SPW_TOP|SPW|RX|data_l_r [4] $ (!\A_SPW_TOP|SPW|RX|data_l_r [7] $ (!\A_SPW_TOP|SPW|RX|data_l_r [6] $ (!\A_SPW_TOP|SPW|RX|data [0]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|data_l_r [4]),
.datab(!\A_SPW_TOP|SPW|RX|data_l_r [7]),
.datac(!\A_SPW_TOP|SPW|RX|data_l_r [6]),
.datad(!\A_SPW_TOP|SPW|RX|data [0]),
.datae(!\A_SPW_TOP|SPW|RX|data_l_r [3]),
.dataf(!\A_SPW_TOP|SPW|RX|data_l_r [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~2 .lut_mask = 64'h6996966996696996;
defparam \A_SPW_TOP|SPW|RX|always9~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y14_N23
dffeas \A_SPW_TOP|SPW|RX|data_l_r[2] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|data [2]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|data_l_r[1] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|data [1]),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|RX|data[9]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|data_l_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|data_l_r[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|data_l_r[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~3_combout = ( \A_SPW_TOP|SPW|RX|data_l_r [1] & ( \A_SPW_TOP|SPW|RX|data [8] & ( !\A_SPW_TOP|SPW|RX|data [9] $ (!\A_SPW_TOP|SPW|RX|data_l_r [2]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data_l_r [1] & ( \A_SPW_TOP|SPW|RX|data [8] & (
// !\A_SPW_TOP|SPW|RX|data [9] $ (\A_SPW_TOP|SPW|RX|data_l_r [2]) ) ) ) # ( \A_SPW_TOP|SPW|RX|data_l_r [1] & ( !\A_SPW_TOP|SPW|RX|data [8] & ( !\A_SPW_TOP|SPW|RX|data [9] $ (\A_SPW_TOP|SPW|RX|data_l_r [2]) ) ) ) # ( !\A_SPW_TOP|SPW|RX|data_l_r [1] & (
// !\A_SPW_TOP|SPW|RX|data [8] & ( !\A_SPW_TOP|SPW|RX|data [9] $ (!\A_SPW_TOP|SPW|RX|data_l_r [2]) ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|RX|data [9]),
.datac(!\A_SPW_TOP|SPW|RX|data_l_r [2]),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|RX|data_l_r [1]),
.dataf(!\A_SPW_TOP|SPW|RX|data [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~3 .lut_mask = 64'h3C3CC3C3C3C33C3C;
defparam \A_SPW_TOP|SPW|RX|always9~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~5 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~5_combout = ( \A_SPW_TOP|SPW|RX|rx_error~4_combout & ( \A_SPW_TOP|SPW|RX|last_was_data~q & ( (!\A_SPW_TOP|SPW|RX|rx_error~3_combout & (!\A_SPW_TOP|SPW|RX|always9~2_combout $ (!\A_SPW_TOP|SPW|RX|always9~3_combout ))) ) ) ) #
// ( !\A_SPW_TOP|SPW|RX|rx_error~4_combout & ( \A_SPW_TOP|SPW|RX|last_was_data~q & ( !\A_SPW_TOP|SPW|RX|rx_error~3_combout ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_error~4_combout & ( !\A_SPW_TOP|SPW|RX|last_was_data~q & ( (!\A_SPW_TOP|SPW|RX|rx_error~3_combout
// & !\A_SPW_TOP|SPW|RX|rx_error~q ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_error~4_combout & ( !\A_SPW_TOP|SPW|RX|last_was_data~q & ( !\A_SPW_TOP|SPW|RX|rx_error~3_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_error~3_combout ),
.datab(!\A_SPW_TOP|SPW|RX|always9~2_combout ),
.datac(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datad(!\A_SPW_TOP|SPW|RX|always9~3_combout ),
.datae(!\A_SPW_TOP|SPW|RX|rx_error~4_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|last_was_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~5 .lut_mask = 64'hAAAAA0A0AAAA2288;
defparam \A_SPW_TOP|SPW|RX|rx_error~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y14_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always9~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always9~1_combout = ( \A_SPW_TOP|SPW|RX|data [8] & ( !\A_SPW_TOP|SPW|RX|data [9] ) ) # ( !\A_SPW_TOP|SPW|RX|data [8] & ( \A_SPW_TOP|SPW|RX|data [9] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|data [9]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|data [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always9~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always9~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always9~1 .lut_mask = 64'h00FF00FFFF00FF00;
defparam \A_SPW_TOP|SPW|RX|always9~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y14_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~0_combout = ( \A_SPW_TOP|SPW|RX|timecode [1] & ( \A_SPW_TOP|SPW|RX|timecode [0] & ( (\A_SPW_TOP|SPW|RX|last_was_timec~q & (!\A_SPW_TOP|SPW|RX|last_was_control~q & (!\A_SPW_TOP|SPW|RX|always9~0_combout $
// (\A_SPW_TOP|SPW|RX|always9~1_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode [1] & ( \A_SPW_TOP|SPW|RX|timecode [0] & ( (\A_SPW_TOP|SPW|RX|last_was_timec~q & (!\A_SPW_TOP|SPW|RX|last_was_control~q & (!\A_SPW_TOP|SPW|RX|always9~0_combout $
// (!\A_SPW_TOP|SPW|RX|always9~1_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|RX|timecode [1] & ( !\A_SPW_TOP|SPW|RX|timecode [0] & ( (\A_SPW_TOP|SPW|RX|last_was_timec~q & (!\A_SPW_TOP|SPW|RX|last_was_control~q & (!\A_SPW_TOP|SPW|RX|always9~0_combout $
// (!\A_SPW_TOP|SPW|RX|always9~1_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|timecode [1] & ( !\A_SPW_TOP|SPW|RX|timecode [0] & ( (\A_SPW_TOP|SPW|RX|last_was_timec~q & (!\A_SPW_TOP|SPW|RX|last_was_control~q & (!\A_SPW_TOP|SPW|RX|always9~0_combout $
// (\A_SPW_TOP|SPW|RX|always9~1_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|always9~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|last_was_timec~q ),
.datac(!\A_SPW_TOP|SPW|RX|always9~1_combout ),
.datad(!\A_SPW_TOP|SPW|RX|last_was_control~q ),
.datae(!\A_SPW_TOP|SPW|RX|timecode [1]),
.dataf(!\A_SPW_TOP|SPW|RX|timecode [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~0 .lut_mask = 64'h2100120012002100;
defparam \A_SPW_TOP|SPW|RX|rx_error~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_error~9 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_error~9_combout = ( \A_SPW_TOP|SPW|RX|rx_error~5_combout & ( \A_SPW_TOP|SPW|RX|rx_error~0_combout & ( (((\A_SPW_TOP|SPW|RX|rx_error~8_combout ) # (\A_SPW_TOP|SPW|RX|rx_error~7_combout )) # (\A_SPW_TOP|SPW|RX|rx_error~6_combout )) #
// (\A_SPW_TOP|SPW|RX|rx_error~2_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_error~5_combout & ( \A_SPW_TOP|SPW|RX|rx_error~0_combout & ( (((\A_SPW_TOP|SPW|RX|rx_error~8_combout ) # (\A_SPW_TOP|SPW|RX|rx_error~7_combout )) #
// (\A_SPW_TOP|SPW|RX|rx_error~6_combout )) # (\A_SPW_TOP|SPW|RX|rx_error~2_combout ) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_error~5_combout & ( !\A_SPW_TOP|SPW|RX|rx_error~0_combout & ( ((\A_SPW_TOP|SPW|RX|rx_error~8_combout ) #
// (\A_SPW_TOP|SPW|RX|rx_error~7_combout )) # (\A_SPW_TOP|SPW|RX|rx_error~2_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_error~5_combout & ( !\A_SPW_TOP|SPW|RX|rx_error~0_combout & ( (((\A_SPW_TOP|SPW|RX|rx_error~8_combout ) #
// (\A_SPW_TOP|SPW|RX|rx_error~7_combout )) # (\A_SPW_TOP|SPW|RX|rx_error~6_combout )) # (\A_SPW_TOP|SPW|RX|rx_error~2_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_error~2_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_error~6_combout ),
.datac(!\A_SPW_TOP|SPW|RX|rx_error~7_combout ),
.datad(!\A_SPW_TOP|SPW|RX|rx_error~8_combout ),
.datae(!\A_SPW_TOP|SPW|RX|rx_error~5_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_error~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_error~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_error~9 .lut_mask = 64'h7FFF5FFF7FFF7FFF;
defparam \A_SPW_TOP|SPW|RX|rx_error~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N26
dffeas \A_SPW_TOP|SPW|RX|rx_error (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_error~9_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_error~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_error .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_error .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|overflow_credit_error~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|overflow_credit_error~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|overflow_credit_error~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|overflow_credit_error~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|overflow_credit_error~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|rx_data|overflow_credit_error~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter[0]~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter[0]~8_combout = ( !\A_SPW_TOP|rx_data|credit_counter [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter[0]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[0]~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter[0]~8 .lut_mask = 64'hFFFFFFFF00000000;
defparam \A_SPW_TOP|rx_data|credit_counter[0]~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~1_sumout = SUM(( \A_SPW_TOP|rx_data|counter [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|rx_data|Add0~2 = CARRY(( \A_SPW_TOP|rx_data|counter [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|counter [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|rx_data|Add0~1_sumout ),
.cout(\A_SPW_TOP|rx_data|Add0~2 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~1 .lut_mask = 64'h0000000000000F0F;
defparam \A_SPW_TOP|rx_data|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout = (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [0])
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N40
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .lut_mask = 64'h0000F0F000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[82] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N47
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [82] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [82] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [82]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]
// & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [86] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[86] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N35
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (
// (\u0|mm_interconnect_0|cmd_mux_004|src_data [87] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|cmd_mux_004|src_data [88])) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_004|src_data [87] & ((!\u0|mm_interconnect_0|cmd_mux_004|src_data [88])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h1D0C1D0C11001100;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_004|src_data [86]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[81] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [81] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [81] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h0B0B0B0B08080808;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N35
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout & (
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout &
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000CFC0CFC0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N43
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [87] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [87] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_004|src_data [88])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hE222E222C000C000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_004|src_data [86]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N43
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[80] .lut_mask = 64'h5F555F550F000F00;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [80]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|cmd_mux_004|src_data [86] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// ((!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|src_data [86]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h3232323202020202;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N58
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[79] .lut_mask = 64'h50FF50FF50505050;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N44
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] )
// + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) ) #
// ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) )
// # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) )
// ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F000F000FFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_004|src_data [79] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [79] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [79]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h5055505550005000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout
// ) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] &
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0202AAAA0257AAFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N37
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) +
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_004|src_data [80]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [80]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N19
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout
// & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h00035053F0F3F0F3;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N13
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]
// ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N31
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]
// ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0A5F0A5F2A7F2A7F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y32_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y29_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N36
cyclonev_lcell_comb \u0|data_read_en_rx|always0~0 (
// Equation(s):
// \u0|data_read_en_rx|always0~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout & !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_read_en_rx|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_read_en_rx|always0~0 .extended_lut = "off";
defparam \u0|data_read_en_rx|always0~0 .lut_mask = 64'h0C00000000000000;
defparam \u0|data_read_en_rx|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y28_N8
dffeas \u0|data_read_en_rx|data_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|data_read_en_rx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_read_en_rx|data_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_read_en_rx|data_out .is_wysiwyg = "true";
defparam \u0|data_read_en_rx|data_out .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_take~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_take~0_combout = ( !\A_SPW_TOP|SPW|RX|last_is_timec~q & ( (\A_SPW_TOP|SPW|RX|control [2] & (\A_SPW_TOP|SPW|RX|last_is_control~q & (!\A_SPW_TOP|SPW|RX|control [0] $ (!\A_SPW_TOP|SPW|RX|control [1])))) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [0]),
.datab(!\A_SPW_TOP|SPW|RX|control [2]),
.datac(!\A_SPW_TOP|SPW|RX|control [1]),
.datad(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_take~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_take~0 .lut_mask = 64'h0012001200000000;
defparam \A_SPW_TOP|SPW|RX|rx_data_take~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_take~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_take~1_combout = ( \A_SPW_TOP|SPW|RX|last_is_control~q & ( \A_SPW_TOP|SPW|RX|last_is_data~q & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q & (((!\A_SPW_TOP|SPW|RX|last_is_timec~q )) # (\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ))) #
// (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & (((\A_SPW_TOP|SPW|RX|rx_data_take~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_control~q & ( \A_SPW_TOP|SPW|RX|last_is_data~q & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q & (((!\A_SPW_TOP|SPW|RX|last_is_timec~q )) #
// (\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ))) # (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & (((\A_SPW_TOP|SPW|RX|rx_data_take~q )))) ) ) ) # ( \A_SPW_TOP|SPW|RX|last_is_control~q & ( !\A_SPW_TOP|SPW|RX|last_is_data~q & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q
// & (\A_SPW_TOP|SPW|RX|rx_data_take~0_combout )) # (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & ((\A_SPW_TOP|SPW|RX|rx_data_take~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|last_is_control~q & ( !\A_SPW_TOP|SPW|RX|last_is_data~q & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q
// & (((\A_SPW_TOP|SPW|RX|rx_data_take~q & !\A_SPW_TOP|SPW|RX|last_is_timec~q )) # (\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ))) # (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & (((\A_SPW_TOP|SPW|RX|rx_data_take~q )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datac(!\A_SPW_TOP|SPW|RX|rx_data_take~q ),
.datad(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.datae(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.dataf(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_take~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_take~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_take~1 .lut_mask = 64'h4F474747CF47CF47;
defparam \A_SPW_TOP|SPW|RX|rx_data_take~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N35
dffeas \A_SPW_TOP|SPW|RX|rx_data_take (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_take~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_take~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_take .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_take .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y14_N5
dffeas \A_SPW_TOP|SPW|RX|rx_data_take_0 (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_take~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_take_0~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_take_0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_take_0 .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y14_N53
dffeas \A_SPW_TOP|SPW|RX|rx_buffer_write (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_take_0~q ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_buffer_write .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~5_sumout = SUM(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|block_write~q )) # (\A_SPW_TOP|rx_data|f_full~q ) ) + ( \A_SPW_TOP|rx_data|counter [1] ) + ( \A_SPW_TOP|rx_data|Add0~2 ))
// \A_SPW_TOP|rx_data|Add0~6 = CARRY(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|block_write~q )) # (\A_SPW_TOP|rx_data|f_full~q ) ) + ( \A_SPW_TOP|rx_data|counter [1] ) + ( \A_SPW_TOP|rx_data|Add0~2 ))
.dataa(!\A_SPW_TOP|rx_data|f_full~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datad(!\A_SPW_TOP|rx_data|block_write~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|counter [1]),
.datag(gnd),
.cin(\A_SPW_TOP|rx_data|Add0~2 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|rx_data|Add0~5_sumout ),
.cout(\A_SPW_TOP|rx_data|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~5 .lut_mask = 64'h0000FF000000F5FF;
defparam \A_SPW_TOP|rx_data|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N20
dffeas \A_SPW_TOP|rx_data|counter[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add0~5_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~9_sumout = SUM(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [2] ) + ( \A_SPW_TOP|rx_data|Add0~6 ))
// \A_SPW_TOP|rx_data|Add0~10 = CARRY(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [2] ) + ( \A_SPW_TOP|rx_data|Add0~6 ))
.dataa(!\A_SPW_TOP|rx_data|block_write~q ),
.datab(!\A_SPW_TOP|rx_data|f_full~q ),
.datac(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|counter [2]),
.datag(gnd),
.cin(\A_SPW_TOP|rx_data|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|rx_data|Add0~9_sumout ),
.cout(\A_SPW_TOP|rx_data|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~9 .lut_mask = 64'h0000FF000000F7F7;
defparam \A_SPW_TOP|rx_data|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter[2]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|counter[2]~feeder_combout = ( \A_SPW_TOP|rx_data|Add0~9_sumout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|counter[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[2]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|counter[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N35
dffeas \A_SPW_TOP|rx_data|counter[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|counter[2]~feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~13_sumout = SUM(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [3] ) + ( \A_SPW_TOP|rx_data|Add0~10 ))
// \A_SPW_TOP|rx_data|Add0~14 = CARRY(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [3] ) + ( \A_SPW_TOP|rx_data|Add0~10 ))
.dataa(!\A_SPW_TOP|rx_data|block_write~q ),
.datab(!\A_SPW_TOP|rx_data|f_full~q ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|counter [3]),
.datag(gnd),
.cin(\A_SPW_TOP|rx_data|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|rx_data|Add0~13_sumout ),
.cout(\A_SPW_TOP|rx_data|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~13 .lut_mask = 64'h0000FF000000FF77;
defparam \A_SPW_TOP|rx_data|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter[3]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|counter[3]~feeder_combout = ( \A_SPW_TOP|rx_data|Add0~13_sumout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|Add0~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|counter[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[3]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|counter[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N32
dffeas \A_SPW_TOP|rx_data|counter[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|counter[3]~feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~17_sumout = SUM(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [4] ) + ( \A_SPW_TOP|rx_data|Add0~14 ))
// \A_SPW_TOP|rx_data|Add0~18 = CARRY(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [4] ) + ( \A_SPW_TOP|rx_data|Add0~14 ))
.dataa(!\A_SPW_TOP|rx_data|block_write~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|f_full~q ),
.datad(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|counter [4]),
.datag(gnd),
.cin(\A_SPW_TOP|rx_data|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|rx_data|Add0~17_sumout ),
.cout(\A_SPW_TOP|rx_data|Add0~18 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~17 .lut_mask = 64'h0000FF000000FF5F;
defparam \A_SPW_TOP|rx_data|Add0~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter[4]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|counter[4]~feeder_combout = ( \A_SPW_TOP|rx_data|Add0~17_sumout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|Add0~17_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|counter[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[4]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|counter[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N41
dffeas \A_SPW_TOP|rx_data|counter[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|counter[4]~feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add0~21 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add0~21_sumout = SUM(( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q )) # (\A_SPW_TOP|rx_data|block_write~q ) ) + ( \A_SPW_TOP|rx_data|counter [5] ) + ( \A_SPW_TOP|rx_data|Add0~18 ))
.dataa(!\A_SPW_TOP|rx_data|block_write~q ),
.datab(!\A_SPW_TOP|rx_data|f_full~q ),
.datac(!\A_SPW_TOP|rx_data|counter [5]),
.datad(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|rx_data|Add0~18 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|rx_data|Add0~21_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add0~21 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add0~21 .lut_mask = 64'h0000F0F00000FF77;
defparam \A_SPW_TOP|rx_data|Add0~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter[5]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|counter[5]~feeder_combout = ( \A_SPW_TOP|rx_data|Add0~21_sumout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|Add0~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|counter[5]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[5]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|counter[5]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N23
dffeas \A_SPW_TOP|rx_data|counter[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|counter[5]~feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Equal1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Equal1~0_combout = ( \A_SPW_TOP|rx_data|counter [5] & ( \A_SPW_TOP|rx_data|counter [1] ) ) # ( !\A_SPW_TOP|rx_data|counter [5] & ( \A_SPW_TOP|rx_data|counter [1] ) ) # ( \A_SPW_TOP|rx_data|counter [5] & ( !\A_SPW_TOP|rx_data|counter
// [1] ) ) # ( !\A_SPW_TOP|rx_data|counter [5] & ( !\A_SPW_TOP|rx_data|counter [1] & ( (((\A_SPW_TOP|rx_data|counter [4]) # (\A_SPW_TOP|rx_data|counter [2])) # (\A_SPW_TOP|rx_data|counter [3])) # (\A_SPW_TOP|rx_data|counter [0]) ) ) )
.dataa(!\A_SPW_TOP|rx_data|counter [0]),
.datab(!\A_SPW_TOP|rx_data|counter [3]),
.datac(!\A_SPW_TOP|rx_data|counter [2]),
.datad(!\A_SPW_TOP|rx_data|counter [4]),
.datae(!\A_SPW_TOP|rx_data|counter [5]),
.dataf(!\A_SPW_TOP|rx_data|counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Equal1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Equal1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Equal1~0 .lut_mask = 64'h7FFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|rx_data|Equal1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N44
dffeas \A_SPW_TOP|rx_data|f_empty (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|Equal1~0_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|f_empty~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|f_empty .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|f_empty .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|block_read~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|block_read~0_combout = ( \A_SPW_TOP|rx_data|block_read~q & ( \u0|data_read_en_rx|data_out~q ) ) # ( !\A_SPW_TOP|rx_data|block_read~q & ( (\u0|data_read_en_rx|data_out~q & \A_SPW_TOP|rx_data|f_empty~q ) ) )
.dataa(gnd),
.datab(!\u0|data_read_en_rx|data_out~q ),
.datac(!\A_SPW_TOP|rx_data|f_empty~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|block_read~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|block_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|block_read~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|block_read~0 .lut_mask = 64'h0303030333333333;
defparam \A_SPW_TOP|rx_data|block_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N38
dffeas \A_SPW_TOP|rx_data|block_read (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|block_read~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|block_read~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|block_read .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|block_read .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|counter~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|counter~0_combout = ( \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( \A_SPW_TOP|rx_data|f_empty~q & ( (!\A_SPW_TOP|rx_data|f_full~q & (!\A_SPW_TOP|rx_data|block_write~q $ (((!\A_SPW_TOP|rx_data|block_read~q &
// \u0|data_read_en_rx|data_out~q ))))) # (\A_SPW_TOP|rx_data|f_full~q & (((!\A_SPW_TOP|rx_data|block_read~q & \u0|data_read_en_rx|data_out~q )))) ) ) ) # ( !\A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( \A_SPW_TOP|rx_data|f_empty~q & (
// (!\A_SPW_TOP|rx_data|block_read~q & \u0|data_read_en_rx|data_out~q ) ) ) ) # ( \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( !\A_SPW_TOP|rx_data|f_empty~q & ( (!\A_SPW_TOP|rx_data|f_full~q & !\A_SPW_TOP|rx_data|block_write~q ) ) ) )
.dataa(!\A_SPW_TOP|rx_data|f_full~q ),
.datab(!\A_SPW_TOP|rx_data|block_write~q ),
.datac(!\A_SPW_TOP|rx_data|block_read~q ),
.datad(!\u0|data_read_en_rx|data_out~q ),
.datae(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.dataf(!\A_SPW_TOP|rx_data|f_empty~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|counter~0 .lut_mask = 64'h0000888800F08878;
defparam \A_SPW_TOP|rx_data|counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N38
dffeas \A_SPW_TOP|rx_data|counter[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add0~1_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|counter[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Equal0~0_combout = ( \A_SPW_TOP|rx_data|counter [5] & ( \A_SPW_TOP|rx_data|counter [1] & ( (\A_SPW_TOP|rx_data|counter [0] & (\A_SPW_TOP|rx_data|counter [3] & (\A_SPW_TOP|rx_data|counter [2] & \A_SPW_TOP|rx_data|counter [4]))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|counter [0]),
.datab(!\A_SPW_TOP|rx_data|counter [3]),
.datac(!\A_SPW_TOP|rx_data|counter [2]),
.datad(!\A_SPW_TOP|rx_data|counter [4]),
.datae(!\A_SPW_TOP|rx_data|counter [5]),
.dataf(!\A_SPW_TOP|rx_data|counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Equal0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Equal0~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|rx_data|Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N56
dffeas \A_SPW_TOP|rx_data|f_full (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|Equal0~0_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|f_full~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|f_full .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|f_full .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|block_write~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|block_write~0_combout = ( \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( (!\A_SPW_TOP|rx_data|f_full~q ) # (\A_SPW_TOP|rx_data|block_write~q ) ) )
.dataa(!\A_SPW_TOP|rx_data|block_write~q ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|rx_data|f_full~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|block_write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|block_write~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|block_write~0 .lut_mask = 64'h00000000FF55FF55;
defparam \A_SPW_TOP|rx_data|block_write~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y11_N29
dffeas \A_SPW_TOP|rx_data|block_write (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|block_write~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|block_write~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|block_write .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|block_write .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|mem~12_combout = ( \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( (!\A_SPW_TOP|rx_data|block_write~q & !\A_SPW_TOP|rx_data|f_full~q ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|rx_data|block_write~q ),
.datac(!\A_SPW_TOP|rx_data|f_full~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem~12 .lut_mask = 64'h00000000C0C0C0C0;
defparam \A_SPW_TOP|rx_data|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N17
dffeas \A_SPW_TOP|rx_data|credit_counter[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|credit_counter[0]~8_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|credit_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~2_combout = ( \A_SPW_TOP|rx_data|credit_counter [1] & ( !\A_SPW_TOP|rx_data|credit_counter [0] ) ) # ( !\A_SPW_TOP|rx_data|credit_counter [1] & ( \A_SPW_TOP|rx_data|credit_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|credit_counter [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~2 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|rx_data|Add1~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N47
dffeas \A_SPW_TOP|rx_data|credit_counter[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add1~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|credit_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~1_combout = !\A_SPW_TOP|rx_data|credit_counter [2] $ (((!\A_SPW_TOP|rx_data|credit_counter [0]) # (!\A_SPW_TOP|rx_data|credit_counter [1])))
.dataa(gnd),
.datab(!\A_SPW_TOP|rx_data|credit_counter [0]),
.datac(!\A_SPW_TOP|rx_data|credit_counter [2]),
.datad(!\A_SPW_TOP|rx_data|credit_counter [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~1 .lut_mask = 64'h0F3C0F3C0F3C0F3C;
defparam \A_SPW_TOP|rx_data|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N43
dffeas \A_SPW_TOP|rx_data|credit_counter[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add1~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|credit_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add1~0_combout = (\A_SPW_TOP|rx_data|credit_counter [0] & (\A_SPW_TOP|rx_data|credit_counter [1] & \A_SPW_TOP|rx_data|credit_counter [2]))
.dataa(gnd),
.datab(!\A_SPW_TOP|rx_data|credit_counter [0]),
.datac(!\A_SPW_TOP|rx_data|credit_counter [1]),
.datad(!\A_SPW_TOP|rx_data|credit_counter [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add1~0 .lut_mask = 64'h0003000300030003;
defparam \A_SPW_TOP|rx_data|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter~3_combout = ( \A_SPW_TOP|rx_data|credit_counter [3] & ( (!\A_SPW_TOP|rx_data|block_write~q & (\A_SPW_TOP|SPW|RX|rx_buffer_write~q & (!\A_SPW_TOP|rx_data|f_full~q & !\A_SPW_TOP|rx_data|Add1~0_combout ))) ) ) # (
// !\A_SPW_TOP|rx_data|credit_counter [3] & ( ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # ((\A_SPW_TOP|rx_data|Add1~0_combout ) # (\A_SPW_TOP|rx_data|f_full~q ))) # (\A_SPW_TOP|rx_data|block_write~q ) ) )
.dataa(!\A_SPW_TOP|rx_data|block_write~q ),
.datab(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datac(!\A_SPW_TOP|rx_data|f_full~q ),
.datad(!\A_SPW_TOP|rx_data|Add1~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter~3 .lut_mask = 64'hDFFFDFFF20002000;
defparam \A_SPW_TOP|rx_data|credit_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter[3]~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter[3]~4_combout = (\u0|data_read_en_rx|data_out~q & \A_SPW_TOP|rx_data|f_empty~q )
.dataa(gnd),
.datab(!\u0|data_read_en_rx|data_out~q ),
.datac(!\A_SPW_TOP|rx_data|f_empty~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[3]~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter[3]~4 .lut_mask = 64'h0303030303030303;
defparam \A_SPW_TOP|rx_data|credit_counter[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr~1_combout = !\A_SPW_TOP|rx_data|rd_ptr [0] $ (((!\A_SPW_TOP|rx_data|f_empty~q ) # (!\u0|data_read_en_rx|data_out~q )))
.dataa(!\A_SPW_TOP|rx_data|f_empty~q ),
.datab(!\u0|data_read_en_rx|data_out~q ),
.datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|rd_ptr~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr~1 .lut_mask = 64'h1E1E1E1E1E1E1E1E;
defparam \A_SPW_TOP|rx_data|rd_ptr~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N8
dffeas \A_SPW_TOP|rx_data|rd_ptr[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|rd_ptr [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr~2_combout = !\A_SPW_TOP|rx_data|rd_ptr [1] $ (((!\A_SPW_TOP|rx_data|f_empty~q ) # ((!\u0|data_read_en_rx|data_out~q ) # (!\A_SPW_TOP|rx_data|rd_ptr [0]))))
.dataa(!\A_SPW_TOP|rx_data|f_empty~q ),
.datab(!\u0|data_read_en_rx|data_out~q ),
.datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
.datad(!\A_SPW_TOP|rx_data|rd_ptr [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|rd_ptr~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr~2 .lut_mask = 64'h0F1E0F1E0F1E0F1E;
defparam \A_SPW_TOP|rx_data|rd_ptr~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N23
dffeas \A_SPW_TOP|rx_data|rd_ptr[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|rd_ptr [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr~3_combout = ( \A_SPW_TOP|rx_data|f_empty~q & ( !\A_SPW_TOP|rx_data|rd_ptr [2] $ (((!\A_SPW_TOP|rx_data|rd_ptr [0]) # ((!\u0|data_read_en_rx|data_out~q ) # (!\A_SPW_TOP|rx_data|rd_ptr [1])))) ) ) # (
// !\A_SPW_TOP|rx_data|f_empty~q & ( \A_SPW_TOP|rx_data|rd_ptr [2] ) )
.dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
.datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
.datac(!\u0|data_read_en_rx|data_out~q ),
.datad(!\A_SPW_TOP|rx_data|rd_ptr [1]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|f_empty~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|rd_ptr~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr~3 .lut_mask = 64'h5555555555565556;
defparam \A_SPW_TOP|rx_data|rd_ptr~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N35
dffeas \A_SPW_TOP|rx_data|rd_ptr[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|rd_ptr [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr~4_combout = ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (!\A_SPW_TOP|rx_data|rd_ptr [1]) # ((!\A_SPW_TOP|rx_data|rd_ptr [0]) # ((!\A_SPW_TOP|rx_data|f_empty~q ) # (!\u0|data_read_en_rx|data_out~q ))) )
// ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( \A_SPW_TOP|rx_data|rd_ptr [2] & ( (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|f_empty~q & \u0|data_read_en_rx|data_out~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [3] & (
// !\A_SPW_TOP|rx_data|rd_ptr [2] ) )
.dataa(!\A_SPW_TOP|rx_data|rd_ptr [1]),
.datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
.datac(!\A_SPW_TOP|rx_data|f_empty~q ),
.datad(!\u0|data_read_en_rx|data_out~q ),
.datae(!\A_SPW_TOP|rx_data|rd_ptr [3]),
.dataf(!\A_SPW_TOP|rx_data|rd_ptr [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|rd_ptr~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr~4 .lut_mask = 64'h0000FFFF0001FFFE;
defparam \A_SPW_TOP|rx_data|rd_ptr~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N20
dffeas \A_SPW_TOP|rx_data|rd_ptr[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~4_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|rd_ptr [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|always2~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|always2~1_combout = (\A_SPW_TOP|rx_data|rd_ptr [2] & (\A_SPW_TOP|rx_data|rd_ptr [0] & (\A_SPW_TOP|rx_data|rd_ptr [1] & \A_SPW_TOP|rx_data|rd_ptr [3])))
.dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
.datab(!\A_SPW_TOP|rx_data|rd_ptr [0]),
.datac(!\A_SPW_TOP|rx_data|rd_ptr [1]),
.datad(!\A_SPW_TOP|rx_data|rd_ptr [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|always2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|always2~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|always2~1 .lut_mask = 64'h0001000100010001;
defparam \A_SPW_TOP|rx_data|always2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr~5_combout = !\A_SPW_TOP|rx_data|rd_ptr [4] $ (((!\A_SPW_TOP|rx_data|always2~1_combout ) # ((!\u0|data_read_en_rx|data_out~q ) # (!\A_SPW_TOP|rx_data|f_empty~q ))))
.dataa(!\A_SPW_TOP|rx_data|always2~1_combout ),
.datab(!\u0|data_read_en_rx|data_out~q ),
.datac(!\A_SPW_TOP|rx_data|f_empty~q ),
.datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|rd_ptr~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr~5 .lut_mask = 64'h01FE01FE01FE01FE;
defparam \A_SPW_TOP|rx_data|rd_ptr~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N50
dffeas \A_SPW_TOP|rx_data|rd_ptr[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~5_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|rd_ptr [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|rd_ptr~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|rd_ptr~0_combout = ( \A_SPW_TOP|rx_data|rd_ptr [5] & ( (!\A_SPW_TOP|rx_data|always2~1_combout ) # ((!\u0|data_read_en_rx|data_out~q ) # ((!\A_SPW_TOP|rx_data|f_empty~q ) # (!\A_SPW_TOP|rx_data|rd_ptr [4]))) ) ) # (
// !\A_SPW_TOP|rx_data|rd_ptr [5] & ( (\A_SPW_TOP|rx_data|always2~1_combout & (\u0|data_read_en_rx|data_out~q & (\A_SPW_TOP|rx_data|f_empty~q & \A_SPW_TOP|rx_data|rd_ptr [4]))) ) )
.dataa(!\A_SPW_TOP|rx_data|always2~1_combout ),
.datab(!\u0|data_read_en_rx|data_out~q ),
.datac(!\A_SPW_TOP|rx_data|f_empty~q ),
.datad(!\A_SPW_TOP|rx_data|rd_ptr [4]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|rd_ptr [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|rd_ptr~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|rd_ptr~0 .lut_mask = 64'h00010001FFFEFFFE;
defparam \A_SPW_TOP|rx_data|rd_ptr~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N17
dffeas \A_SPW_TOP|rx_data|rd_ptr[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|rd_ptr [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|rd_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|rd_ptr[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|always2~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|always2~0_combout = ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1] & (!\A_SPW_TOP|rx_data|rd_ptr [0]))) # (\A_SPW_TOP|rx_data|rd_ptr [2] &
// (\A_SPW_TOP|rx_data|rd_ptr [1] & (\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|rd_ptr [5]))) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] & ( \A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1] &
// !\A_SPW_TOP|rx_data|rd_ptr [0])) ) ) ) # ( \A_SPW_TOP|rx_data|rd_ptr [4] & ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1] & !\A_SPW_TOP|rx_data|rd_ptr [0])) ) ) ) # ( !\A_SPW_TOP|rx_data|rd_ptr [4] &
// ( !\A_SPW_TOP|rx_data|rd_ptr [3] & ( (!\A_SPW_TOP|rx_data|rd_ptr [2] & (!\A_SPW_TOP|rx_data|rd_ptr [1] & (!\A_SPW_TOP|rx_data|rd_ptr [0] & \A_SPW_TOP|rx_data|rd_ptr [5]))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|rd_ptr [2]),
.datab(!\A_SPW_TOP|rx_data|rd_ptr [1]),
.datac(!\A_SPW_TOP|rx_data|rd_ptr [0]),
.datad(!\A_SPW_TOP|rx_data|rd_ptr [5]),
.datae(!\A_SPW_TOP|rx_data|rd_ptr [4]),
.dataf(!\A_SPW_TOP|rx_data|rd_ptr [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|always2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|always2~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|always2~0 .lut_mask = 64'h0080808080808081;
defparam \A_SPW_TOP|rx_data|always2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter[3]~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter[3]~1_combout = ( \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( \A_SPW_TOP|rx_data|f_full~q & ( (!\A_SPW_TOP|rx_data|block_read~q & (\A_SPW_TOP|rx_data|credit_counter[3]~4_combout & \A_SPW_TOP|rx_data|always2~0_combout )) )
// ) ) # ( !\A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( \A_SPW_TOP|rx_data|f_full~q & ( (!\A_SPW_TOP|rx_data|block_read~q & (\A_SPW_TOP|rx_data|credit_counter[3]~4_combout & \A_SPW_TOP|rx_data|always2~0_combout )) ) ) ) # (
// \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( !\A_SPW_TOP|rx_data|f_full~q & ( (!\A_SPW_TOP|rx_data|block_write~q ) # ((!\A_SPW_TOP|rx_data|block_read~q & (\A_SPW_TOP|rx_data|credit_counter[3]~4_combout & \A_SPW_TOP|rx_data|always2~0_combout ))) ) ) ) # (
// !\A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( !\A_SPW_TOP|rx_data|f_full~q & ( (!\A_SPW_TOP|rx_data|block_read~q & (\A_SPW_TOP|rx_data|credit_counter[3]~4_combout & \A_SPW_TOP|rx_data|always2~0_combout )) ) ) )
.dataa(!\A_SPW_TOP|rx_data|block_read~q ),
.datab(!\A_SPW_TOP|rx_data|credit_counter[3]~4_combout ),
.datac(!\A_SPW_TOP|rx_data|always2~0_combout ),
.datad(!\A_SPW_TOP|rx_data|block_write~q ),
.datae(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.dataf(!\A_SPW_TOP|rx_data|f_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[3]~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter[3]~1 .lut_mask = 64'h0202FF0202020202;
defparam \A_SPW_TOP|rx_data|credit_counter[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N35
dffeas \A_SPW_TOP|rx_data|credit_counter[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|credit_counter~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|credit_counter[3]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|credit_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter~2_combout = ( \A_SPW_TOP|rx_data|f_full~q & ( \A_SPW_TOP|rx_data|credit_counter [3] & ( !\A_SPW_TOP|rx_data|credit_counter [4] ) ) ) # ( !\A_SPW_TOP|rx_data|f_full~q & ( \A_SPW_TOP|rx_data|credit_counter [3] & (
// !\A_SPW_TOP|rx_data|credit_counter [4] $ (((!\A_SPW_TOP|rx_data|block_write~q & \A_SPW_TOP|SPW|RX|rx_buffer_write~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|f_full~q & ( !\A_SPW_TOP|rx_data|credit_counter [3] & ( \A_SPW_TOP|rx_data|credit_counter [4] ) ) ) # (
// !\A_SPW_TOP|rx_data|f_full~q & ( !\A_SPW_TOP|rx_data|credit_counter [3] & ( !\A_SPW_TOP|rx_data|credit_counter [4] $ (((!\A_SPW_TOP|rx_data|Add1~0_combout ) # ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|block_write~q )))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|credit_counter [4]),
.datab(!\A_SPW_TOP|rx_data|Add1~0_combout ),
.datac(!\A_SPW_TOP|rx_data|block_write~q ),
.datad(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datae(!\A_SPW_TOP|rx_data|f_full~q ),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter~2 .lut_mask = 64'h55655555AA5AAAAA;
defparam \A_SPW_TOP|rx_data|credit_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N32
dffeas \A_SPW_TOP|rx_data|credit_counter[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|credit_counter~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|credit_counter[3]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|credit_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter~5_combout = ( \A_SPW_TOP|rx_data|credit_counter [3] & ( (!\A_SPW_TOP|rx_data|credit_counter [4] & ((!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ) # (\A_SPW_TOP|rx_data|f_full~q ))) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter [3]
// & ( (!\A_SPW_TOP|rx_data|f_full~q & (\A_SPW_TOP|SPW|RX|rx_buffer_write~q & \A_SPW_TOP|rx_data|credit_counter [4])) ) )
.dataa(!\A_SPW_TOP|rx_data|f_full~q ),
.datab(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datac(!\A_SPW_TOP|rx_data|credit_counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter~5 .lut_mask = 64'h02020202D0D0D0D0;
defparam \A_SPW_TOP|rx_data|credit_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|credit_counter~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|credit_counter~0_combout = ( \A_SPW_TOP|rx_data|credit_counter [4] & ( \A_SPW_TOP|rx_data|credit_counter [3] & ( !\A_SPW_TOP|rx_data|credit_counter [5] $ (((!\A_SPW_TOP|rx_data|credit_counter~5_combout ) #
// ((!\A_SPW_TOP|rx_data|Add1~0_combout ) # (\A_SPW_TOP|rx_data|block_write~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter [4] & ( \A_SPW_TOP|rx_data|credit_counter [3] & ( !\A_SPW_TOP|rx_data|credit_counter [5] $
// (((!\A_SPW_TOP|rx_data|credit_counter~5_combout & !\A_SPW_TOP|rx_data|block_write~q ))) ) ) ) # ( \A_SPW_TOP|rx_data|credit_counter [4] & ( !\A_SPW_TOP|rx_data|credit_counter [3] & ( !\A_SPW_TOP|rx_data|credit_counter [5] $
// (((!\A_SPW_TOP|rx_data|credit_counter~5_combout ) # ((!\A_SPW_TOP|rx_data|Add1~0_combout ) # (\A_SPW_TOP|rx_data|block_write~q )))) ) ) ) # ( !\A_SPW_TOP|rx_data|credit_counter [4] & ( !\A_SPW_TOP|rx_data|credit_counter [3] & (
// \A_SPW_TOP|rx_data|credit_counter [5] ) ) )
.dataa(!\A_SPW_TOP|rx_data|credit_counter [5]),
.datab(!\A_SPW_TOP|rx_data|credit_counter~5_combout ),
.datac(!\A_SPW_TOP|rx_data|block_write~q ),
.datad(!\A_SPW_TOP|rx_data|Add1~0_combout ),
.datae(!\A_SPW_TOP|rx_data|credit_counter [4]),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|credit_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|credit_counter~0 .lut_mask = 64'h555555656A6A5565;
defparam \A_SPW_TOP|rx_data|credit_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N26
dffeas \A_SPW_TOP|rx_data|credit_counter[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|credit_counter~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|credit_counter[3]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|credit_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|credit_counter[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|credit_counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|rx_data|always0~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|always0~0_combout = ( \A_SPW_TOP|rx_data|credit_counter [3] & ( (!\A_SPW_TOP|rx_data|credit_counter [4] & (\A_SPW_TOP|SPW|RX|rx_buffer_write~q & !\A_SPW_TOP|rx_data|credit_counter [5])) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|rx_data|credit_counter [4]),
.datac(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datad(!\A_SPW_TOP|rx_data|credit_counter [5]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|credit_counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|always0~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|always0~0 .lut_mask = 64'h000000000C000C00;
defparam \A_SPW_TOP|rx_data|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y9_N41
dffeas \A_SPW_TOP|rx_data|overflow_credit_error (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|overflow_credit_error~feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|overflow_credit_error~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|overflow_credit_error .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|overflow_credit_error .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y9_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector5~1_combout = ( !\u0|link_disable|data_out~q & ( \A_SPW_TOP|SPW|FSM|after850ns [0] & ( (!\A_SPW_TOP|SPW|RX|rx_error~q & (!\A_SPW_TOP|rx_data|overflow_credit_error~q & ((!\A_SPW_TOP|SPW|FSM|Equal1~0_combout ) #
// (!\A_SPW_TOP|SPW|FSM|Equal1~1_combout )))) ) ) ) # ( !\u0|link_disable|data_out~q & ( !\A_SPW_TOP|SPW|FSM|after850ns [0] & ( (!\A_SPW_TOP|SPW|RX|rx_error~q & !\A_SPW_TOP|rx_data|overflow_credit_error~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Equal1~0_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_error~q ),
.datac(!\A_SPW_TOP|SPW|FSM|Equal1~1_combout ),
.datad(!\A_SPW_TOP|rx_data|overflow_credit_error~q ),
.datae(!\u0|link_disable|data_out~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|after850ns [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector5~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector5~1 .lut_mask = 64'hCC000000C8000000;
defparam \A_SPW_TOP|SPW|FSM|Selector5~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|Selector5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|Selector5~0_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( ((\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q & (\A_SPW_TOP|SPW|FSM|always0~1_combout & !\A_SPW_TOP|SPW|FSM|Equal0~3_combout ))) #
// (\A_SPW_TOP|SPW|FSM|Selector5~1_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|state_fsm.run~q & ( \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( (\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q & (\A_SPW_TOP|SPW|FSM|always0~1_combout &
// !\A_SPW_TOP|SPW|FSM|Equal0~3_combout )) ) ) ) # ( \A_SPW_TOP|SPW|FSM|state_fsm.run~q & ( !\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q & ( \A_SPW_TOP|SPW|FSM|Selector5~1_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|Selector5~1_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ),
.datac(!\A_SPW_TOP|SPW|FSM|always0~1_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|Equal0~3_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|Selector5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|Selector5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|Selector5~0 .lut_mask = 64'h0000555503005755;
defparam \A_SPW_TOP|SPW|FSM|Selector5~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N29
dffeas \A_SPW_TOP|SPW|FSM|state_fsm.run (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|Selector5~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|state_fsm.run .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|state_fsm.run .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_reset_n~0 (
// Equation(s):
// \A_SPW_TOP|tx_reset_n~0_combout = (!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ) # (\db_system_spwulight_b|aux_pb~q )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datab(gnd),
.datac(!\db_system_spwulight_b|aux_pb~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_reset_n~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_reset_n~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_reset_n~0 .lut_mask = 64'hAFAFAFAFAFAFAFAF;
defparam \A_SPW_TOP|tx_reset_n~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N43
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[81] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N29
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [81] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [81] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR
// [2] ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[86] .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y24_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y24_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_011|src_data [88] & \u0|mm_interconnect_0|cmd_mux_011|src_data [87]) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h2222222200F000F0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000ACACACAC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N35
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y24_N17
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_011|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_011|src_data [88]) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|src_data [87]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hA0A0A0A0CC00CC00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [86] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [86] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000C000C003F003F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N38
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [86] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [86] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00BB00BB00880088;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N40
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[79] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_011|src_data [79] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_data [79] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_data [79]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) #
// ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) )
// # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) )
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout &
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h0404CCCC0437CCFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [80] = (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout )))) #
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout
// ))))
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[80] .lut_mask = 64'h7350735073507350;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [80]))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|src_data [80]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000BB88BB88;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N59
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] & (
// (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] &
// ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & ( (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h37003700370037FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N49
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N47
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_011|src_data [86])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_011|src_data [86]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000000000F330F33;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y24_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y24_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] &
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [82] = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )
// ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant
// [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[82] .lut_mask = 64'h5F5F55550F0F0000;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_011|src_data [82]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|src_data [82]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y25_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0F5F0F5F33333333;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N50
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N48
cyclonev_lcell_comb \u0|write_en_tx|always0~0 (
// Equation(s):
// \u0|write_en_tx|always0~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout &
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_en_tx|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_en_tx|always0~0 .extended_lut = "off";
defparam \u0|write_en_tx|always0~0 .lut_mask = 64'h4000400000000000;
defparam \u0|write_en_tx|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N8
dffeas \u0|write_en_tx|data_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|write_en_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_en_tx|data_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_en_tx|data_out .is_wysiwyg = "true";
defparam \u0|write_en_tx|data_out .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~1_sumout = SUM(( \A_SPW_TOP|tx_data|counter [0] ) + ( VCC ) + ( !VCC ))
// \A_SPW_TOP|tx_data|Add0~2 = CARRY(( \A_SPW_TOP|tx_data|counter [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(!\A_SPW_TOP|tx_data|counter [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|tx_data|Add0~1_sumout ),
.cout(\A_SPW_TOP|tx_data|Add0~2 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~1 .lut_mask = 64'h0000000000003333;
defparam \A_SPW_TOP|tx_data|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N16
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] &
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]
// & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[81] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[86] .lut_mask = 64'h0055005533773377;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N38
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y23_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y23_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_015|src_data [88] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [88] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_015|src_data [87])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h05C505C500C000C0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_015|src_data [86])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000FC0CFC0C;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N17
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y23_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( (!\u0|mm_interconnect_0|cmd_mux_015|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_015|src_data [88]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hC0C0C0C0AA00AA00;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|cmd_mux_015|src_data [86]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h000000000C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N56
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[79] .lut_mask = 64'h7373737350505050;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_015|src_data [79] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [79] & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [79]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N44
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout )) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000AFA0AFA0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N58
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [0] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] )
// + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]
// & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])
// ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]
// & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])
// ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h3377337700000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N25
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM((
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [1] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[80] .lut_mask = 64'h7755775533003300;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_015|src_data [80] & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [80] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [80]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h5151515140404040;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout
// & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [1] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h000000FF333333FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )
// ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h11FF11FF00000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N19
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [2] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] )
// + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10
// ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_015|src_data [81] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]
// & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|src_data [81]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00CC00CC00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N41
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout
// )))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h05350535F5F5F5F5;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant
// [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[82] .lut_mask = 64'h33F333F300F000F0;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N2
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( (\u0|mm_interconnect_0|cmd_mux_015|src_data [86] & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout
// & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|src_data [86]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000F000F03030303;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y23_N14
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y23_N29
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [3] ) + ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_015|src_data [82]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|src_data [82]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [3] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h02570257AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N7
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N6
cyclonev_lcell_comb \u0|timecode_tx_enable|always0~0 (
// Equation(s):
// \u0|timecode_tx_enable|always0~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] &
// ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_enable|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_enable|always0~0 .extended_lut = "off";
defparam \u0|timecode_tx_enable|always0~0 .lut_mask = 64'h00C0000000000000;
defparam \u0|timecode_tx_enable|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y21_N26
dffeas \u0|timecode_tx_enable|data_out (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|timecode_tx_enable|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_enable|data_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_enable|data_out .is_wysiwyg = "true";
defparam \u0|timecode_tx_enable|data_out .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|send_fct_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout = (\A_SPW_TOP|SPW|FSM|state_fsm.run~q ) # (\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx~0 .lut_mask = 64'h3F3F3F3F3F3F3F3F;
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N38
dffeas \A_SPW_TOP|SPW|FSM|send_fct_tx (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|send_fct_tx .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N8
dffeas \A_SPW_TOP|rx_data|open_slot_fct (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|always2~0_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|open_slot_fct~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|open_slot_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|open_slot_fct .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag[1]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout = ( !\A_SPW_TOP|SPW|TX|block_sum_fct_send~q & ( \A_SPW_TOP|rx_data|open_slot_fct~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|block_sum_fct_send~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[1]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag[1]~0 .lut_mask = 64'h0F0F0F0F00000000;
defparam \A_SPW_TOP|SPW|TX|fct_flag[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|write_tx~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|write_tx~0_combout = ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q & ( (\A_SPW_TOP|tx_data|write_tx~q ) # (\A_SPW_TOP|tx_data|Equal1~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|Equal1~0_combout ),
.datad(!\A_SPW_TOP|tx_data|write_tx~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|write_tx~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|write_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|write_tx~0 .lut_mask = 64'h0FFF0FFF00000000;
defparam \A_SPW_TOP|tx_data|write_tx~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N23
dffeas \A_SPW_TOP|tx_data|write_tx (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|write_tx~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|write_tx~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|write_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|write_tx .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always7~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always7~3_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( !\A_SPW_TOP|SPW|TX|hold_fct~q ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|hold_fct~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always7~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always7~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always7~3 .lut_mask = 64'hCCCCCCCC00000000;
defparam \A_SPW_TOP|SPW|TX|always7~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always7~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always7~5_combout = ( \A_SPW_TOP|SPW|TX|always7~3_combout & ( (\A_SPW_TOP|tx_data|write_tx~q & !\A_SPW_TOP|SPW|TX|LessThan2~0_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always7~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always7~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always7~5 .lut_mask = 64'h0000000044444444;
defparam \A_SPW_TOP|SPW|TX|always7~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector5~1_combout = ( \A_SPW_TOP|SPW|TX|hold_null~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ) ) # ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & (((!\u0|timecode_tx_enable|data_out~q ) #
// (\A_SPW_TOP|SPW|TX|hold_data~q )) # (\A_SPW_TOP|SPW|TX|hold_fct~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_fct~q ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datac(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datad(!\u0|timecode_tx_enable|data_out~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector5~1 .lut_mask = 64'h3313331333333333;
defparam \A_SPW_TOP|SPW|TX|Selector5~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Add2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Add2~0_combout = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ( (\A_SPW_TOP|SPW|TX|always7~4_combout & (((!\A_SPW_TOP|SPW|TX|Selector5~1_combout ) #
// (\A_SPW_TOP|SPW|TX|always7~5_combout )) # (\A_SPW_TOP|SPW|TX|always7~1_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ( (\A_SPW_TOP|SPW|TX|always7~1_combout &
// \A_SPW_TOP|SPW|TX|Selector5~1_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datab(!\A_SPW_TOP|SPW|TX|always7~5_combout ),
.datac(!\A_SPW_TOP|SPW|TX|always7~4_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
.datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Add2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Add2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Add2~0 .lut_mask = 64'h005500000F070000;
defparam \A_SPW_TOP|SPW|TX|Add2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag~3_combout = ( \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout & ( !\A_SPW_TOP|SPW|TX|fct_flag [0] $ (!\A_SPW_TOP|SPW|TX|fct_flag [1] $ (((!\A_SPW_TOP|SPW|TX|Equal5~0_combout ) # (!\A_SPW_TOP|SPW|TX|Add2~0_combout )))) ) ) # (
// !\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout & ( (!\A_SPW_TOP|SPW|TX|Equal5~0_combout ) # ((!\A_SPW_TOP|SPW|TX|Add2~0_combout ) # (!\A_SPW_TOP|SPW|TX|fct_flag [0] $ (!\A_SPW_TOP|SPW|TX|fct_flag [1]))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datab(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Add2~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_flag~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag~3 .lut_mask = 64'hFFF6FFF699969996;
defparam \A_SPW_TOP|SPW|TX|fct_flag~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|enable_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|enable_tx~0_combout = ( \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q & ( !\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .lut_mask = 64'h00000000AAAAAAAA;
defparam \A_SPW_TOP|SPW|FSM|enable_tx~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N56
dffeas \A_SPW_TOP|SPW|FSM|enable_tx (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|enable_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|enable_tx .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag[1]~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout = ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( \A_SPW_TOP|SPW|TX|Selector4~2_combout & ( \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & (
// \A_SPW_TOP|SPW|TX|Selector4~2_combout & ( \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) ) ) # ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( !\A_SPW_TOP|SPW|TX|Selector4~2_combout & ( (\A_SPW_TOP|SPW|TX|Equal5~0_combout ) #
// (\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( !\A_SPW_TOP|SPW|TX|Selector4~2_combout & ( (\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout & ((\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ) #
// (\A_SPW_TOP|SPW|TX|last_type~14_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datab(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[1]~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag[1]~2 .lut_mask = 64'h07070FFF0F0F0F0F;
defparam \A_SPW_TOP|SPW|TX|fct_flag[1]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y10_N44
dffeas \A_SPW_TOP|SPW|TX|fct_flag[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|fct_flag~3_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_flag [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag~1_combout = ( \A_SPW_TOP|SPW|TX|Add2~0_combout & ( \A_SPW_TOP|SPW|TX|fct_flag [2] & ( (!\A_SPW_TOP|SPW|TX|Equal5~0_combout & ((!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) # ((\A_SPW_TOP|SPW|TX|fct_flag [0]) #
// (\A_SPW_TOP|SPW|TX|fct_flag [1])))) # (\A_SPW_TOP|SPW|TX|Equal5~0_combout & (((!\A_SPW_TOP|SPW|TX|fct_flag [1]) # (!\A_SPW_TOP|SPW|TX|fct_flag [0])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Add2~0_combout & ( \A_SPW_TOP|SPW|TX|fct_flag [2] & (
// (!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) # ((\A_SPW_TOP|SPW|TX|fct_flag [0]) # (\A_SPW_TOP|SPW|TX|fct_flag [1])) ) ) ) # ( \A_SPW_TOP|SPW|TX|Add2~0_combout & ( !\A_SPW_TOP|SPW|TX|fct_flag [2] & ( (!\A_SPW_TOP|SPW|TX|Equal5~0_combout &
// ((!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) # ((!\A_SPW_TOP|SPW|TX|fct_flag [1] & !\A_SPW_TOP|SPW|TX|fct_flag [0])))) # (\A_SPW_TOP|SPW|TX|Equal5~0_combout & (((\A_SPW_TOP|SPW|TX|fct_flag [1] & \A_SPW_TOP|SPW|TX|fct_flag [0])))) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|Add2~0_combout & ( !\A_SPW_TOP|SPW|TX|fct_flag [2] & ( (!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ) # ((!\A_SPW_TOP|SPW|TX|fct_flag [1] & !\A_SPW_TOP|SPW|TX|fct_flag [0])) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
.datad(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datae(!\A_SPW_TOP|SPW|TX|Add2~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_flag~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag~1 .lut_mask = 64'hFAAAC88BAFFFBFFC;
defparam \A_SPW_TOP|SPW|TX|fct_flag~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y10_N20
dffeas \A_SPW_TOP|SPW|TX|fct_flag[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|fct_flag~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_flag [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector5~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector5~2_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ( (\A_SPW_TOP|SPW|FSM|send_fct_tx~q & ((!\A_SPW_TOP|SPW|TX|fct_flag [2]) # ((!\A_SPW_TOP|SPW|TX|fct_flag [1]) #
// (!\A_SPW_TOP|SPW|TX|fct_flag [0])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
.datab(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.datac(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
.datad(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datae(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector5~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector5~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector5~2 .lut_mask = 64'h0000000033320000;
defparam \A_SPW_TOP|SPW|TX|Selector5~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector5~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector5~3_combout = ( \A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( ((!\u0|timecode_tx_enable|data_out~q ) # ((!\A_SPW_TOP|SPW|TX|always7~3_combout ) # (\A_SPW_TOP|SPW|TX|Selector5~2_combout
// ))) # (\A_SPW_TOP|SPW|TX|hold_data~q ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( \A_SPW_TOP|SPW|TX|Selector5~2_combout ) ) ) # ( \A_SPW_TOP|SPW|TX|always7~1_combout & (
// !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( \A_SPW_TOP|SPW|TX|Selector5~2_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( \A_SPW_TOP|SPW|TX|Selector5~2_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datab(!\u0|timecode_tx_enable|data_out~q ),
.datac(!\A_SPW_TOP|SPW|TX|Selector5~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector5~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector5~3 .lut_mask = 64'h0F0F0F0F0F0FFFDF;
defparam \A_SPW_TOP|SPW|TX|Selector5~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_e~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_e~0_combout = ( \A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( \A_SPW_TOP|SPW|TX|always7~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & (
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( ((!\A_SPW_TOP|SPW|TX|LessThan2~0_combout & (\A_SPW_TOP|tx_data|write_tx~q & \A_SPW_TOP|SPW|TX|always7~3_combout ))) # (\A_SPW_TOP|SPW|TX|always7~0_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|tx_data|write_tx~q ),
.datad(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~0 .lut_mask = 64'h00000000555D5555;
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|block_sum_fct_send~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|block_sum_fct_send~0_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_e~0_combout & ( \A_SPW_TOP|rx_data|open_slot_fct~q & ( (!\A_SPW_TOP|SPW|TX|Selector5~3_combout ) # (((!\A_SPW_TOP|SPW|TX|Equal5~0_combout ) #
// (\A_SPW_TOP|SPW|TX|Selector4~2_combout )) # (\A_SPW_TOP|SPW|TX|block_sum_fct_send~q )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout & ( \A_SPW_TOP|rx_data|open_slot_fct~q & ( (((\A_SPW_TOP|SPW|TX|Selector5~3_combout &
// !\A_SPW_TOP|SPW|TX|Equal5~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout )) # (\A_SPW_TOP|SPW|TX|block_sum_fct_send~q ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout_e~0_combout & ( !\A_SPW_TOP|rx_data|open_slot_fct~q & (
// (\A_SPW_TOP|SPW|TX|Selector5~3_combout & (\A_SPW_TOP|SPW|TX|block_sum_fct_send~q & (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & \A_SPW_TOP|SPW|TX|Equal5~0_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout & (
// !\A_SPW_TOP|rx_data|open_slot_fct~q & ( (\A_SPW_TOP|SPW|TX|block_sum_fct_send~q & (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((!\A_SPW_TOP|SPW|TX|Selector5~3_combout ) # (\A_SPW_TOP|SPW|TX|Equal5~0_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datab(!\A_SPW_TOP|SPW|TX|block_sum_fct_send~q ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.dataf(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|block_sum_fct_send~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|block_sum_fct_send~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|block_sum_fct_send~0 .lut_mask = 64'h203000107F3FFFBF;
defparam \A_SPW_TOP|SPW|TX|block_sum_fct_send~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y10_N17
dffeas \A_SPW_TOP|SPW|TX|block_sum_fct_send (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|block_sum_fct_send~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|block_sum_fct_send~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|block_sum_fct_send .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|block_sum_fct_send .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag~4_combout = ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( !\A_SPW_TOP|SPW|TX|fct_flag [0] $ (((\A_SPW_TOP|rx_data|open_slot_fct~q & (!\A_SPW_TOP|SPW|TX|block_sum_fct_send~q & ((\A_SPW_TOP|SPW|TX|Selector4~2_combout ) #
// (\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout )))))) ) ) # ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( !\A_SPW_TOP|SPW|TX|fct_flag [0] $ (((!\A_SPW_TOP|rx_data|open_slot_fct~q & (\A_SPW_TOP|SPW|TX|Equal5~0_combout & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout
// )))) # (\A_SPW_TOP|rx_data|open_slot_fct~q & ((!\A_SPW_TOP|SPW|TX|block_sum_fct_send~q ) # ((\A_SPW_TOP|SPW|TX|Equal5~0_combout & !\A_SPW_TOP|SPW|TX|Selector4~2_combout )))))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datab(!\A_SPW_TOP|rx_data|open_slot_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|block_sum_fct_send~q ),
.datae(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datag(!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_flag~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag~4 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|TX|fct_flag~4 .lut_mask = 64'hA9AA95A599AA99AA;
defparam \A_SPW_TOP|SPW|TX|fct_flag~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_flag[0]~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_flag[0]~10_combout = ( !\A_SPW_TOP|SPW|TX|fct_flag~4_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_flag~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_flag[0]~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[0]~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_flag[0]~10 .lut_mask = 64'hFFFFFFFF00000000;
defparam \A_SPW_TOP|SPW|TX|fct_flag[0]~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y10_N50
dffeas \A_SPW_TOP|SPW|TX|fct_flag[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|fct_flag[0]~10_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_flag [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_flag[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_flag[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always7~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always7~4_combout = ( \A_SPW_TOP|SPW|TX|fct_flag [2] & ( (\A_SPW_TOP|SPW|FSM|send_fct_tx~q & (!\A_SPW_TOP|SPW|TX|hold_null~q & ((!\A_SPW_TOP|SPW|TX|fct_flag [0]) # (!\A_SPW_TOP|SPW|TX|fct_flag [1])))) ) ) # (
// !\A_SPW_TOP|SPW|TX|fct_flag [2] & ( (\A_SPW_TOP|SPW|FSM|send_fct_tx~q & !\A_SPW_TOP|SPW|TX|hold_null~q ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datab(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
.datac(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.datad(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always7~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always7~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always7~4 .lut_mask = 64'h0F000F000E000E00;
defparam \A_SPW_TOP|SPW|TX|always7~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector3~0_combout = ( \A_SPW_TOP|SPW|TX|always7~4_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ) ) # ( !\A_SPW_TOP|SPW|TX|always7~4_combout & ( ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q &
// (\A_SPW_TOP|SPW|FSM|send_fct_tx~q & !\A_SPW_TOP|SPW|TX|LessThan2~0_combout ))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datac(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.datad(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|always7~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector3~0 .lut_mask = 64'h5755575555555555;
defparam \A_SPW_TOP|SPW|TX|Selector3~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N44
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|Selector3~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|enable_time_code~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|enable_time_code~0_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( (\u0|timecode_tx_enable|data_out~q & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & (!\A_SPW_TOP|SPW|TX|hold_data~q & !\A_SPW_TOP|SPW|TX|hold_fct~q ))) ) )
.dataa(!\u0|timecode_tx_enable|data_out~q ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datac(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datad(!\A_SPW_TOP|SPW|TX|hold_fct~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|enable_time_code~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|enable_time_code~0 .lut_mask = 64'h1000100000000000;
defparam \A_SPW_TOP|SPW|TX|enable_time_code~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector5~0_combout = ( \u0|timecode_tx_enable|data_out~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & (\A_SPW_TOP|SPW|TX|always7~1_combout & ((!\A_SPW_TOP|SPW|TX|always7~3_combout ) # (\A_SPW_TOP|SPW|TX|hold_data~q )))) ) ) # (
// !\u0|timecode_tx_enable|data_out~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & \A_SPW_TOP|SPW|TX|always7~1_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datab(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datad(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datae(gnd),
.dataf(!\u0|timecode_tx_enable|data_out~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector5~0 .lut_mask = 64'h000F000F000D000D;
defparam \A_SPW_TOP|SPW|TX|Selector5~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout = ( !\A_SPW_TOP|SPW|TX|Equal5~0_combout & ( (((\A_SPW_TOP|tx_data|data_out [8] & !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector5~2_combout )) #
// (\A_SPW_TOP|SPW|TX|Selector5~0_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~2_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0 .lut_mask = 64'h4FFF4FFF00000000;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer~5_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout &
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|last_type~10_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & (
// \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout &
// (!\A_SPW_TOP|SPW|TX|last_type~10_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout ) #
// (!\A_SPW_TOP|SPW|TX|last_type~10_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout &
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|last_type~10_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~5 .lut_mask = 64'h4E00EE004E004E00;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector4~0_combout = ( \A_SPW_TOP|SPW|TX|always7~3_combout & ( (\A_SPW_TOP|SPW|TX|Selector5~1_combout & (!\A_SPW_TOP|SPW|TX|always7~1_combout & ((!\A_SPW_TOP|tx_data|write_tx~q ) # (\A_SPW_TOP|SPW|TX|LessThan2~0_combout )))) ) ) # (
// !\A_SPW_TOP|SPW|TX|always7~3_combout & ( (\A_SPW_TOP|SPW|TX|Selector5~1_combout & !\A_SPW_TOP|SPW|TX|always7~1_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector4~0 .lut_mask = 64'h0F000F000B000B00;
defparam \A_SPW_TOP|SPW|TX|Selector4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ( (((\A_SPW_TOP|SPW|TX|Selector5~0_combout ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q )) #
// (\A_SPW_TOP|SPW|TX|Selector4~0_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3 .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y11_N59
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|global_counter_transfer~5_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Add4~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Add4~0_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] $ (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) ) # (
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Add4~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Add4~0 .lut_mask = 64'h5555555556565656;
defparam \A_SPW_TOP|SPW|TX|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer~2_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & ( \A_SPW_TOP|SPW|TX|Add4~0_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((!\A_SPW_TOP|SPW|TX|Selector5~3_combout ) #
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout )))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (((!\A_SPW_TOP|SPW|TX|last_type~10_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & (
// \A_SPW_TOP|SPW|TX|Add4~0_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout )) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((!\A_SPW_TOP|SPW|TX|last_type~10_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Add4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~2 .lut_mask = 64'h000000005F0ADF8A;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y11_N50
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|global_counter_transfer~2_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~21 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~21_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] &
// \A_SPW_TOP|tx_data|data_out [8])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|tx_data|data_out [8])))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datad(!\A_SPW_TOP|tx_data|data_out [8]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~21 .lut_mask = 64'h0402040200000000;
defparam \A_SPW_TOP|SPW|TX|last_type~21 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|ready_tx_data~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|ready_tx_data~0_combout = ( \A_SPW_TOP|SPW|TX|ready_tx_data~q & ( (!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & ((!\A_SPW_TOP|SPW|TX|last_type~14_combout ) #
// (\A_SPW_TOP|SPW|TX|last_type~21_combout )))) ) ) # ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q & ( (!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (\A_SPW_TOP|SPW|TX|last_type~14_combout &
// \A_SPW_TOP|SPW|TX|last_type~21_combout ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|ready_tx_data~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_data~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|ready_tx_data~0 .lut_mask = 64'h0002000220222022;
defparam \A_SPW_TOP|SPW|TX|ready_tx_data~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N11
dffeas \A_SPW_TOP|SPW|TX|ready_tx_data (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|ready_tx_data~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|ready_tx_data .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|counter~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|counter~0_combout = ( \A_SPW_TOP|tx_data|f_empty~q & ( \A_SPW_TOP|SPW|TX|ready_tx_data~q & ( !\A_SPW_TOP|tx_data|block_read~q $ (((!\A_SPW_TOP|tx_data|f_full~q & (\u0|write_en_tx|data_out~q & !\A_SPW_TOP|tx_data|block_write~q ))))
// ) ) ) # ( !\A_SPW_TOP|tx_data|f_empty~q & ( \A_SPW_TOP|SPW|TX|ready_tx_data~q & ( (!\A_SPW_TOP|tx_data|f_full~q & (\u0|write_en_tx|data_out~q & !\A_SPW_TOP|tx_data|block_write~q )) ) ) ) # ( \A_SPW_TOP|tx_data|f_empty~q & (
// !\A_SPW_TOP|SPW|TX|ready_tx_data~q & ( (!\A_SPW_TOP|tx_data|f_full~q & (\u0|write_en_tx|data_out~q & !\A_SPW_TOP|tx_data|block_write~q )) ) ) ) # ( !\A_SPW_TOP|tx_data|f_empty~q & ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q & ( (!\A_SPW_TOP|tx_data|f_full~q
// & (\u0|write_en_tx|data_out~q & !\A_SPW_TOP|tx_data|block_write~q )) ) ) )
.dataa(!\A_SPW_TOP|tx_data|f_full~q ),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(!\A_SPW_TOP|tx_data|block_write~q ),
.datad(!\A_SPW_TOP|tx_data|block_read~q ),
.datae(!\A_SPW_TOP|tx_data|f_empty~q ),
.dataf(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|counter~0 .lut_mask = 64'h202020202020DF20;
defparam \A_SPW_TOP|tx_data|counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N32
dffeas \A_SPW_TOP|tx_data|counter[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add0~1_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~5_sumout = SUM(( \A_SPW_TOP|tx_data|counter [1] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~2 ))
// \A_SPW_TOP|tx_data|Add0~6 = CARRY(( \A_SPW_TOP|tx_data|counter [1] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~2 ))
.dataa(!\A_SPW_TOP|tx_data|block_write~q ),
.datab(gnd),
.datac(!\u0|write_en_tx|data_out~q ),
.datad(!\A_SPW_TOP|tx_data|counter [1]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|f_full~q ),
.datag(gnd),
.cin(\A_SPW_TOP|tx_data|Add0~2 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|tx_data|Add0~5_sumout ),
.cout(\A_SPW_TOP|tx_data|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~5 .lut_mask = 64'h00000A00000000FF;
defparam \A_SPW_TOP|tx_data|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N47
dffeas \A_SPW_TOP|tx_data|counter[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add0~5_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~9_sumout = SUM(( \A_SPW_TOP|tx_data|counter [2] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~6 ))
// \A_SPW_TOP|tx_data|Add0~10 = CARRY(( \A_SPW_TOP|tx_data|counter [2] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~6 ))
.dataa(!\A_SPW_TOP|tx_data|block_write~q ),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(!\A_SPW_TOP|tx_data|f_full~q ),
.datad(!\A_SPW_TOP|tx_data|counter [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\A_SPW_TOP|tx_data|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|tx_data|Add0~9_sumout ),
.cout(\A_SPW_TOP|tx_data|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~9 .lut_mask = 64'h00002020000000FF;
defparam \A_SPW_TOP|tx_data|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~13_sumout = SUM(( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|counter [3] ) + ( \A_SPW_TOP|tx_data|Add0~10 ))
// \A_SPW_TOP|tx_data|Add0~14 = CARRY(( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|counter [3] ) + ( \A_SPW_TOP|tx_data|Add0~10 ))
.dataa(!\A_SPW_TOP|tx_data|block_write~q ),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(!\A_SPW_TOP|tx_data|f_full~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|counter [3]),
.datag(gnd),
.cin(\A_SPW_TOP|tx_data|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|tx_data|Add0~13_sumout ),
.cout(\A_SPW_TOP|tx_data|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~13 .lut_mask = 64'h0000FF000000DFDF;
defparam \A_SPW_TOP|tx_data|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N35
dffeas \A_SPW_TOP|tx_data|counter[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add0~13_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~17_sumout = SUM(( \A_SPW_TOP|tx_data|counter [4] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~14 ))
// \A_SPW_TOP|tx_data|Add0~18 = CARRY(( \A_SPW_TOP|tx_data|counter [4] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~14 ))
.dataa(!\A_SPW_TOP|tx_data|block_write~q ),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(!\A_SPW_TOP|tx_data|counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|f_full~q ),
.datag(gnd),
.cin(\A_SPW_TOP|tx_data|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|tx_data|Add0~17_sumout ),
.cout(\A_SPW_TOP|tx_data|Add0~18 ),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~17 .lut_mask = 64'h0000220000000F0F;
defparam \A_SPW_TOP|tx_data|Add0~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N26
dffeas \A_SPW_TOP|tx_data|counter[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add0~17_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add0~21 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add0~21_sumout = SUM(( \A_SPW_TOP|tx_data|counter [5] ) + ( ((!\u0|write_en_tx|data_out~q ) # (\A_SPW_TOP|tx_data|f_full~q )) # (\A_SPW_TOP|tx_data|block_write~q ) ) + ( \A_SPW_TOP|tx_data|Add0~18 ))
.dataa(!\A_SPW_TOP|tx_data|block_write~q ),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(!\A_SPW_TOP|tx_data|counter [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|f_full~q ),
.datag(gnd),
.cin(\A_SPW_TOP|tx_data|Add0~18 ),
.sharein(gnd),
.combout(),
.sumout(\A_SPW_TOP|tx_data|Add0~21_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add0~21 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add0~21 .lut_mask = 64'h0000220000000F0F;
defparam \A_SPW_TOP|tx_data|Add0~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N44
dffeas \A_SPW_TOP|tx_data|counter[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add0~21_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Equal0~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Equal0~0_combout = ( \A_SPW_TOP|tx_data|counter [2] & ( \A_SPW_TOP|tx_data|counter [4] & ( (\A_SPW_TOP|tx_data|counter [1] & (\A_SPW_TOP|tx_data|counter [5] & (\A_SPW_TOP|tx_data|counter [3] & \A_SPW_TOP|tx_data|counter [0]))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|counter [1]),
.datab(!\A_SPW_TOP|tx_data|counter [5]),
.datac(!\A_SPW_TOP|tx_data|counter [3]),
.datad(!\A_SPW_TOP|tx_data|counter [0]),
.datae(!\A_SPW_TOP|tx_data|counter [2]),
.dataf(!\A_SPW_TOP|tx_data|counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Equal0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Equal0~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Equal0~0 .lut_mask = 64'h0000000000000001;
defparam \A_SPW_TOP|tx_data|Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N50
dffeas \A_SPW_TOP|tx_data|f_full (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|Equal0~0_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|f_full~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|f_full .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|f_full .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|block_write~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|block_write~0_combout = (\u0|write_en_tx|data_out~q & ((!\A_SPW_TOP|tx_data|f_full~q ) # (\A_SPW_TOP|tx_data|block_write~q )))
.dataa(gnd),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(!\A_SPW_TOP|tx_data|block_write~q ),
.datad(!\A_SPW_TOP|tx_data|f_full~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|block_write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|block_write~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|block_write~0 .lut_mask = 64'h3303330333033303;
defparam \A_SPW_TOP|tx_data|block_write~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N53
dffeas \A_SPW_TOP|tx_data|block_write (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|block_write~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|block_write~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|block_write .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|block_write .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y11_N29
dffeas \A_SPW_TOP|tx_data|counter[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add0~9_sumout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|counter~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|counter[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Equal1~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Equal1~0_combout = ( \A_SPW_TOP|tx_data|counter [4] & ( \A_SPW_TOP|tx_data|counter [3] ) ) # ( !\A_SPW_TOP|tx_data|counter [4] & ( \A_SPW_TOP|tx_data|counter [3] ) ) # ( \A_SPW_TOP|tx_data|counter [4] & ( !\A_SPW_TOP|tx_data|counter
// [3] ) ) # ( !\A_SPW_TOP|tx_data|counter [4] & ( !\A_SPW_TOP|tx_data|counter [3] & ( (((\A_SPW_TOP|tx_data|counter [5]) # (\A_SPW_TOP|tx_data|counter [1])) # (\A_SPW_TOP|tx_data|counter [0])) # (\A_SPW_TOP|tx_data|counter [2]) ) ) )
.dataa(!\A_SPW_TOP|tx_data|counter [2]),
.datab(!\A_SPW_TOP|tx_data|counter [0]),
.datac(!\A_SPW_TOP|tx_data|counter [1]),
.datad(!\A_SPW_TOP|tx_data|counter [5]),
.datae(!\A_SPW_TOP|tx_data|counter [4]),
.dataf(!\A_SPW_TOP|tx_data|counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Equal1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Equal1~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Equal1~0 .lut_mask = 64'h7FFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|tx_data|Equal1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N56
dffeas \A_SPW_TOP|tx_data|f_empty (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Equal1~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|f_empty~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|f_empty .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|f_empty .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|block_read~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|block_read~0_combout = (\A_SPW_TOP|SPW|TX|ready_tx_data~q & ((\A_SPW_TOP|tx_data|block_read~q ) # (\A_SPW_TOP|tx_data|f_empty~q )))
.dataa(!\A_SPW_TOP|tx_data|f_empty~q ),
.datab(!\A_SPW_TOP|tx_data|block_read~q ),
.datac(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|block_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|block_read~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|block_read~0 .lut_mask = 64'h0707070707070707;
defparam \A_SPW_TOP|tx_data|block_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y11_N59
dffeas \A_SPW_TOP|tx_data|block_read (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|block_read~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|block_read~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|block_read .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|block_read .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem~0 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|mem~0feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~0_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~0 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [8] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [8]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N46
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y16_N39
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[8]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[8]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [8] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|data_out[8]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[8]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[8]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[81] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_010|src_data [81] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [81] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [86] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0])) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] & \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[86] .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y22_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y22_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_010|src_data [88] & \u0|mm_interconnect_0|cmd_mux_010|src_data [87])))) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_010|src_data [88] & \u0|mm_interconnect_0|cmd_mux_010|src_data [87])) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h0050005088D888D8;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000CCF0CCF0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N13
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y22_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_010|src_data [88])) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_010|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_010|src_data [88])))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [87]),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hD888D88850005000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[80] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y23_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout
// & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [1] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_010|src_data [80] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [80] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [80]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|cmd_mux_010|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000053535353;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N23
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000AACCAACC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[79] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout
// & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_010|src_data [79]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|src_data [79]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000B8B8B8B8;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N47
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [0] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] )
// + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h333F0000333F5555;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N13
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM((
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [1] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [1])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0011CCDD0C1DCCDD;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N25
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM((
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]
// ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10
// ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000003333;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout & (
// \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout
// & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [1] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h000000FF555555FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & (
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]
// & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])))
// ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0C4C0C4C3F7F3F7F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N30
cyclonev_lcell_comb \u0|write_data_fifo_tx|always0~0 (
// Equation(s):
// \u0|write_data_fifo_tx|always0~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|always0~0 .extended_lut = "off";
defparam \u0|write_data_fifo_tx|always0~0 .lut_mask = 64'h2000200000000000;
defparam \u0|write_data_fifo_tx|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y16_N41
dffeas \u0|write_data_fifo_tx|data_out[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|data_out[8]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[8] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|wr_ptr[0]~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|wr_ptr[0]~0_combout = !\A_SPW_TOP|tx_data|wr_ptr [0]
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|wr_ptr[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \A_SPW_TOP|tx_data|wr_ptr[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|mem~14_combout = ( !\A_SPW_TOP|tx_data|f_full~q & ( (!\A_SPW_TOP|tx_data|block_write~q & \u0|write_en_tx|data_out~q ) ) )
.dataa(!\A_SPW_TOP|tx_data|block_write~q ),
.datab(!\u0|write_en_tx|data_out~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|f_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem~14 .lut_mask = 64'h2222222200000000;
defparam \A_SPW_TOP|tx_data|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N53
dffeas \A_SPW_TOP|tx_data|wr_ptr[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~14_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|wr_ptr [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|comb~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|comb~0_combout = ( !\A_SPW_TOP|tx_data|f_full~q & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q & (!\db_system_spwulight_b|aux_pb~q & (!\A_SPW_TOP|tx_data|block_write~q & \u0|write_en_tx|data_out~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datab(!\db_system_spwulight_b|aux_pb~q ),
.datac(!\A_SPW_TOP|tx_data|block_write~q ),
.datad(!\u0|write_en_tx|data_out~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|f_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|comb~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|comb~0 .lut_mask = 64'h0040004000000000;
defparam \A_SPW_TOP|tx_data|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~1_combout = !\A_SPW_TOP|tx_data|wr_ptr [1] $ (!\A_SPW_TOP|tx_data|wr_ptr [0])
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Add2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~1 .lut_mask = 64'h55AA55AA55AA55AA;
defparam \A_SPW_TOP|tx_data|Add2~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N50
dffeas \A_SPW_TOP|tx_data|wr_ptr[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add2~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~14_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|wr_ptr [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~2_combout = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] $ (!\A_SPW_TOP|tx_data|wr_ptr [2]) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [2] ) )
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|wr_ptr [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Add2~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~2 .lut_mask = 64'h0F0F0F0F5A5A5A5A;
defparam \A_SPW_TOP|tx_data|Add2~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N23
dffeas \A_SPW_TOP|tx_data|wr_ptr[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add2~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~14_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|wr_ptr [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~3_combout = ( \A_SPW_TOP|tx_data|wr_ptr [1] & ( !\A_SPW_TOP|tx_data|wr_ptr [3] $ (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # (!\A_SPW_TOP|tx_data|wr_ptr [2]))) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [1] & ( \A_SPW_TOP|tx_data|wr_ptr [3] ) )
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|wr_ptr [3]),
.datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Add2~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~3 .lut_mask = 64'h0F0F0F0F0F5A0F5A;
defparam \A_SPW_TOP|tx_data|Add2~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N20
dffeas \A_SPW_TOP|tx_data|wr_ptr[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add2~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~14_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|wr_ptr [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~4_combout = ( \A_SPW_TOP|tx_data|wr_ptr [2] & ( !\A_SPW_TOP|tx_data|wr_ptr [4] $ (((!\A_SPW_TOP|tx_data|wr_ptr [0]) # ((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (!\A_SPW_TOP|tx_data|wr_ptr [3])))) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [2] &
// ( \A_SPW_TOP|tx_data|wr_ptr [4] ) )
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datab(!\A_SPW_TOP|tx_data|wr_ptr [4]),
.datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
.datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Add2~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~4 .lut_mask = 64'h3333333333363336;
defparam \A_SPW_TOP|tx_data|Add2~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N56
dffeas \A_SPW_TOP|tx_data|wr_ptr[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add2~4_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~14_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|wr_ptr [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add2~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add2~0_combout = ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( !\A_SPW_TOP|tx_data|wr_ptr [5] $ (((!\A_SPW_TOP|tx_data|wr_ptr [3]) # ((!\A_SPW_TOP|tx_data|wr_ptr [1]) # (!\A_SPW_TOP|tx_data|wr_ptr [2])))) ) ) )
// # ( !\A_SPW_TOP|tx_data|wr_ptr [4] & ( \A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [5] ) ) ) # ( \A_SPW_TOP|tx_data|wr_ptr [4] & ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [5] ) ) ) # ( !\A_SPW_TOP|tx_data|wr_ptr [4] &
// ( !\A_SPW_TOP|tx_data|wr_ptr [0] & ( \A_SPW_TOP|tx_data|wr_ptr [5] ) ) )
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [3]),
.datab(!\A_SPW_TOP|tx_data|wr_ptr [5]),
.datac(!\A_SPW_TOP|tx_data|wr_ptr [1]),
.datad(!\A_SPW_TOP|tx_data|wr_ptr [2]),
.datae(!\A_SPW_TOP|tx_data|wr_ptr [4]),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Add2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add2~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add2~0 .lut_mask = 64'h3333333333333336;
defparam \A_SPW_TOP|tx_data|Add2~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N59
dffeas \A_SPW_TOP|tx_data|wr_ptr[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|Add2~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~14_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|wr_ptr [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|wr_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|wr_ptr[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|mem~12_combout = ( !\A_SPW_TOP|tx_data|wr_ptr [2] & ( (!\A_SPW_TOP|tx_data|wr_ptr [1] & (!\A_SPW_TOP|tx_data|wr_ptr [4] & !\A_SPW_TOP|tx_data|wr_ptr [3])) ) )
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [1]),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|wr_ptr [4]),
.datad(!\A_SPW_TOP|tx_data|wr_ptr [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem~12 .lut_mask = 64'hA000A00000000000;
defparam \A_SPW_TOP|tx_data|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|mem~13_combout = (!\A_SPW_TOP|tx_data|wr_ptr [0] & (\A_SPW_TOP|tx_data|comb~0_combout & (!\A_SPW_TOP|tx_data|wr_ptr [5] & \A_SPW_TOP|tx_data|mem~12_combout )))
.dataa(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datab(!\A_SPW_TOP|tx_data|comb~0_combout ),
.datac(!\A_SPW_TOP|tx_data|wr_ptr [5]),
.datad(!\A_SPW_TOP|tx_data|mem~12_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem~13 .lut_mask = 64'h0020002000200020;
defparam \A_SPW_TOP|tx_data|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N32
dffeas \A_SPW_TOP|tx_data|mem~9 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [8]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~9_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~9 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~9 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|block_read~_wirecell (
// Equation(s):
// \A_SPW_TOP|tx_data|block_read~_wirecell_combout = !\A_SPW_TOP|tx_data|block_read~q
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|block_read~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|block_read~_wirecell_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|block_read~_wirecell .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|block_read~_wirecell .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \A_SPW_TOP|tx_data|block_read~_wirecell .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N43
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y16_N42
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[0]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[0]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|data_out[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[0]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y16_N44
dffeas \u0|write_data_fifo_tx|data_out[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|data_out[0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[0] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y11_N41
dffeas \A_SPW_TOP|tx_data|rd_ptr[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|rd_ptr [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~1_combout = !\A_SPW_TOP|tx_data|rd_ptr [0] $ (((!\A_SPW_TOP|tx_data|f_empty~q ) # (!\A_SPW_TOP|SPW|TX|ready_tx_data~q )))
.dataa(gnd),
.datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
.datac(!\A_SPW_TOP|tx_data|f_empty~q ),
.datad(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|rd_ptr~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~1 .lut_mask = 64'h333C333C333C333C;
defparam \A_SPW_TOP|tx_data|rd_ptr~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N29
dffeas \A_SPW_TOP|tx_data|rd_ptr[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|rd_ptr [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~2_combout = ( \A_SPW_TOP|tx_data|rd_ptr [0] & ( !\A_SPW_TOP|tx_data|rd_ptr [1] $ (((!\A_SPW_TOP|tx_data|f_empty~q ) # (!\A_SPW_TOP|SPW|TX|ready_tx_data~q ))) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [0] & ( \A_SPW_TOP|tx_data|rd_ptr
// [1] ) )
.dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
.datab(!\A_SPW_TOP|tx_data|f_empty~q ),
.datac(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|rd_ptr [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|rd_ptr~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~2 .lut_mask = 64'h5555555556565656;
defparam \A_SPW_TOP|tx_data|rd_ptr~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N26
dffeas \A_SPW_TOP|tx_data|rd_ptr[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|rd_ptr [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~3_combout = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( (!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|f_empty~q ) # ((!\A_SPW_TOP|tx_data|rd_ptr [0]) # (!\A_SPW_TOP|SPW|TX|ready_tx_data~q ))) ) ) # (
// !\A_SPW_TOP|tx_data|rd_ptr [2] & ( (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|f_empty~q & (\A_SPW_TOP|tx_data|rd_ptr [0] & \A_SPW_TOP|SPW|TX|ready_tx_data~q ))) ) )
.dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
.datab(!\A_SPW_TOP|tx_data|f_empty~q ),
.datac(!\A_SPW_TOP|tx_data|rd_ptr [0]),
.datad(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|rd_ptr [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|rd_ptr~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~3 .lut_mask = 64'h00010001FFFEFFFE;
defparam \A_SPW_TOP|tx_data|rd_ptr~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N1
dffeas \A_SPW_TOP|tx_data|rd_ptr[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~4_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|rd_ptr [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~4_combout = ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|SPW|TX|ready_tx_data~q & ( !\A_SPW_TOP|tx_data|rd_ptr [3] $ (((!\A_SPW_TOP|tx_data|rd_ptr [1]) # ((!\A_SPW_TOP|tx_data|f_empty~q ) # (!\A_SPW_TOP|tx_data|rd_ptr [0]))))
// ) ) ) # ( !\A_SPW_TOP|tx_data|rd_ptr [2] & ( \A_SPW_TOP|SPW|TX|ready_tx_data~q & ( \A_SPW_TOP|tx_data|rd_ptr [3] ) ) ) # ( \A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q & ( \A_SPW_TOP|tx_data|rd_ptr [3] ) ) ) # (
// !\A_SPW_TOP|tx_data|rd_ptr [2] & ( !\A_SPW_TOP|SPW|TX|ready_tx_data~q & ( \A_SPW_TOP|tx_data|rd_ptr [3] ) ) )
.dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
.datab(!\A_SPW_TOP|tx_data|f_empty~q ),
.datac(!\A_SPW_TOP|tx_data|rd_ptr [3]),
.datad(!\A_SPW_TOP|tx_data|rd_ptr [0]),
.datae(!\A_SPW_TOP|tx_data|rd_ptr [2]),
.dataf(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|rd_ptr~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~4 .lut_mask = 64'h0F0F0F0F0F0F0F1E;
defparam \A_SPW_TOP|tx_data|rd_ptr~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|Add3~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|Add3~0_combout = (\A_SPW_TOP|tx_data|rd_ptr [1] & (\A_SPW_TOP|tx_data|rd_ptr [0] & (\A_SPW_TOP|tx_data|rd_ptr [2] & \A_SPW_TOP|tx_data|rd_ptr [3])))
.dataa(!\A_SPW_TOP|tx_data|rd_ptr [1]),
.datab(!\A_SPW_TOP|tx_data|rd_ptr [0]),
.datac(!\A_SPW_TOP|tx_data|rd_ptr [2]),
.datad(!\A_SPW_TOP|tx_data|rd_ptr [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|Add3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|Add3~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|Add3~0 .lut_mask = 64'h0001000100010001;
defparam \A_SPW_TOP|tx_data|Add3~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N32
dffeas \A_SPW_TOP|tx_data|rd_ptr[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~5_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|rd_ptr [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~5_combout = !\A_SPW_TOP|tx_data|rd_ptr [4] $ (((!\A_SPW_TOP|tx_data|Add3~0_combout ) # ((!\A_SPW_TOP|tx_data|f_empty~q ) # (!\A_SPW_TOP|SPW|TX|ready_tx_data~q ))))
.dataa(!\A_SPW_TOP|tx_data|Add3~0_combout ),
.datab(!\A_SPW_TOP|tx_data|f_empty~q ),
.datac(!\A_SPW_TOP|tx_data|rd_ptr [4]),
.datad(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|rd_ptr~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~5 .lut_mask = 64'h0F1E0F1E0F1E0F1E;
defparam \A_SPW_TOP|tx_data|rd_ptr~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N8
dffeas \A_SPW_TOP|tx_data|rd_ptr[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|rd_ptr [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|rd_ptr[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|rd_ptr~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|rd_ptr~0_combout = ( \A_SPW_TOP|tx_data|rd_ptr [5] & ( (!\A_SPW_TOP|tx_data|Add3~0_combout ) # ((!\A_SPW_TOP|tx_data|f_empty~q ) # ((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # (!\A_SPW_TOP|tx_data|rd_ptr [4]))) ) ) # (
// !\A_SPW_TOP|tx_data|rd_ptr [5] & ( (\A_SPW_TOP|tx_data|Add3~0_combout & (\A_SPW_TOP|tx_data|f_empty~q & (\A_SPW_TOP|SPW|TX|ready_tx_data~q & \A_SPW_TOP|tx_data|rd_ptr [4]))) ) )
.dataa(!\A_SPW_TOP|tx_data|Add3~0_combout ),
.datab(!\A_SPW_TOP|tx_data|f_empty~q ),
.datac(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datad(!\A_SPW_TOP|tx_data|rd_ptr [4]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|rd_ptr [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|rd_ptr~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|rd_ptr~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|rd_ptr~0 .lut_mask = 64'h00010001FFFEFFFE;
defparam \A_SPW_TOP|tx_data|rd_ptr~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y13_N33
cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
// \~QUARTUS_CREATED_GND~I_combout = GND
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\~QUARTUS_CREATED_GND~I_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N28
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y16_N52
dffeas \u0|write_data_fifo_tx|data_out[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[1] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout = (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [2])
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N49
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y16_N19
dffeas \u0|write_data_fifo_tx|data_out[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[2] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [3] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N52
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y16_N9
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[3]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[3]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|data_out[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[3]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y16_N11
dffeas \u0|write_data_fifo_tx|data_out[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|data_out[3]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[3] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [4] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N31
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y16_N24
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[4]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[4]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|data_out[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[4]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y16_N26
dffeas \u0|write_data_fifo_tx|data_out[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|data_out[4]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[4] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [5] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N34
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y16_N57
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[5]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[5]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|data_out[5]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[5]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[5]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y16_N59
dffeas \u0|write_data_fifo_tx|data_out[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|data_out[5]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[5] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [6] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N13
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y16_N4
dffeas \u0|write_data_fifo_tx|data_out[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[6] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [7] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y16_N30
cyclonev_lcell_comb \u0|write_data_fifo_tx|data_out[7]~feeder (
// Equation(s):
// \u0|write_data_fifo_tx|data_out[7]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|data_out[7]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[7]~feeder .extended_lut = "off";
defparam \u0|write_data_fifo_tx|data_out[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|write_data_fifo_tx|data_out[7]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y16_N32
dffeas \u0|write_data_fifo_tx|data_out[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|data_out[7]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|write_data_fifo_tx|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|write_data_fifo_tx|data_out [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|write_data_fifo_tx|data_out[7] .is_wysiwyg = "true";
defparam \u0|write_data_fifo_tx|data_out[7] .power_up = "low";
// synopsys translate_on
// Location: M10K_X20_Y11_N0
cyclonev_ram_block \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 (
.portawe(\A_SPW_TOP|tx_data|comb~0_combout ),
.portare(vcc),
.portaaddrstall(gnd),
.portbwe(gnd),
.portbre(vcc),
.portbaddrstall(!\A_SPW_TOP|tx_data|block_read~_wirecell_combout ),
.clk0(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.clk1(gnd),
.ena0(vcc),
.ena1(vcc),
.ena2(vcc),
.ena3(vcc),
.clr0(gnd),
.clr1(gnd),
.nerror(vcc),
.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\u0|write_data_fifo_tx|data_out [8],\u0|write_data_fifo_tx|data_out [7],\u0|write_data_fifo_tx|data_out [6],\u0|write_data_fifo_tx|data_out [5],\u0|write_data_fifo_tx|data_out [4],
\u0|write_data_fifo_tx|data_out [3],\u0|write_data_fifo_tx|data_out [2],\u0|write_data_fifo_tx|data_out [1],\u0|write_data_fifo_tx|data_out [0]}),
.portaaddr({\A_SPW_TOP|tx_data|wr_ptr [5],\A_SPW_TOP|tx_data|wr_ptr [4],\A_SPW_TOP|tx_data|wr_ptr [3],\A_SPW_TOP|tx_data|wr_ptr [2],\A_SPW_TOP|tx_data|wr_ptr [1],\A_SPW_TOP|tx_data|wr_ptr [0]}),
.portabyteenamasks(1'b1),
.portbdatain(40'b0000000000000000000000000000000000000000),
.portbaddr({\A_SPW_TOP|tx_data|rd_ptr~0_combout ,\A_SPW_TOP|tx_data|rd_ptr~5_combout ,\A_SPW_TOP|tx_data|rd_ptr~4_combout ,\A_SPW_TOP|tx_data|rd_ptr~3_combout ,\A_SPW_TOP|tx_data|rd_ptr~2_combout ,\A_SPW_TOP|tx_data|rd_ptr~1_combout }),
.portbbyteenamasks(1'b1),
.devclrn(devclrn),
.devpor(devpor),
.portadataout(),
.portbdataout(\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ),
.eccstatus(),
.dftout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .logical_ram_name = "spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|altsyncram:mem_rtl_0|altsyncram_pfo1:auto_generated|ALTSYNCRAM";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "old";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .operation_mode = "dual_port";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_address_width = 6;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_width = 40;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_last_address = 63;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_clear = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_width = 6;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_width = 40;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_last_address = 63;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_logical_ram_width = 9;
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0";
defparam \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0 .ram_block_type = "M20K";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~9 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~9_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 & ( (\A_SPW_TOP|tx_data|mem~9_q ) # (\A_SPW_TOP|tx_data|mem~0_q ) ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 & (
// (!\A_SPW_TOP|tx_data|mem~0_q & \A_SPW_TOP|tx_data|mem~9_q ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|tx_data|mem~9_q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~9 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~9 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \A_SPW_TOP|tx_data|data_out~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N14
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y11_N43
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N26
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|wr_ptr [1]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y11_N5
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|comb~0_combout ),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder_combout = ( \A_SPW_TOP|tx_data|wr_ptr [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N52
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|mem~10_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [0] & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [1] & ( (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [2] & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [4] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass
// [3]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [0] & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [1] & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [2] & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [4] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [3]))) ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [2]),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [4]),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [3]),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [0]),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem~10 .lut_mask = 64'h0000C00C00003003;
defparam \A_SPW_TOP|tx_data|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[12] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[12] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder_combout = ( \u0|write_data_fifo_tx|data_out [8] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|write_data_fifo_tx|data_out [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N25
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [21]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y11_N5
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N55
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|wr_ptr [2]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder_combout = ( \A_SPW_TOP|tx_data|wr_ptr [4] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|wr_ptr [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N1
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~4_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[8] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y11_N38
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[10] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|rd_ptr~5_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|tx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [10]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[10] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N23
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|wr_ptr [3]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|mem~11_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [10] & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [7] & ( (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [9] & (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [8] & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [6]
// $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [5])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [10] & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [7] & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [9] & (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [8] &
// (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [6] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [5])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [10] & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [7] & ( (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [9] &
// (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [8] & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [6] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [5])))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [10] & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [7] & (
// (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [9] & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [8] & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [6] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [5])))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [6]),
.datab(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [5]),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [9]),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [8]),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [10]),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem~11 .lut_mask = 64'h9000090000900009;
defparam \A_SPW_TOP|tx_data|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N20
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[11] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|wr_ptr [5]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~10 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~10_combout = ( \A_SPW_TOP|tx_data|mem~11_combout & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( (!\A_SPW_TOP|tx_data|mem~10_combout & (\A_SPW_TOP|tx_data|data_out~9_combout )) # (\A_SPW_TOP|tx_data|mem~10_combout &
// ((!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & (\A_SPW_TOP|tx_data|data_out~9_combout )) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ((\A_SPW_TOP|tx_data|mem_rtl_0_bypass [21]))))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem~11_combout & (
// \A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( \A_SPW_TOP|tx_data|data_out~9_combout ) ) ) # ( \A_SPW_TOP|tx_data|mem~11_combout & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( (!\A_SPW_TOP|tx_data|mem~10_combout &
// (\A_SPW_TOP|tx_data|data_out~9_combout )) # (\A_SPW_TOP|tx_data|mem~10_combout & ((!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ((\A_SPW_TOP|tx_data|mem_rtl_0_bypass [21]))) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] &
// (\A_SPW_TOP|tx_data|data_out~9_combout )))) ) ) ) # ( !\A_SPW_TOP|tx_data|mem~11_combout & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( \A_SPW_TOP|tx_data|data_out~9_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out~9_combout ),
.datab(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [21]),
.datae(!\A_SPW_TOP|tx_data|mem~11_combout ),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~10 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~10 .lut_mask = 64'h5555457555555457;
defparam \A_SPW_TOP|tx_data|data_out~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~2 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~2_combout = (!\A_SPW_TOP|tx_data|f_empty~q ) # ((!\A_SPW_TOP|SPW|TX|ready_tx_data~q ) # (\A_SPW_TOP|tx_data|block_read~q ))
.dataa(gnd),
.datab(!\A_SPW_TOP|tx_data|f_empty~q ),
.datac(!\A_SPW_TOP|tx_data|block_read~q ),
.datad(!\A_SPW_TOP|SPW|TX|ready_tx_data~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~2 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~2 .lut_mask = 64'hFFCFFFCFFFCFFFCF;
defparam \A_SPW_TOP|tx_data|data_out~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N56
dffeas \A_SPW_TOP|tx_data|data_out[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~10_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~11_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~11 .lut_mask = 64'h0000000007070707;
defparam \A_SPW_TOP|SPW|TX|last_type~11 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal5~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal5~4_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2])) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Equal5~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal5~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal5~4 .lut_mask = 64'h0000000040404040;
defparam \A_SPW_TOP|SPW|TX|Equal5~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout = ( \A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( !\A_SPW_TOP|SPW|TX|last_type~11_combout ) ) # ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( (!\A_SPW_TOP|tx_data|data_out [8] &
// !\A_SPW_TOP|SPW|TX|Equal5~4_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~4_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1 .lut_mask = 64'hAA00AA00F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer~8_combout = ( !\A_SPW_TOP|SPW|TX|Selector4~2_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout & (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout &
// (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] $ (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]
// $ (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))))) ) ) # ( \A_SPW_TOP|SPW|TX|Selector4~2_combout & ( ((!\A_SPW_TOP|SPW|TX|last_type~10_combout & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] $ ((!\A_SPW_TOP|SPW|TX|global_counter_transfer
// [0]))))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ),
.datag(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~8 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~8 .lut_mask = 64'h104030C033CC30C0;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y11_N14
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|global_counter_transfer~8_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal5~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal5~0_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal5~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal5~0 .lut_mask = 64'h0202020200000000;
defparam \A_SPW_TOP|SPW|TX|Equal5~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|hold_fct~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|hold_fct~0_combout = ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & !\A_SPW_TOP|SPW|TX|Equal5~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (\A_SPW_TOP|SPW|TX|hold_fct~q &
// !\A_SPW_TOP|SPW|TX|Selector4~2_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_fct~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|hold_fct~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_fct~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|hold_fct~0 .lut_mask = 64'h50505050F000F000;
defparam \A_SPW_TOP|SPW|TX|hold_fct~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N20
dffeas \A_SPW_TOP|SPW|TX|hold_fct (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|hold_fct~0_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|hold_fct~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|hold_fct .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always7~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always7~0_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( (!\A_SPW_TOP|SPW|TX|hold_data~q & (!\A_SPW_TOP|SPW|TX|hold_fct~q & \u0|timecode_tx_enable|data_out~q )) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datab(!\A_SPW_TOP|SPW|TX|hold_fct~q ),
.datac(gnd),
.datad(!\u0|timecode_tx_enable|data_out~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always7~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always7~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always7~0 .lut_mask = 64'h0088008800000000;
defparam \A_SPW_TOP|SPW|TX|always7~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~14_combout = ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|always7~0_combout & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout & (\A_SPW_TOP|tx_data|write_tx~q &
// \A_SPW_TOP|SPW|TX|always7~3_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|tx_data|write_tx~q ),
.datad(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~14 .lut_mask = 64'h0000000000080000;
defparam \A_SPW_TOP|SPW|TX|last_type~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|hold_data~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|hold_data~0_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & ( (!\A_SPW_TOP|SPW|TX|last_type~14_combout & (\A_SPW_TOP|SPW|TX|hold_data~q )) # (\A_SPW_TOP|SPW|TX|last_type~14_combout &
// ((!\A_SPW_TOP|SPW|TX|last_type~21_combout ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|hold_data~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_data~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|hold_data~0 .lut_mask = 64'h000000005F505F50;
defparam \A_SPW_TOP|SPW|TX|hold_data~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N2
dffeas \A_SPW_TOP|SPW|TX|hold_data (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|hold_data~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|hold_data~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_data .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|hold_data .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always7~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always7~1_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( (!\A_SPW_TOP|SPW|TX|hold_data~q & ((!\A_SPW_TOP|SPW|TX|fct_flag [0]) # ((!\A_SPW_TOP|SPW|TX|fct_flag [2]) # (!\A_SPW_TOP|SPW|TX|fct_flag [1])))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datab(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datac(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
.datad(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always7~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always7~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always7~1 .lut_mask = 64'hAAA8AAA800000000;
defparam \A_SPW_TOP|SPW|TX|always7~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout = ( \A_SPW_TOP|SPW|TX|always7~5_combout & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ((!\A_SPW_TOP|SPW|TX|always7~1_combout ) #
// (!\A_SPW_TOP|SPW|TX|Selector5~1_combout )))) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~5_combout & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & !\A_SPW_TOP|SPW|TX|Selector5~1_combout )) ) )
.dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|always7~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6 .lut_mask = 64'h8800880088808880;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y14_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always8~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|always8~1_combout = (\A_SPW_TOP|SPW|RX|always8~0_combout & \A_SPW_TOP|SPW|RX|ready_control_p_r~q )
.dataa(!\A_SPW_TOP|SPW|RX|always8~0_combout ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|always8~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|always8~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|always8~1 .lut_mask = 64'h0505050505050505;
defparam \A_SPW_TOP|SPW|RX|always8~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y14_N35
dffeas \A_SPW_TOP|SPW|RX|rx_got_fct (
.clk(!\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|always8~1_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_got_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_got_fct .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always7~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always7~2_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( (\A_SPW_TOP|tx_data|write_tx~q & !\A_SPW_TOP|SPW|TX|hold_fct~q ) ) )
.dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|hold_fct~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always7~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always7~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always7~2 .lut_mask = 64'h5050505000000000;
defparam \A_SPW_TOP|SPW|TX|always7~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|hold_data~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|hold_data~1_combout = ( \A_SPW_TOP|SPW|TX|always7~2_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|always7~0_combout & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout & (!\A_SPW_TOP|SPW|TX|always7~1_combout &
// !\A_SPW_TOP|SPW|TX|last_type~21_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~2_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|hold_data~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_data~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|hold_data~1 .lut_mask = 64'h0000000000008000;
defparam \A_SPW_TOP|SPW|TX|hold_data~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|block_sum~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|block_sum~0_combout = ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( \A_SPW_TOP|SPW|RX|rx_got_fct~q ) ) # ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( \A_SPW_TOP|SPW|RX|rx_got_fct~q & ( (((\A_SPW_TOP|SPW|TX|enable_time_code~0_combout )
// # (\A_SPW_TOP|SPW|TX|block_sum~q )) # (\A_SPW_TOP|SPW|TX|hold_data~1_combout )) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( !\A_SPW_TOP|SPW|RX|rx_got_fct~q & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout
// & (!\A_SPW_TOP|SPW|TX|hold_data~1_combout & (\A_SPW_TOP|SPW|TX|block_sum~q & !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|hold_data~1_combout ),
.datac(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.datad(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|block_sum~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|block_sum~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|block_sum~0 .lut_mask = 64'h080000007FFFFFFF;
defparam \A_SPW_TOP|SPW|TX|block_sum~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y10_N29
dffeas \A_SPW_TOP|SPW|TX|block_sum (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|block_sum~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|block_sum~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|block_sum .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|block_sum .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~11_combout = ( \A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( \A_SPW_TOP|SPW|RX|rx_got_fct~q & ( (!\A_SPW_TOP|SPW|TX|block_sum~q & !\A_SPW_TOP|SPW|TX|fct_counter_receive [0]) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( \A_SPW_TOP|SPW|RX|rx_got_fct~q & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive [0] & ((!\A_SPW_TOP|SPW|TX|block_sum~q ) # ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout &
// \A_SPW_TOP|SPW|TX|last_type~21_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( !\A_SPW_TOP|SPW|RX|rx_got_fct~q & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (\A_SPW_TOP|SPW|TX|last_type~21_combout &
// !\A_SPW_TOP|SPW|TX|fct_counter_receive [0])) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [0]),
.datae(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.dataf(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~11 .lut_mask = 64'h03000000AB00AA00;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout = !\A_SPW_TOP|SPW|TX|fct_counter_receive [1] $ (!\A_SPW_TOP|SPW|TX|fct_counter_receive [0])
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [1]),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~9 .lut_mask = 64'h0FF00FF00FF00FF0;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~10_combout = ( \A_SPW_TOP|SPW|TX|block_sum~q & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout &
// \A_SPW_TOP|SPW|TX|last_type~21_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|block_sum~q & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout & ( ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout &
// \A_SPW_TOP|SPW|TX|last_type~21_combout ))) # (\A_SPW_TOP|SPW|RX|rx_got_fct~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datae(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~10 .lut_mask = 64'h3373005000000000;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y10_N23
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|fct_counter_receive~10_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_counter_receive [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan2~1_combout = ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [2] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive [0] & !\A_SPW_TOP|SPW|TX|fct_counter_receive [1]) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [0]),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan2~1 .lut_mask = 64'hC0C0C0C000000000;
defparam \A_SPW_TOP|SPW|TX|LessThan2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout = ( !\A_SPW_TOP|SPW|TX|Selector4~2_combout & ( (\A_SPW_TOP|SPW|TX|last_type~21_combout & (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout )) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datad(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0 .lut_mask = 64'h3000300000000000;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (\A_SPW_TOP|SPW|RX|rx_got_fct~q & ((!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]) # (\A_SPW_TOP|SPW|TX|fct_counter_receive [5]))) ) ) # (
// !\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & \A_SPW_TOP|SPW|RX|rx_got_fct~q ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
.datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.datac(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~13 .lut_mask = 64'h030303030D0D0D0D;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~3_combout = ( \A_SPW_TOP|SPW|TX|block_sum~q & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & \A_SPW_TOP|SPW|TX|fct_counter_receive [4]) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|block_sum~q & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & (\A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout & ((!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]) #
// (\A_SPW_TOP|SPW|TX|LessThan2~1_combout )))) # (\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & (((\A_SPW_TOP|SPW|TX|fct_counter_receive [4])))) ) ) ) # ( \A_SPW_TOP|SPW|TX|block_sum~q & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & (
// (\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & (!\A_SPW_TOP|SPW|TX|LessThan2~1_combout $ (!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|block_sum~q & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & (
// (!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & (\A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout & ((\A_SPW_TOP|SPW|TX|fct_counter_receive [4])))) # (\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & ((!\A_SPW_TOP|SPW|TX|LessThan2~1_combout
// $ (!\A_SPW_TOP|SPW|TX|fct_counter_receive [4])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout ),
.datac(!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.datae(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~3 .lut_mask = 64'h0572055022570055;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout = (!\A_SPW_TOP|SPW|TX|block_sum~q & \A_SPW_TOP|SPW|RX|rx_got_fct~q )
.dataa(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~12 .lut_mask = 64'h2222222222222222;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout = ( \A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout ) ) # ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (
// \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout & ( ((\A_SPW_TOP|SPW|TX|Selector4~2_combout ) # (\A_SPW_TOP|SPW|TX|Selector5~3_combout )) # (\A_SPW_TOP|SPW|TX|last_type~14_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (
// !\A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout & ( (\A_SPW_TOP|SPW|TX|last_type~14_combout & (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & \A_SPW_TOP|SPW|TX|last_type~21_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datae(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2 .lut_mask = 64'h004000007F7FFFFF;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y10_N11
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|fct_counter_receive~3_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [5] & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~5_combout = ( \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout & ( \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & ( !\A_SPW_TOP|SPW|TX|LessThan2~1_combout $ (!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]) ) )
// ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout & ( \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & ( !\A_SPW_TOP|SPW|TX|LessThan2~1_combout $ (!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]) ) ) ) # (
// \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & ( (\A_SPW_TOP|SPW|RX|rx_got_fct~q & (!\A_SPW_TOP|SPW|TX|block_sum~q & (!\A_SPW_TOP|SPW|TX|LessThan2~1_combout $
// (\A_SPW_TOP|SPW|TX|fct_counter_receive [3])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & ( (\A_SPW_TOP|SPW|RX|rx_got_fct~q & (!\A_SPW_TOP|SPW|TX|block_sum~q &
// !\A_SPW_TOP|SPW|TX|fct_counter_receive [3])) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
.datae(!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~5 .lut_mask = 64'h3000201055AA55AA;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y10_N41
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|fct_counter_receive~5_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~1_combout = ( \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & (((!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout
// & \A_SPW_TOP|SPW|TX|fct_counter_receive [3])))) # (\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & (((!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]) # (\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout )) # (\A_SPW_TOP|SPW|TX|LessThan2~1_combout ))) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout & ( \A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive [5] & \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ) ) ) ) # (
// \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [5] $ (((!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ) # ((!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ) #
// (\A_SPW_TOP|SPW|TX|fct_counter_receive [3])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( (\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout & (!\A_SPW_TOP|SPW|TX|fct_counter_receive
// [5] $ (((!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ) # (\A_SPW_TOP|SPW|TX|fct_counter_receive [3]))))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|LessThan2~1_combout ),
.datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
.datae(!\A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~1 .lut_mask = 64'h06033633030333D3;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y10_N44
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|fct_counter_receive~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [4] & ( (!\A_SPW_TOP|SPW|TX|block_sum~q & (\A_SPW_TOP|SPW|RX|rx_got_fct~q & \A_SPW_TOP|SPW|TX|fct_counter_receive [5])) ) )
.dataa(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14 .lut_mask = 64'h0000000002020202;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout = ( \A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout ) ) # ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (
// \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout & ( ((\A_SPW_TOP|SPW|TX|Selector4~2_combout ) # (\A_SPW_TOP|SPW|TX|Selector5~3_combout )) # (\A_SPW_TOP|SPW|TX|last_type~14_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (
// !\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout & ( (\A_SPW_TOP|SPW|TX|last_type~14_combout & (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & (\A_SPW_TOP|SPW|TX|last_type~21_combout & !\A_SPW_TOP|SPW|TX|Selector4~2_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datae(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8 .lut_mask = 64'h0400000077FFFFFF;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y10_N59
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|fct_counter_receive~11_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_counter_receive [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout = ( \A_SPW_TOP|SPW|TX|fct_counter_receive [2] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive [0] & !\A_SPW_TOP|SPW|TX|fct_counter_receive [1]) ) ) # ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [2] & (
// (\A_SPW_TOP|SPW|TX|fct_counter_receive [1]) # (\A_SPW_TOP|SPW|TX|fct_counter_receive [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [0]),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [1]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~6 .lut_mask = 64'h0FFF0FFFF000F000;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|fct_counter_receive~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|fct_counter_receive~7_combout = ( \A_SPW_TOP|SPW|TX|block_sum~q & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (\A_SPW_TOP|SPW|TX|last_type~21_combout &
// !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|block_sum~q & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout & ( ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (\A_SPW_TOP|SPW|TX|last_type~21_combout &
// !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ))) # (\A_SPW_TOP|SPW|RX|rx_got_fct~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.datab(!\A_SPW_TOP|SPW|RX|rx_got_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datad(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|block_sum~q ),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|fct_counter_receive~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~7 .lut_mask = 64'h3733050000000000;
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y10_N20
dffeas \A_SPW_TOP|SPW|TX|fct_counter_receive[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|fct_counter_receive~7_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|fct_counter_receive [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|fct_counter_receive[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y10_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|LessThan2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|LessThan2~0_combout = ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [0] & ( !\A_SPW_TOP|SPW|TX|fct_counter_receive [3] & ( (!\A_SPW_TOP|SPW|TX|fct_counter_receive [2] & (!\A_SPW_TOP|SPW|TX|fct_counter_receive [5] &
// (!\A_SPW_TOP|SPW|TX|fct_counter_receive [4] & !\A_SPW_TOP|SPW|TX|fct_counter_receive [1]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_counter_receive [2]),
.datab(!\A_SPW_TOP|SPW|TX|fct_counter_receive [5]),
.datac(!\A_SPW_TOP|SPW|TX|fct_counter_receive [4]),
.datad(!\A_SPW_TOP|SPW|TX|fct_counter_receive [1]),
.datae(!\A_SPW_TOP|SPW|TX|fct_counter_receive [0]),
.dataf(!\A_SPW_TOP|SPW|TX|fct_counter_receive [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|LessThan2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|LessThan2~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|SPW|TX|LessThan2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y10_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector4~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector4~1_combout = ( \A_SPW_TOP|SPW|TX|hold_null~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ) ) # ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ( (!\A_SPW_TOP|SPW|FSM|send_fct_tx~q )
// # ((\A_SPW_TOP|SPW|TX|fct_flag [0] & (\A_SPW_TOP|SPW|TX|fct_flag [1] & \A_SPW_TOP|SPW|TX|fct_flag [2]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|fct_flag [0]),
.datab(!\A_SPW_TOP|SPW|TX|fct_flag [1]),
.datac(!\A_SPW_TOP|SPW|TX|fct_flag [2]),
.datad(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.datae(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector4~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector4~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector4~1 .lut_mask = 64'h00000000FF01FFFF;
defparam \A_SPW_TOP|SPW|TX|Selector4~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector4~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector4~2_combout = ( \A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|always7~2_combout & ( (\A_SPW_TOP|SPW|TX|Selector4~1_combout ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|always7~2_combout & ( (((\A_SPW_TOP|SPW|TX|LessThan2~0_combout & \A_SPW_TOP|SPW|TX|Selector5~1_combout )) # (\A_SPW_TOP|SPW|TX|Selector4~1_combout )) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q
// ) ) ) ) # ( \A_SPW_TOP|SPW|TX|always7~1_combout & ( !\A_SPW_TOP|SPW|TX|always7~2_combout & ( (\A_SPW_TOP|SPW|TX|Selector4~1_combout ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & (
// !\A_SPW_TOP|SPW|TX|always7~2_combout & ( ((\A_SPW_TOP|SPW|TX|Selector5~1_combout ) # (\A_SPW_TOP|SPW|TX|Selector4~1_combout )) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~1_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|always7~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector4~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector4~2 .lut_mask = 64'h5FFF5F5F5F7F5F5F;
defparam \A_SPW_TOP|SPW|TX|Selector4~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Add4~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Add4~1_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] $ (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (
// \A_SPW_TOP|SPW|TX|global_counter_transfer [2] ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Add4~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Add4~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Add4~1 .lut_mask = 64'h5555555555AA55AA;
defparam \A_SPW_TOP|SPW|TX|Add4~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer~4_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & ( \A_SPW_TOP|SPW|TX|Add4~1_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((!\A_SPW_TOP|SPW|TX|Selector5~3_combout ) #
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout )))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (((!\A_SPW_TOP|SPW|TX|last_type~10_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout & (
// \A_SPW_TOP|SPW|TX|Add4~1_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|last_type~10_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Add4~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~4 .lut_mask = 64'h0000000050FAD8FA;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y11_N53
dffeas \A_SPW_TOP|SPW|TX|global_counter_transfer[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|global_counter_transfer~4_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|first_time~feeder (
// Equation(s):
// \A_SPW_TOP|SPW|TX|first_time~feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|first_time~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|first_time~feeder .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|first_time~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|SPW|TX|first_time~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y11_N29
dffeas \A_SPW_TOP|SPW|TX|first_time (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|first_time~feeder_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|first_time~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|first_time .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|first_time .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~10_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] &
// \A_SPW_TOP|SPW|TX|first_time~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datad(!\A_SPW_TOP|SPW|TX|first_time~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~10 .lut_mask = 64'h0000000000100010;
defparam \A_SPW_TOP|SPW|TX|last_type~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|hold_null~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|hold_null~0_combout = ( \A_SPW_TOP|SPW|TX|hold_null~q & ( (!\A_SPW_TOP|SPW|TX|last_type~10_combout ) # (!\A_SPW_TOP|SPW|TX|Selector4~2_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( (!\A_SPW_TOP|SPW|TX|last_type~10_combout &
// \A_SPW_TOP|SPW|TX|Selector4~2_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|hold_null~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_null~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|hold_null~0 .lut_mask = 64'h0A0A0A0AFAFAFAFA;
defparam \A_SPW_TOP|SPW|TX|hold_null~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N35
dffeas \A_SPW_TOP|SPW|TX|hold_null (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|hold_null~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|hold_null~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|hold_null .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|hold_null .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|FSM|WideOr0 (
// Equation(s):
// \A_SPW_TOP|SPW|FSM|WideOr0~combout = (!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q & \A_SPW_TOP|SPW|FSM|enable_tx~0_combout )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|FSM|enable_tx~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|FSM|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|WideOr0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|FSM|WideOr0 .lut_mask = 64'h00CC00CC00CC00CC;
defparam \A_SPW_TOP|SPW|FSM|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y12_N11
dffeas \A_SPW_TOP|SPW|FSM|send_null_tx (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|SPW|FSM|WideOr0~combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|FSM|send_null_tx .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|FSM|send_null_tx .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector0~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector0~0_combout = ( \A_SPW_TOP|SPW|FSM|send_null_tx~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ) # (\A_SPW_TOP|SPW|FSM|enable_tx~q ) ) ) # ( !\A_SPW_TOP|SPW|FSM|send_null_tx~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q )
// )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.datad(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector0~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector0~0 .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \A_SPW_TOP|SPW|TX|Selector0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y12_N1
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|Selector0~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector1~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector1~0_combout = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q & ( \A_SPW_TOP|SPW|FSM|send_null_tx~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & (((!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ) # (!\A_SPW_TOP|SPW|FSM|enable_tx~q )) #
// (\A_SPW_TOP|SPW|TX|hold_null~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q & ( \A_SPW_TOP|SPW|FSM|send_null_tx~q & ( (\A_SPW_TOP|SPW|FSM|enable_tx~q ) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) ) ) # (
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q & ( !\A_SPW_TOP|SPW|FSM|send_null_tx~q & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q & ( !\A_SPW_TOP|SPW|FSM|send_null_tx~q & (
// \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.datab(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datad(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector1~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector1~0 .lut_mask = 64'h0F0F0F0F0FFF0F0D;
defparam \A_SPW_TOP|SPW|TX|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y12_N5
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|Selector1~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector2~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector2~0_combout = ( !\A_SPW_TOP|SPW|TX|hold_null~q & ( \A_SPW_TOP|SPW|FSM|send_null_tx~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & (\A_SPW_TOP|SPW|FSM|send_fct_tx~q & \A_SPW_TOP|SPW|FSM|enable_tx~q )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datab(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.datae(!\A_SPW_TOP|SPW|TX|hold_null~q ),
.dataf(!\A_SPW_TOP|SPW|FSM|send_null_tx~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector2~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector2~0 .lut_mask = 64'h0000000000110000;
defparam \A_SPW_TOP|SPW|TX|Selector2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Selector2~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Selector2~1_combout = ( \A_SPW_TOP|SPW|FSM|send_fct_tx~q & ( ((\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & ((\A_SPW_TOP|SPW|TX|LessThan2~0_combout ) # (\A_SPW_TOP|SPW|TX|always7~4_combout )))) #
// (\A_SPW_TOP|SPW|TX|Selector2~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|FSM|send_fct_tx~q & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ) # (\A_SPW_TOP|SPW|TX|Selector2~0_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector2~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|always7~4_combout ),
.datad(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|send_fct_tx~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Selector2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Selector2~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Selector2~1 .lut_mask = 64'h7777577777775777;
defparam \A_SPW_TOP|SPW|TX|Selector2~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y12_N41
dffeas \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|Selector2~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_sout~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_sout~0_combout = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_sout~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_sout~0 .lut_mask = 64'hC0C0C0C000000000;
defparam \A_SPW_TOP|SPW|TX|tx_sout~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [3] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N40
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N12
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[3]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[3]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[3]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter
// [0] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y18_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout
// & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[82] .lut_mask = 64'h30FF30FF30303030;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [82] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [82] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [82]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h3131313120202020;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y20_N16
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[88] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]
// & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[88] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[87] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) #
// ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[87] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [87] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_014|src_data [88])))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [87] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h202020202F202F20;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [86] = (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])))) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [0] & (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])) # (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])))
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[86] .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|cmd_mux_014|src_data [86]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|cmd_mux_014|src_data [86])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0101454501014545;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|cmd_mux_014|src_data [86])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h5454101054541010;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y17_N34
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y20_N46
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [80] = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )
// ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[80] .lut_mask = 64'h5F5F0F0F55550000;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [80]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_014|src_data [88] & !\u0|mm_interconnect_0|cmd_mux_014|src_data [87]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h88888888F000F000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_014|src_data [80]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [80]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & \u0|mm_interconnect_0|cmd_mux_014|src_data [86]) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h1111111100330033;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// !\u0|mm_interconnect_0|cmd_mux_014|src_data [86]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_data [86]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h3030303033003300;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]
// ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [79] = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )
// ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[79] .lut_mask = 64'h5F5F0F0F55550000;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout
// & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [1] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [79] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [79] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) )
// )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [79]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N34
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) )
// # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h1010101FF0F0F0FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] )
// + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout
// & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [1] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000555500FF55FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout
// & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout
// & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout
// & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h00F050F003F353F3;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N19
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] )
// + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [3] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6
// ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [3]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1B1B1B1B1BBB1BBB;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N3
cyclonev_lcell_comb \u0|timecode_tx_data|always0~0 (
// Equation(s):
// \u0|timecode_tx_data|always0~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|always0~0 .extended_lut = "off";
defparam \u0|timecode_tx_data|always0~0 .lut_mask = 64'h0080008000000000;
defparam \u0|timecode_tx_data|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N14
dffeas \u0|timecode_tx_data|data_out[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[3]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[3] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout = ( \A_SPW_TOP|SPW|TX|always7~3_combout & ( (\A_SPW_TOP|SPW|TX|last_type~11_combout & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & (!\A_SPW_TOP|SPW|TX|hold_data~q &
// \u0|timecode_tx_enable|data_out~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datac(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datad(!\u0|timecode_tx_enable|data_out~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 .lut_mask = 64'h0000000000100010;
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y11_N53
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [3]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [6] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N1
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N33
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[6]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[6]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[6]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[6]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[6]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N35
dffeas \u0|timecode_tx_data|data_out[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[6]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[6] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N20
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [6]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout = (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [7])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [7]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N4
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N42
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[7]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[7]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[7]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[7]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[7]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N44
dffeas \u0|timecode_tx_data|data_out[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[7]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[7] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N28
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [7]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout = (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [5])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N22
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y16_N59
dffeas \u0|timecode_tx_data|data_out[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [5]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[5] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N35
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [5]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [4] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N19
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N27
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[4]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[4]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[4]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N29
dffeas \u0|timecode_tx_data|data_out[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[4]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[4] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N32
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [4]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~2_combout = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx
// [5])) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7] $ (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5])) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [6]),
.datab(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [7]),
.datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [5]),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [4]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~2 .lut_mask = 64'h6969969669699696;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N55
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N3
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[0]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[0]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[0]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N5
dffeas \u0|timecode_tx_data|data_out[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[0] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N25
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [0]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout = (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [2])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N37
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N18
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[2]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[2]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[2]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N20
dffeas \u0|timecode_tx_data|data_out[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[2] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N38
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [2]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y16_N10
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y16_N36
cyclonev_lcell_comb \u0|timecode_tx_data|data_out[1]~feeder (
// Equation(s):
// \u0|timecode_tx_data|data_out[1]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|data_out[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[1]~feeder .extended_lut = "off";
defparam \u0|timecode_tx_data|data_out[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|timecode_tx_data|data_out[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y16_N38
dffeas \u0|timecode_tx_data|data_out[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|data_out[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|timecode_tx_data|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_data|data_out [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_data|data_out[1] .is_wysiwyg = "true";
defparam \u0|timecode_tx_data|data_out[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N41
dffeas \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [1]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] $ (!\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] $
// (\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]))) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] $ (!\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout $
// (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3]),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]),
.datad(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]),
.datae(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~3 .lut_mask = 64'h6996966969969669;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~15_combout = ( \A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|Equal5~4_combout & ( !\A_SPW_TOP|SPW|TX|always7~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|Equal5~4_combout & (
// (!\A_SPW_TOP|SPW|TX|always7~0_combout & (((!\A_SPW_TOP|tx_data|write_tx~q ) # (!\A_SPW_TOP|SPW|TX|always7~3_combout )) # (\A_SPW_TOP|SPW|TX|LessThan2~0_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|always7~1_combout & ( !\A_SPW_TOP|SPW|TX|Equal5~4_combout &
// ( !\A_SPW_TOP|SPW|TX|always7~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( !\A_SPW_TOP|SPW|TX|Equal5~4_combout & ( !\A_SPW_TOP|SPW|TX|always7~0_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|tx_data|write_tx~q ),
.datad(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Equal5~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~15 .lut_mask = 64'hAAAAAAAAAAA2AAAA;
defparam \A_SPW_TOP|SPW|TX|last_type~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~16 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~16_combout = ( \A_SPW_TOP|SPW|TX|last_type~11_combout & ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ) ) # ( !\A_SPW_TOP|SPW|TX|last_type~11_combout & ( (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q &
// (((!\A_SPW_TOP|SPW|TX|always7~3_combout ) # (!\u0|timecode_tx_enable|data_out~q )) # (\A_SPW_TOP|SPW|TX|hold_data~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datab(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datad(!\u0|timecode_tx_enable|data_out~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~16 .lut_mask = 64'h0F0D0F0D0F0F0F0F;
defparam \A_SPW_TOP|SPW|TX|last_type~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~17 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~17_combout = ( !\A_SPW_TOP|SPW|TX|Selector5~2_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~0_combout & ( (!\A_SPW_TOP|SPW|TX|last_type~14_combout & (((!\A_SPW_TOP|SPW|TX|last_type~16_combout )) #
// (\A_SPW_TOP|SPW|TX|last_type~15_combout ))) # (\A_SPW_TOP|SPW|TX|last_type~14_combout & (!\A_SPW_TOP|tx_data|data_out [8] & ((!\A_SPW_TOP|SPW|TX|last_type~16_combout ) # (\A_SPW_TOP|SPW|TX|last_type~15_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type~15_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~16_combout ),
.datad(!\A_SPW_TOP|tx_data|data_out [8]),
.datae(!\A_SPW_TOP|SPW|TX|Selector5~2_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~17 .lut_mask = 64'hF3A2000000000000;
defparam \A_SPW_TOP|SPW|TX|last_type~17 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~12_combout = ( \u0|timecode_tx_enable|data_out~q & ( \A_SPW_TOP|tx_data|write_tx~q & ( (!\A_SPW_TOP|SPW|TX|always7~1_combout & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout & (\A_SPW_TOP|SPW|TX|hold_data~q &
// \A_SPW_TOP|SPW|TX|always7~3_combout ))) ) ) ) # ( !\u0|timecode_tx_enable|data_out~q & ( \A_SPW_TOP|tx_data|write_tx~q & ( (!\A_SPW_TOP|SPW|TX|always7~1_combout & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout & \A_SPW_TOP|SPW|TX|always7~3_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datad(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datae(!\u0|timecode_tx_enable|data_out~q ),
.dataf(!\A_SPW_TOP|tx_data|write_tx~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~12 .lut_mask = 64'h0000000000880008;
defparam \A_SPW_TOP|SPW|TX|last_type~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~13_combout = ( \A_SPW_TOP|SPW|TX|Selector5~2_combout & ( \A_SPW_TOP|SPW|TX|Selector5~0_combout & ( !\A_SPW_TOP|SPW|TX|Equal5~0_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|Selector5~2_combout & (
// \A_SPW_TOP|SPW|TX|Selector5~0_combout & ( !\A_SPW_TOP|SPW|TX|Equal5~0_combout ) ) ) # ( \A_SPW_TOP|SPW|TX|Selector5~2_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~0_combout & ( !\A_SPW_TOP|SPW|TX|Equal5~0_combout ) ) ) # (
// !\A_SPW_TOP|SPW|TX|Selector5~2_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~0_combout & ( (\A_SPW_TOP|SPW|TX|last_type~12_combout & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & (!\A_SPW_TOP|SPW|TX|Equal5~0_combout & \A_SPW_TOP|tx_data|data_out [8]))) ) )
// )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~12_combout ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datad(!\A_SPW_TOP|tx_data|data_out [8]),
.datae(!\A_SPW_TOP|SPW|TX|Selector5~2_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~13 .lut_mask = 64'h0010F0F0F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|last_type~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~20 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~20_combout = ( \A_SPW_TOP|SPW|TX|last_type.TIMEC~q & ( \A_SPW_TOP|SPW|TX|enable_time_code~0_combout ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.TIMEC~q & ( \A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (
// (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (((!\A_SPW_TOP|SPW|TX|last_type~17_combout & !\A_SPW_TOP|SPW|TX|last_type~13_combout )))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (\A_SPW_TOP|SPW|TX|last_type~10_combout )) ) ) ) # (
// \A_SPW_TOP|SPW|TX|last_type.TIMEC~q & ( !\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (((\A_SPW_TOP|SPW|TX|last_type~13_combout ) # (\A_SPW_TOP|SPW|TX|last_type~17_combout )))) #
// (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|last_type~10_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type~17_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~13_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datae(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.dataf(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~20 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~20 .lut_mask = 64'h00003FAAC055FFFF;
defparam \A_SPW_TOP|SPW|TX|last_type~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N50
dffeas \A_SPW_TOP|SPW|TX|last_type.TIMEC (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|last_type~20_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.TIMEC .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.TIMEC .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal5~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal5~2_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal5~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal5~2 .lut_mask = 64'hC000C00000000000;
defparam \A_SPW_TOP|SPW|TX|Equal5~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~18 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~18_combout = ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((!\A_SPW_TOP|tx_data|data_out [8]) #
// (!\A_SPW_TOP|SPW|TX|last_type~14_combout )))) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~18 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~18 .lut_mask = 64'hC080C08000000000;
defparam \A_SPW_TOP|SPW|TX|last_type~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~19 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~19_combout = ( \A_SPW_TOP|SPW|TX|last_type.DATA~q & ( \A_SPW_TOP|SPW|TX|last_type~18_combout ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.DATA~q & ( \A_SPW_TOP|SPW|TX|last_type~18_combout & (
// (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (((!\A_SPW_TOP|SPW|TX|last_type~17_combout & !\A_SPW_TOP|SPW|TX|last_type~13_combout )))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (\A_SPW_TOP|SPW|TX|last_type~10_combout )) ) ) ) # (
// \A_SPW_TOP|SPW|TX|last_type.DATA~q & ( !\A_SPW_TOP|SPW|TX|last_type~18_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (((\A_SPW_TOP|SPW|TX|last_type~13_combout ) # (\A_SPW_TOP|SPW|TX|last_type~17_combout )))) #
// (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|last_type~10_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type~17_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~13_combout ),
.datae(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.dataf(!\A_SPW_TOP|SPW|TX|last_type~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~19 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~19 .lut_mask = 64'h00003AFAC505FFFF;
defparam \A_SPW_TOP|SPW|TX|last_type~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N56
dffeas \A_SPW_TOP|SPW|TX|last_type.DATA (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|last_type~19_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.DATA .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.DATA .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N58
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[19] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [6]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [19]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[19] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[19] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N17
dffeas \A_SPW_TOP|tx_data|mem~7 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [6]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~7_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~7 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~7 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~15 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~15_combout = (!\A_SPW_TOP|tx_data|mem~0_q & ((\A_SPW_TOP|tx_data|mem~7_q ))) # (\A_SPW_TOP|tx_data|mem~0_q & (\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a6 ))
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a6 ),
.datad(!\A_SPW_TOP|tx_data|mem~7_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~15 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~15 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|tx_data|data_out~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~16 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~16_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [19] & ( \A_SPW_TOP|tx_data|data_out~15_combout ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [19] & ( \A_SPW_TOP|tx_data|data_out~15_combout & (
// (!\A_SPW_TOP|tx_data|mem~10_combout ) # ((!\A_SPW_TOP|tx_data|mem~11_combout ) # (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [19] & (
// !\A_SPW_TOP|tx_data|data_out~15_combout & ( (\A_SPW_TOP|tx_data|mem~10_combout & (\A_SPW_TOP|tx_data|mem~11_combout & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datab(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datac(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [19]),
.dataf(!\A_SPW_TOP|tx_data|data_out~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~16 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~16 .lut_mask = 64'h00000201FDFEFFFF;
defparam \A_SPW_TOP|tx_data|data_out~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N53
dffeas \A_SPW_TOP|tx_data|data_out[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~16_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout = ( \A_SPW_TOP|SPW|TX|last_type~14_combout & ( (!\A_SPW_TOP|SPW|TX|last_type~21_combout & (!\A_SPW_TOP|SPW|TX|Selector4~0_combout & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q &
// !\A_SPW_TOP|SPW|TX|Selector4~1_combout ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datad(!\A_SPW_TOP|SPW|TX|Selector4~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0 .lut_mask = 64'h0000000080008000;
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y11_N58
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [6]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N38
dffeas \A_SPW_TOP|tx_data|mem~6 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [5]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~6_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~6 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~6 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~5 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~5_combout = (!\A_SPW_TOP|tx_data|mem~0_q & ((\A_SPW_TOP|tx_data|mem~6_q ))) # (\A_SPW_TOP|tx_data|mem~0_q & (\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a5 ))
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a5 ),
.datad(!\A_SPW_TOP|tx_data|mem~6_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~5 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~5 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|tx_data|data_out~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N4
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[18] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [5]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [18]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[18] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[18] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~6 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~6_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( \A_SPW_TOP|tx_data|mem~10_combout & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & (((\A_SPW_TOP|tx_data|data_out~5_combout )))) #
// (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ((!\A_SPW_TOP|tx_data|mem~11_combout & (\A_SPW_TOP|tx_data|data_out~5_combout )) # (\A_SPW_TOP|tx_data|mem~11_combout & ((\A_SPW_TOP|tx_data|mem_rtl_0_bypass [18]))))) ) ) ) # (
// !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( \A_SPW_TOP|tx_data|mem~10_combout & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ((!\A_SPW_TOP|tx_data|mem~11_combout & (\A_SPW_TOP|tx_data|data_out~5_combout )) # (\A_SPW_TOP|tx_data|mem~11_combout &
// ((\A_SPW_TOP|tx_data|mem_rtl_0_bypass [18]))))) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & (((\A_SPW_TOP|tx_data|data_out~5_combout )))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( !\A_SPW_TOP|tx_data|mem~10_combout & (
// \A_SPW_TOP|tx_data|data_out~5_combout ) ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & ( !\A_SPW_TOP|tx_data|mem~10_combout & ( \A_SPW_TOP|tx_data|data_out~5_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datab(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|tx_data|data_out~5_combout ),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [18]),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.dataf(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~6 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~6 .lut_mask = 64'h0F0F0F0F0D2F0E1F;
defparam \A_SPW_TOP|tx_data|data_out~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N20
dffeas \A_SPW_TOP|tx_data|data_out[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~6_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N47
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [5]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N44
dffeas \A_SPW_TOP|tx_data|mem~8 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [7]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~8_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~8 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~8 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~0 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~0_combout = ( \A_SPW_TOP|tx_data|mem~0_q & ( \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a7 ) ) # ( !\A_SPW_TOP|tx_data|mem~0_q & ( \A_SPW_TOP|tx_data|mem~8_q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a7 ),
.datad(!\A_SPW_TOP|tx_data|mem~8_q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|mem~0_q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~0 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~0 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \A_SPW_TOP|tx_data|data_out~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder_combout = \u0|write_data_fifo_tx|data_out [7]
.dataa(gnd),
.datab(gnd),
.datac(!\u0|write_data_fifo_tx|data_out [7]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N28
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [20]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~1 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~1_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [20] & ( \A_SPW_TOP|tx_data|mem~10_combout & ( ((\A_SPW_TOP|tx_data|mem~11_combout & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass
// [11])))) # (\A_SPW_TOP|tx_data|data_out~0_combout ) ) ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [20] & ( \A_SPW_TOP|tx_data|mem~10_combout & ( (\A_SPW_TOP|tx_data|data_out~0_combout & ((!\A_SPW_TOP|tx_data|mem~11_combout ) #
// (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] $ (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11])))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [20] & ( !\A_SPW_TOP|tx_data|mem~10_combout & ( \A_SPW_TOP|tx_data|data_out~0_combout ) ) ) # (
// !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [20] & ( !\A_SPW_TOP|tx_data|mem~10_combout & ( \A_SPW_TOP|tx_data|data_out~0_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datab(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datad(!\A_SPW_TOP|tx_data|data_out~0_combout ),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [20]),
.dataf(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~1 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~1 .lut_mask = 64'h00FF00FF00DE21FF;
defparam \A_SPW_TOP|tx_data|data_out~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N14
dffeas \A_SPW_TOP|tx_data|data_out[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~1_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N35
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [7]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y11_N11
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[17] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [4]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [17]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[17] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[17] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N41
dffeas \A_SPW_TOP|tx_data|mem~5 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [4]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~5_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~5 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~5 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~7 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~7_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 & ( (\A_SPW_TOP|tx_data|mem~5_q ) # (\A_SPW_TOP|tx_data|mem~0_q ) ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 & (
// (!\A_SPW_TOP|tx_data|mem~0_q & \A_SPW_TOP|tx_data|mem~5_q ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|tx_data|mem~5_q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~7 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~7 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \A_SPW_TOP|tx_data|data_out~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N27
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~8 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~8_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [17] & ( \A_SPW_TOP|tx_data|data_out~7_combout ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [17] & ( \A_SPW_TOP|tx_data|data_out~7_combout & (
// (!\A_SPW_TOP|tx_data|mem~11_combout ) # ((!\A_SPW_TOP|tx_data|mem~10_combout ) # (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] $ (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [17] & (
// !\A_SPW_TOP|tx_data|data_out~7_combout & ( (\A_SPW_TOP|tx_data|mem~11_combout & (\A_SPW_TOP|tx_data|mem~10_combout & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11])))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datab(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [17]),
.dataf(!\A_SPW_TOP|tx_data|data_out~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~8 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~8 .lut_mask = 64'h00000201FDFEFFFF;
defparam \A_SPW_TOP|tx_data|data_out~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N29
dffeas \A_SPW_TOP|tx_data|data_out[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~8_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N11
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [4]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder (
// Equation(s):
// \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder_combout = ( \u0|write_data_fifo_tx|data_out [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|write_data_fifo_tx|data_out [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N19
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [15]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N8
dffeas \A_SPW_TOP|tx_data|mem~3 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [2]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~3_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~3 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~3 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~17 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~17_combout = ( \A_SPW_TOP|tx_data|mem~0_q & ( \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a2 ) ) # ( !\A_SPW_TOP|tx_data|mem~0_q & ( \A_SPW_TOP|tx_data|mem~3_q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a2 ),
.datad(!\A_SPW_TOP|tx_data|mem~3_q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|mem~0_q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~17 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~17 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \A_SPW_TOP|tx_data|data_out~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~18 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~18_combout = ( \A_SPW_TOP|tx_data|data_out~17_combout & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]) # ((!\A_SPW_TOP|tx_data|mem~10_combout ) #
// ((!\A_SPW_TOP|tx_data|mem~11_combout ) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [15]))) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out~17_combout & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ( (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] &
// (\A_SPW_TOP|tx_data|mem~10_combout & (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [15] & \A_SPW_TOP|tx_data|mem~11_combout ))) ) ) ) # ( \A_SPW_TOP|tx_data|data_out~17_combout & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & (
// ((!\A_SPW_TOP|tx_data|mem~10_combout ) # ((!\A_SPW_TOP|tx_data|mem~11_combout ) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [15]))) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out~17_combout & (
// !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & (\A_SPW_TOP|tx_data|mem~10_combout & (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [15] & \A_SPW_TOP|tx_data|mem~11_combout ))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datab(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [15]),
.datad(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datae(!\A_SPW_TOP|tx_data|data_out~17_combout ),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~18 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~18 .lut_mask = 64'h0002FFDF0001FFEF;
defparam \A_SPW_TOP|tx_data|data_out~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N2
dffeas \A_SPW_TOP|tx_data|data_out[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~18_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N50
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [2]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N49
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[16] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [3]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [16]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[16] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[16] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N47
dffeas \A_SPW_TOP|tx_data|mem~4 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [3]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~4_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~4 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~4 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~3 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~3_combout = (!\A_SPW_TOP|tx_data|mem~0_q & ((\A_SPW_TOP|tx_data|mem~4_q ))) # (\A_SPW_TOP|tx_data|mem~0_q & (\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a3 ))
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a3 ),
.datad(!\A_SPW_TOP|tx_data|mem~4_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~3 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~3 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|tx_data|data_out~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~4 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~4_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [16] & ( \A_SPW_TOP|tx_data|data_out~3_combout ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [16] & ( \A_SPW_TOP|tx_data|data_out~3_combout & (
// (!\A_SPW_TOP|tx_data|mem~11_combout ) # ((!\A_SPW_TOP|tx_data|mem~10_combout ) # (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] $ (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [16] & (
// !\A_SPW_TOP|tx_data|data_out~3_combout & ( (\A_SPW_TOP|tx_data|mem~11_combout & (\A_SPW_TOP|tx_data|mem~10_combout & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11])))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datab(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datad(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [16]),
.dataf(!\A_SPW_TOP|tx_data|data_out~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~4 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~4 .lut_mask = 64'h00000021FFDEFFFF;
defparam \A_SPW_TOP|tx_data|data_out~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N26
dffeas \A_SPW_TOP|tx_data|data_out[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~4_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N17
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [3]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~4_combout = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] & ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5] $
// (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] & ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last
// [6] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] $ (\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]))) ) ) ) # ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] & (
// !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] $ (\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]))) ) ) )
// # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3] & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7] $
// (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [6]),
.datab(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [5]),
.datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [7]),
.datad(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [4]),
.datae(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [2]),
.dataf(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~4 .lut_mask = 64'h6996966996696996;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y11_N29
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[14] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [1]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [14]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[14] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[14] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N35
dffeas \A_SPW_TOP|tx_data|mem~2 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [1]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~2_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~2 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~2 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~11 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~11_combout = (!\A_SPW_TOP|tx_data|mem~0_q & ((\A_SPW_TOP|tx_data|mem~2_q ))) # (\A_SPW_TOP|tx_data|mem~0_q & (\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a1 ))
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a1 ),
.datad(!\A_SPW_TOP|tx_data|mem~2_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~11 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~11 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|tx_data|data_out~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~12 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~12_combout = ( \A_SPW_TOP|tx_data|data_out~11_combout & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]) # ((!\A_SPW_TOP|tx_data|mem~11_combout ) #
// ((!\A_SPW_TOP|tx_data|mem~10_combout ) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [14]))) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out~11_combout & ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ( (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] &
// (\A_SPW_TOP|tx_data|mem~11_combout & (\A_SPW_TOP|tx_data|mem~10_combout & \A_SPW_TOP|tx_data|mem_rtl_0_bypass [14]))) ) ) ) # ( \A_SPW_TOP|tx_data|data_out~11_combout & ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & (
// ((!\A_SPW_TOP|tx_data|mem~11_combout ) # ((!\A_SPW_TOP|tx_data|mem~10_combout ) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [14]))) # (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out~11_combout & (
// !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12] & ( (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] & (\A_SPW_TOP|tx_data|mem~11_combout & (\A_SPW_TOP|tx_data|mem~10_combout & \A_SPW_TOP|tx_data|mem_rtl_0_bypass [14]))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datab(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datad(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [14]),
.datae(!\A_SPW_TOP|tx_data|data_out~11_combout ),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~12 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~12 .lut_mask = 64'h0002FDFF0001FEFF;
defparam \A_SPW_TOP|tx_data|data_out~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N35
dffeas \A_SPW_TOP|tx_data|data_out[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~12_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N25
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [1]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y11_N2
dffeas \A_SPW_TOP|tx_data|mem_rtl_0_bypass[13] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [0]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem_rtl_0_bypass [13]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[13] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem_rtl_0_bypass[13] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y11_N14
dffeas \A_SPW_TOP|tx_data|mem~1 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\u0|write_data_fifo_tx|data_out [0]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|tx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|mem~1_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|mem~1 .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|mem~1 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~13 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~13_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout & ( (\A_SPW_TOP|tx_data|mem~1_q ) # (\A_SPW_TOP|tx_data|mem~0_q ) ) ) # (
// !\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout & ( (!\A_SPW_TOP|tx_data|mem~0_q & \A_SPW_TOP|tx_data|mem~1_q ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem~0_q ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|tx_data|mem~1_q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~13 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~13 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \A_SPW_TOP|tx_data|data_out~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|tx_data|data_out~14 (
// Equation(s):
// \A_SPW_TOP|tx_data|data_out~14_combout = ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [13] & ( \A_SPW_TOP|tx_data|data_out~13_combout ) ) # ( !\A_SPW_TOP|tx_data|mem_rtl_0_bypass [13] & ( \A_SPW_TOP|tx_data|data_out~13_combout & (
// (!\A_SPW_TOP|tx_data|mem~10_combout ) # ((!\A_SPW_TOP|tx_data|mem~11_combout ) # (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|tx_data|mem_rtl_0_bypass [13] & (
// !\A_SPW_TOP|tx_data|data_out~13_combout & ( (\A_SPW_TOP|tx_data|mem~10_combout & (\A_SPW_TOP|tx_data|mem~11_combout & (!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [11]),
.datab(!\A_SPW_TOP|tx_data|mem~10_combout ),
.datac(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [12]),
.datad(!\A_SPW_TOP|tx_data|mem~11_combout ),
.datae(!\A_SPW_TOP|tx_data|mem_rtl_0_bypass [13]),
.dataf(!\A_SPW_TOP|tx_data|data_out~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|tx_data|data_out~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out~14 .extended_lut = "off";
defparam \A_SPW_TOP|tx_data|data_out~14 .lut_mask = 64'h00000021FFDEFFFF;
defparam \A_SPW_TOP|tx_data|data_out~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y11_N50
dffeas \A_SPW_TOP|tx_data|data_out[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|tx_data|data_out~14_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|tx_data|data_out~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|tx_data|data_out [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|tx_data|data_out[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|tx_data|data_out[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y11_N1
dffeas \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|tx_data|data_out [0]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~28 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~28_combout = ( \A_SPW_TOP|SPW|TX|last_type~21_combout & ( \A_SPW_TOP|tx_data|data_out [8] & ( (!\A_SPW_TOP|SPW|TX|last_type.EOP~q & (!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ((\A_SPW_TOP|SPW|TX|last_type~14_combout
// )))) # (\A_SPW_TOP|SPW|TX|last_type.EOP~q & ((!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ) # ((!\A_SPW_TOP|SPW|TX|last_type~11_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type~21_combout & ( \A_SPW_TOP|tx_data|data_out [8] & (
// (\A_SPW_TOP|SPW|TX|last_type.EOP~q & ((!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ) # (!\A_SPW_TOP|SPW|TX|last_type~11_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|last_type~21_combout & ( !\A_SPW_TOP|tx_data|data_out [8] & (
// (\A_SPW_TOP|SPW|TX|last_type.EOP~q & ((!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & ((!\A_SPW_TOP|SPW|TX|last_type~14_combout ))) # (\A_SPW_TOP|SPW|TX|enable_time_code~0_combout & (!\A_SPW_TOP|SPW|TX|last_type~11_combout )))) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|last_type~21_combout & ( !\A_SPW_TOP|tx_data|data_out [8] & ( (\A_SPW_TOP|SPW|TX|last_type.EOP~q & ((!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ) # (!\A_SPW_TOP|SPW|TX|last_type~11_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.datab(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datae(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.dataf(!\A_SPW_TOP|tx_data|data_out [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~28_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~28 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~28 .lut_mask = 64'h54545410545454DC;
defparam \A_SPW_TOP|SPW|TX|last_type~28 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~22 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~22_combout = ( \A_SPW_TOP|SPW|TX|last_type.EOP~q & ( \A_SPW_TOP|SPW|TX|Selector4~2_combout & ( !\A_SPW_TOP|SPW|TX|last_type~10_combout ) ) ) # ( \A_SPW_TOP|SPW|TX|last_type.EOP~q & ( !\A_SPW_TOP|SPW|TX|Selector4~2_combout
// & ( (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & ((\A_SPW_TOP|SPW|TX|last_type~28_combout ))) # (\A_SPW_TOP|SPW|TX|Selector5~3_combout & (!\A_SPW_TOP|SPW|TX|Equal5~0_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type.EOP~q & (
// !\A_SPW_TOP|SPW|TX|Selector4~2_combout & ( (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & \A_SPW_TOP|SPW|TX|last_type~28_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~28_combout ),
.datae(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~22_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~22 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~22 .lut_mask = 64'h00CC30FC0000AAAA;
defparam \A_SPW_TOP|SPW|TX|last_type~22 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N41
dffeas \A_SPW_TOP|SPW|TX|last_type.EOP (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|last_type~22_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.EOP .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.EOP .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_null~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_null~0_combout = ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0] & ( \A_SPW_TOP|SPW|TX|last_type.EOP~q & ( \A_SPW_TOP|SPW|TX|Equal5~2_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0] & (
// \A_SPW_TOP|SPW|TX|last_type.EOP~q & ( \A_SPW_TOP|SPW|TX|Equal5~2_combout ) ) ) # ( \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0] & ( !\A_SPW_TOP|SPW|TX|last_type.EOP~q & ( (\A_SPW_TOP|SPW|TX|last_type.DATA~q & (\A_SPW_TOP|SPW|TX|Equal5~2_combout &
// (!\A_SPW_TOP|SPW|TX|tx_dout_data~4_combout $ (\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1])))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0] & ( !\A_SPW_TOP|SPW|TX|last_type.EOP~q & ( (\A_SPW_TOP|SPW|TX|last_type.DATA~q &
// (\A_SPW_TOP|SPW|TX|Equal5~2_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_data~4_combout $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1])))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~4_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]),
.datae(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~0 .lut_mask = 64'h010404010F0F0F0F;
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_null~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_null~1_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0]) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_null~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~1 .lut_mask = 64'h0C0C0C0C88888888;
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_null~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_null~2_combout = ( !\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_null~1_combout & ( (\A_SPW_TOP|SPW|TX|Equal5~2_combout & (((!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout &
// \A_SPW_TOP|SPW|TX|last_type.TIMEC~q )) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_null~1_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ) #
// ((!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ) # ((!\A_SPW_TOP|SPW|TX|Equal5~2_combout ) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_null~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~2 .lut_mask = 64'hFEFF0000020F0000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_null~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|enable_n_char~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|enable_n_char~0_combout = ( \A_SPW_TOP|SPW|TX|always7~3_combout & ( (\A_SPW_TOP|tx_data|write_tx~q & (!\A_SPW_TOP|SPW|TX|LessThan2~0_combout & !\A_SPW_TOP|SPW|TX|always7~1_combout )) ) )
.dataa(!\A_SPW_TOP|tx_data|write_tx~q ),
.datab(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|enable_n_char~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|enable_n_char~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|enable_n_char~0 .lut_mask = 64'h0000000044004400;
defparam \A_SPW_TOP|SPW|TX|enable_n_char~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~26 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~26_combout = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|always7~0_combout & (\A_SPW_TOP|SPW|TX|enable_n_char~0_combout & ((\A_SPW_TOP|SPW|TX|last_type~21_combout )))) #
// (\A_SPW_TOP|SPW|TX|always7~0_combout & (((\A_SPW_TOP|SPW|TX|last_type~11_combout )))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|enable_n_char~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~21_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~26_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~26 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~26 .lut_mask = 64'h0000000005270527;
defparam \A_SPW_TOP|SPW|TX|last_type~26 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~27 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~27_combout = ( \A_SPW_TOP|SPW|TX|last_type~26_combout & ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (!\A_SPW_TOP|SPW|TX|last_type.FCT~q & (\A_SPW_TOP|SPW|TX|Equal5~0_combout & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout ))))
// # (\A_SPW_TOP|SPW|TX|last_type.FCT~q & (((!\A_SPW_TOP|SPW|TX|last_type~10_combout ) # (!\A_SPW_TOP|SPW|TX|Selector4~2_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_type~26_combout & ( \A_SPW_TOP|SPW|TX|Selector5~3_combout & (
// (!\A_SPW_TOP|SPW|TX|last_type.FCT~q & (\A_SPW_TOP|SPW|TX|Equal5~0_combout & ((!\A_SPW_TOP|SPW|TX|Selector4~2_combout )))) # (\A_SPW_TOP|SPW|TX|last_type.FCT~q & (((!\A_SPW_TOP|SPW|TX|last_type~10_combout ) # (!\A_SPW_TOP|SPW|TX|Selector4~2_combout ))))
// ) ) ) # ( \A_SPW_TOP|SPW|TX|last_type~26_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (\A_SPW_TOP|SPW|TX|last_type.FCT~q & (!\A_SPW_TOP|SPW|TX|last_type~10_combout & \A_SPW_TOP|SPW|TX|Selector4~2_combout )) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|last_type~26_combout & ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (\A_SPW_TOP|SPW|TX|last_type.FCT~q & ((!\A_SPW_TOP|SPW|TX|last_type~10_combout ) # (!\A_SPW_TOP|SPW|TX|Selector4~2_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
.datab(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datae(!\A_SPW_TOP|SPW|TX|last_type~26_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~27_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~27 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~27 .lut_mask = 64'h5550005077507750;
defparam \A_SPW_TOP|SPW|TX|last_type~27 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N53
dffeas \A_SPW_TOP|SPW|TX|last_type.FCT (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|last_type~27_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.FCT .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.FCT .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~24 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~24_combout = (\A_SPW_TOP|SPW|TX|last_type~16_combout & (((\A_SPW_TOP|SPW|TX|enable_n_char~0_combout & \A_SPW_TOP|SPW|TX|Equal5~4_combout )) # (\A_SPW_TOP|SPW|TX|always7~0_combout )))
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|enable_n_char~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~4_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~16_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~24_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~24 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~24 .lut_mask = 64'h0057005700570057;
defparam \A_SPW_TOP|SPW|TX|last_type~24 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~23 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~23_combout = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|Selector5~0_combout & (!\A_SPW_TOP|SPW|TX|Selector5~2_combout & ((!\A_SPW_TOP|tx_data|data_out [8]) # (!\A_SPW_TOP|SPW|TX|last_type~12_combout
// )))) ) ) # ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|Selector5~0_combout & !\A_SPW_TOP|SPW|TX|Selector5~2_combout ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~12_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~2_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~23_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~23 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~23 .lut_mask = 64'hCC00CC00C800C800;
defparam \A_SPW_TOP|SPW|TX|last_type~23 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|last_type~25 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|last_type~25_combout = ( \A_SPW_TOP|SPW|TX|Equal5~0_combout & ( \A_SPW_TOP|SPW|TX|last_type.NULL~q & ( (!\A_SPW_TOP|SPW|TX|last_type~10_combout ) # (!\A_SPW_TOP|SPW|TX|Selector4~2_combout ) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|Equal5~0_combout & ( \A_SPW_TOP|SPW|TX|last_type.NULL~q & ( (!\A_SPW_TOP|SPW|TX|last_type~10_combout ) # (!\A_SPW_TOP|SPW|TX|Selector4~2_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Equal5~0_combout & ( !\A_SPW_TOP|SPW|TX|last_type.NULL~q
// & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & ((!\A_SPW_TOP|SPW|TX|last_type~23_combout ) # (\A_SPW_TOP|SPW|TX|last_type~24_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal5~0_combout & ( !\A_SPW_TOP|SPW|TX|last_type.NULL~q & (
// (\A_SPW_TOP|SPW|TX|last_type~24_combout & (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & \A_SPW_TOP|SPW|TX|last_type~23_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type~10_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type~24_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~23_combout ),
.datae(!\A_SPW_TOP|SPW|TX|Equal5~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|last_type~25_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|last_type~25 .lut_mask = 64'h0030F030FAFAFAFA;
defparam \A_SPW_TOP|SPW|TX|last_type~25 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y12_N11
dffeas \A_SPW_TOP|SPW|TX|last_type.NULL (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|last_type~25_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_type.NULL .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_type.NULL .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~1_combout = ( \A_SPW_TOP|SPW|TX|last_type.NULL~q & ( !\A_SPW_TOP|SPW|TX|last_type.FCT~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~1 .lut_mask = 64'h00000000F0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|tx_dout~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~6_combout = ( \A_SPW_TOP|SPW|TX|first_time~q & ( (!\A_SPW_TOP|SPW|TX|tx_dout~1_combout & \A_SPW_TOP|SPW|TX|Equal5~2_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|first_time~q & ( \A_SPW_TOP|SPW|TX|Equal5~2_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|first_time~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~6 .lut_mask = 64'h00FF00FF00F000F0;
defparam \A_SPW_TOP|SPW|TX|tx_dout~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~8_combout = (\A_SPW_TOP|SPW|TX|Equal5~2_combout & ((!\A_SPW_TOP|SPW|TX|last_type.NULL~q ) # (\A_SPW_TOP|SPW|TX|last_type.FCT~q )))
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
.datad(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~8 .lut_mask = 64'h3033303330333033;
defparam \A_SPW_TOP|SPW|TX|tx_dout~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal5~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal5~3_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3])) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Equal5~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal5~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal5~3 .lut_mask = 64'h2200220000000000;
defparam \A_SPW_TOP|SPW|TX|Equal5~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~7_combout = ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & (((!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q & !\A_SPW_TOP|SPW|TX|Equal5~3_combout ))
// # (\A_SPW_TOP|SPW|TX|last_type.DATA~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal5~2_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & !\A_SPW_TOP|SPW|TX|Equal5~3_combout ) ) ) ) # (
// \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & (((!\A_SPW_TOP|SPW|TX|Equal5~3_combout ) # (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q )) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q
// ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal5~2_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & !\A_SPW_TOP|SPW|TX|Equal5~3_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~3_combout ),
.datae(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~7 .lut_mask = 64'hF000F070F000D050;
defparam \A_SPW_TOP|SPW|TX|tx_dout~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~9_combout = ( \A_SPW_TOP|SPW|TX|tx_dout~8_combout & ( \A_SPW_TOP|SPW|TX|tx_dout~7_combout & ( (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout & !\A_SPW_TOP|SPW|TX|tx_dout~6_combout )) ) )
// ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~8_combout & ( \A_SPW_TOP|SPW|TX|tx_dout~7_combout & ( (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout & !\A_SPW_TOP|SPW|TX|tx_dout~6_combout )) ) ) ) # (
// \A_SPW_TOP|SPW|TX|tx_dout~8_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout~7_combout & ( (\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout & !\A_SPW_TOP|SPW|TX|tx_dout~6_combout )) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_dout~8_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout~7_combout & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (\A_SPW_TOP|SPW|TX|Selector5~3_combout )) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout &
// (((!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout & !\A_SPW_TOP|SPW|TX|tx_dout~6_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout~8_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~9 .lut_mask = 64'h7222500050005000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_sout_e~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_sout_e~0_combout = ( !\A_SPW_TOP|SPW|TX|Selector5~3_combout & ( (\A_SPW_TOP|SPW|TX|tx_sout_e~q & (!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout & !\A_SPW_TOP|SPW|TX|Selector4~2_combout )) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout_e~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_sout_e~0 .lut_mask = 64'h4040404000000000;
defparam \A_SPW_TOP|SPW|TX|tx_sout_e~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~5_combout = ( \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & (!\A_SPW_TOP|SPW|TX|Selector5~0_combout &
// !\A_SPW_TOP|SPW|TX|Selector4~0_combout ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~5 .lut_mask = 64'h0000000080008000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~5_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~4_combout & ( !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0] $ (\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_data~4_combout & (
// !\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0] $ (!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [0]),
.datad(!\A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last [1]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~5 .lut_mask = 64'h0FF00FF0F00FF00F;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~16 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~16_combout = ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( !\A_SPW_TOP|tx_data|data_out [1] & ( (!\A_SPW_TOP|tx_data|data_out [0] & ((!\A_SPW_TOP|tx_data|data_out [8] & ((\A_SPW_TOP|SPW|TX|last_type.FCT~q ))) #
// (\A_SPW_TOP|tx_data|data_out [8] & (!\A_SPW_TOP|SPW|TX|last_type.NULL~q )))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
.datac(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
.datad(!\A_SPW_TOP|tx_data|data_out [0]),
.datae(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.dataf(!\A_SPW_TOP|tx_data|data_out [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~16 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~16 .lut_mask = 64'h00004E0000000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~16 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always3~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always3~4_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] &
// !\A_SPW_TOP|tx_data|data_out [8]))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datad(!\A_SPW_TOP|tx_data|data_out [8]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always3~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always3~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always3~4 .lut_mask = 64'h8000800000000000;
defparam \A_SPW_TOP|SPW|TX|always3~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~17 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~17_combout = ( \A_SPW_TOP|SPW|TX|always3~4_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & ( (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q &
// ((\A_SPW_TOP|SPW|TX|tx_dout_data~16_combout )))) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q & (((!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always3~4_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & (
// \A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ) ) ) # ( \A_SPW_TOP|SPW|TX|always3~4_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & ( (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (((\A_SPW_TOP|SPW|TX|tx_dout_data~16_combout )) #
// (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ))) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q & (((!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always3~4_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout & (
// \A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always3~4_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~17 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~17 .lut_mask = 64'h00FF72FA00FF50D8;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout = ( !\A_SPW_TOP|SPW|TX|hold_data~q & ( (\u0|timecode_tx_enable|data_out~q & (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q & (\A_SPW_TOP|SPW|TX|always7~3_combout &
// !\A_SPW_TOP|SPW|TX|last_type~11_combout ))) ) )
.dataa(!\u0|timecode_tx_enable|data_out~q ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ),
.datac(!\A_SPW_TOP|SPW|TX|always7~3_combout ),
.datad(!\A_SPW_TOP|SPW|TX|last_type~11_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|hold_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7 .lut_mask = 64'h0100010000000000;
defparam \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y11_N10
dffeas \A_SPW_TOP|SPW|TX|timecode_s[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [3]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N16
dffeas \A_SPW_TOP|SPW|TX|timecode_s[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [4]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N2
dffeas \A_SPW_TOP|SPW|TX|timecode_s[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [2]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N56
dffeas \A_SPW_TOP|SPW|TX|timecode_s[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [5]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_timecode~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout = ( \A_SPW_TOP|SPW|TX|timecode_s [5] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|timecode_s [3]) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|timecode_s [5] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|timecode_s [3] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) ) ) ) # ( \A_SPW_TOP|SPW|TX|timecode_s [5] & (
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((\A_SPW_TOP|SPW|TX|timecode_s [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|timecode_s [4])) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|timecode_s [5] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((\A_SPW_TOP|SPW|TX|timecode_s [2]))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] &
// (\A_SPW_TOP|SPW|TX|timecode_s [4])) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|timecode_s [3]),
.datab(!\A_SPW_TOP|SPW|TX|timecode_s [4]),
.datac(!\A_SPW_TOP|SPW|TX|timecode_s [2]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datae(!\A_SPW_TOP|SPW|TX|timecode_s [5]),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~0 .lut_mask = 64'h0F330F33550055FF;
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y11_N5
dffeas \A_SPW_TOP|SPW|TX|timecode_s[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [7]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N44
dffeas \A_SPW_TOP|SPW|TX|timecode_s[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [6]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_timecode~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|timecode_s [7]) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|timecode_s [6]) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|timecode_s [7]),
.datad(!\A_SPW_TOP|SPW|TX|timecode_s [6]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~2 .lut_mask = 64'h00CC00CC0C0C0C0C;
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|Equal5~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|Equal5~1_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|Equal5~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|Equal5~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|Equal5~1 .lut_mask = 64'hCCCCCCCC00000000;
defparam \A_SPW_TOP|SPW|TX|Equal5~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y11_N59
dffeas \A_SPW_TOP|SPW|TX|timecode_s[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [1]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|timecode_s~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|timecode_s~0_combout = (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ) # (\A_SPW_TOP|SPW|TX|timecode_s [9])
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|timecode_s [9]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|timecode_s~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|timecode_s~0 .lut_mask = 64'h0FFF0FFF0FFF0FFF;
defparam \A_SPW_TOP|SPW|TX|timecode_s~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N5
dffeas \A_SPW_TOP|SPW|TX|timecode_s[9] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|timecode_s~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[9] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y11_N14
dffeas \A_SPW_TOP|SPW|TX|timecode_s[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\u0|timecode_tx_data|data_out [0]),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|timecode_s [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|timecode_s[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|timecode_s[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_timecode~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout = ( \A_SPW_TOP|SPW|TX|timecode_s [0] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|timecode_s [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1]) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|timecode_s [0] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|timecode_s [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1]) ) ) ) # ( \A_SPW_TOP|SPW|TX|timecode_s [0] & (
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) # (\A_SPW_TOP|SPW|TX|timecode_s [9]) ) ) ) # ( !\A_SPW_TOP|SPW|TX|timecode_s [0] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (
// (\A_SPW_TOP|SPW|TX|timecode_s [9] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) ) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|timecode_s [1]),
.datac(!\A_SPW_TOP|SPW|TX|timecode_s [9]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datae(!\A_SPW_TOP|SPW|TX|timecode_s [0]),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~1 .lut_mask = 64'h0F000FFF00330033;
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_timecode~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( \A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]) # (\A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout ) ) ) )
// # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( \A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|Equal5~1_combout ))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] &
// (\A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout )) ) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout & \A_SPW_TOP|SPW|TX|global_counter_transfer [3])
// ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|Equal5~1_combout ))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] &
// (\A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout ),
.datac(!\A_SPW_TOP|SPW|TX|Equal5~1_combout ),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~3 .lut_mask = 64'hF0550033F055FF33;
defparam \A_SPW_TOP|SPW|TX|tx_dout_timecode~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~2_combout = ( !\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout & ( (\A_SPW_TOP|SPW|TX|Equal5~2_combout & (((!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout &
// \A_SPW_TOP|SPW|TX|last_type.TIMEC~q )) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ) #
// ((!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ) # ((!\A_SPW_TOP|SPW|TX|Equal5~2_combout ) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~2 .lut_mask = 64'hFFEF0000002F0000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~3_combout = ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( \A_SPW_TOP|tx_data|data_out [8] & ( (\A_SPW_TOP|SPW|TX|always7~0_combout & (!\A_SPW_TOP|SPW|TX|tx_dout~2_combout & \A_SPW_TOP|SPW|TX|tx_dout~1_combout )) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|Equal5~2_combout & ( \A_SPW_TOP|tx_data|data_out [8] & ( (\A_SPW_TOP|SPW|TX|always7~0_combout & !\A_SPW_TOP|SPW|TX|tx_dout~2_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( !\A_SPW_TOP|tx_data|data_out [8] & (
// (!\A_SPW_TOP|SPW|TX|always7~0_combout & (\A_SPW_TOP|SPW|TX|enable_n_char~0_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout~1_combout )))) # (\A_SPW_TOP|SPW|TX|always7~0_combout & (((!\A_SPW_TOP|SPW|TX|tx_dout~2_combout & \A_SPW_TOP|SPW|TX|tx_dout~1_combout
// )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal5~2_combout & ( !\A_SPW_TOP|tx_data|data_out [8] & ( (\A_SPW_TOP|SPW|TX|always7~0_combout & !\A_SPW_TOP|SPW|TX|tx_dout~2_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|enable_n_char~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout~1_combout ),
.datae(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.dataf(!\A_SPW_TOP|tx_data|data_out [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~3 .lut_mask = 64'h5050225050500050;
defparam \A_SPW_TOP|SPW|TX|tx_dout~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~22 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~22_combout = ( \A_SPW_TOP|tx_data|data_out [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] $ (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) ) # (
// !\A_SPW_TOP|tx_data|data_out [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (((\A_SPW_TOP|SPW|TX|global_counter_transfer [0])))) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] &
// ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # (\A_SPW_TOP|tx_data|data_out [7])))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|tx_data|data_out [7]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|data_out [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~22_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~22 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~22 .lut_mask = 64'h44AE44AE22882288;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~22 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~21 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~21_combout = ( \A_SPW_TOP|tx_data|data_out [2] & ( \A_SPW_TOP|tx_data|data_out [0] & ( (!\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|tx_data|data_out [8] $ (((!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))))) #
// (\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|tx_data|data_out [8] & ((\A_SPW_TOP|SPW|TX|global_counter_transfer [2]) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out [2] & ( \A_SPW_TOP|tx_data|data_out [0] & (
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ((!\A_SPW_TOP|tx_data|data_out [1] & (\A_SPW_TOP|tx_data|data_out [8])) # (\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|tx_data|data_out [8] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1])))) ) ) ) # (
// \A_SPW_TOP|tx_data|data_out [2] & ( !\A_SPW_TOP|tx_data|data_out [0] & ( (!\A_SPW_TOP|tx_data|data_out [8] & (((\A_SPW_TOP|tx_data|data_out [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [1])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) ) ) ) # (
// !\A_SPW_TOP|tx_data|data_out [2] & ( !\A_SPW_TOP|tx_data|data_out [0] & ( (\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|tx_data|data_out [8] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [2]))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [1]),
.datab(!\A_SPW_TOP|tx_data|data_out [8]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datae(!\A_SPW_TOP|tx_data|data_out [2]),
.dataf(!\A_SPW_TOP|tx_data|data_out [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~21 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~21 .lut_mask = 64'h040004CC260026CC;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~21 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~20 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~20_combout = ( !\A_SPW_TOP|tx_data|data_out [6] & ( ((!\A_SPW_TOP|tx_data|data_out [7]) # (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1]) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|tx_data|data_out [7]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|data_out [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~20 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~20 .lut_mask = 64'hFFF3FFF300000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~20 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~27 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~27_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( (!\A_SPW_TOP|tx_data|data_out [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout )))) #
// (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|tx_data|data_out [4])))) # (\A_SPW_TOP|tx_data|data_out [8] & ((((\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ))))) ) ) # ( \A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (
// (!\A_SPW_TOP|tx_data|data_out [8] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|tx_data|data_out [3])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (((\A_SPW_TOP|tx_data|data_out [5])))))) # (\A_SPW_TOP|tx_data|data_out [8] &
// ((((\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ))))) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|tx_data|data_out [3]),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.dataf(!\A_SPW_TOP|tx_data|data_out [5]),
.datag(!\A_SPW_TOP|tx_data|data_out [4]),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~27_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~27 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~27 .lut_mask = 64'h02DF085D02DF2A7F;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~27 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~0_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~27_combout & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout_data~27_combout & (
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|tx_dout_data~22_combout & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout )) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] &
// ((!\A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ))))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_data~27_combout & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|tx_dout_data~22_combout & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]
// & (\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout )) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ))))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~22_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_data~27_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~0 .lut_mask = 64'h130213020000AAAA;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~9 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~9_combout = ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( (\A_SPW_TOP|tx_data|data_out [0] & ((!\A_SPW_TOP|tx_data|data_out [8] & ((\A_SPW_TOP|SPW|TX|last_type.FCT~q ))) # (\A_SPW_TOP|tx_data|data_out [8] &
// (!\A_SPW_TOP|SPW|TX|last_type.NULL~q )))) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|last_type.NULL~q ),
.datac(!\A_SPW_TOP|tx_data|data_out [0]),
.datad(!\A_SPW_TOP|SPW|TX|last_type.FCT~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~9 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~9 .lut_mask = 64'h00000000040E040E;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N15
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~10_combout = ( \A_SPW_TOP|tx_data|data_out [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] &
// !\A_SPW_TOP|tx_data|data_out [0]))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datad(!\A_SPW_TOP|tx_data|data_out [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|data_out [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~10 .lut_mask = 64'h0000000020002000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout = ( !\A_SPW_TOP|tx_data|data_out [1] & ( \A_SPW_TOP|SPW|TX|last_type.DATA~q & ( ((!\A_SPW_TOP|SPW|TX|Equal5~2_combout ) # (\A_SPW_TOP|tx_data|data_out [8])) # (\A_SPW_TOP|tx_data|data_out [0]) ) ) ) # (
// !\A_SPW_TOP|tx_data|data_out [1] & ( !\A_SPW_TOP|SPW|TX|last_type.DATA~q & ( ((!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ) # ((!\A_SPW_TOP|SPW|TX|Equal5~2_combout ) # (\A_SPW_TOP|tx_data|data_out [8]))) # (\A_SPW_TOP|tx_data|data_out [0]) ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [0]),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|tx_data|data_out [8]),
.datad(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.datae(!\A_SPW_TOP|tx_data|data_out [1]),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~11 .lut_mask = 64'hFFDF0000FF5F0000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N9
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~12 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~12_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~12 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~12 .lut_mask = 64'h0000000077777777;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always3~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always3~0_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|tx_data|data_out [8] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] &
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & !\A_SPW_TOP|tx_data|data_out [1]))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [8]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datad(!\A_SPW_TOP|tx_data|data_out [1]),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always3~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always3~0 .lut_mask = 64'h8000000000000000;
defparam \A_SPW_TOP|SPW|TX|always3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~13 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~13_combout = ( \A_SPW_TOP|SPW|TX|always3~0_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~5_combout & ( (!\A_SPW_TOP|tx_data|data_out [0] & (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q & (!\A_SPW_TOP|SPW|TX|last_type.DATA~q &
// !\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|always3~0_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout & ( (!\A_SPW_TOP|tx_data|data_out [0] & (((\A_SPW_TOP|SPW|TX|last_type.TIMEC~q &
// !\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout )) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q ))) ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [0]),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always3~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~13 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~13 .lut_mask = 64'h00002A0A00002000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~23 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~23_combout = ( \A_SPW_TOP|tx_data|data_out [0] & ( \A_SPW_TOP|SPW|TX|last_type.DATA~q & ( (!\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|tx_data|data_out [8])) ) ) ) # (
// !\A_SPW_TOP|tx_data|data_out [0] & ( \A_SPW_TOP|SPW|TX|last_type.DATA~q & ( (!\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] $ (\A_SPW_TOP|tx_data|data_out [8]))) ) ) ) # ( \A_SPW_TOP|tx_data|data_out [0] & (
// !\A_SPW_TOP|SPW|TX|last_type.DATA~q & ( (!\A_SPW_TOP|tx_data|data_out [1] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & !\A_SPW_TOP|tx_data|data_out [8])) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out [0] & ( !\A_SPW_TOP|SPW|TX|last_type.DATA~q & (
// (!\A_SPW_TOP|tx_data|data_out [1] & ((!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q & !\A_SPW_TOP|tx_data|data_out [8])) # (\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ((\A_SPW_TOP|tx_data|data_out [8]))))) ) )
// )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datab(!\A_SPW_TOP|tx_data|data_out [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datad(!\A_SPW_TOP|tx_data|data_out [8]),
.datae(!\A_SPW_TOP|tx_data|data_out [0]),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~23_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~23 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~23 .lut_mask = 64'h400CC000C00CC000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~23 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~8 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~8_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( \A_SPW_TOP|SPW|TX|last_type.EOP~q & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|tx_dout_data~23_combout &
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [3])) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & ( !\A_SPW_TOP|SPW|TX|last_type.EOP~q & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (\A_SPW_TOP|SPW|TX|tx_dout_data~23_combout &
// (!\A_SPW_TOP|tx_data|data_out [0] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~23_combout ),
.datac(!\A_SPW_TOP|tx_data|data_out [0]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~8 .lut_mask = 64'h2000000022000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~19 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~19_combout = ( !\A_SPW_TOP|tx_data|data_out [1] & ( (\A_SPW_TOP|tx_data|data_out [0] & ((\A_SPW_TOP|SPW|TX|last_type.DATA~q ) # (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datad(!\A_SPW_TOP|tx_data|data_out [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|data_out [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~19 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~19 .lut_mask = 64'h005F005F00000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~19 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout = ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|tx_data|data_out [8] &
// !\A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) ) ) # ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & ( !\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|tx_data|data_out [8] &
// ((\A_SPW_TOP|SPW|TX|global_counter_transfer [0]) # (\A_SPW_TOP|SPW|TX|tx_dout_data~19_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~19_combout ),
.datac(!\A_SPW_TOP|tx_data|data_out [8]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~1 .lut_mask = 64'h20A00000A0000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always3~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always3~1_combout = ( !\A_SPW_TOP|tx_data|data_out [8] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] &
// \A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|data_out [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always3~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always3~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always3~1 .lut_mask = 64'h0080008000000000;
defparam \A_SPW_TOP|SPW|TX|always3~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always3~5 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always3~5_combout = ( \A_SPW_TOP|tx_data|data_out [0] & ( (!\A_SPW_TOP|tx_data|data_out [1] & !\A_SPW_TOP|tx_data|data_out [8]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|tx_data|data_out [1]),
.datad(!\A_SPW_TOP|tx_data|data_out [8]),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|data_out [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always3~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always3~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always3~5 .lut_mask = 64'h00000000F000F000;
defparam \A_SPW_TOP|SPW|TX|always3~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always3~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always3~2_combout = ( \A_SPW_TOP|SPW|TX|always3~5_combout & ( \A_SPW_TOP|SPW|TX|last_type.DATA~q & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] &
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(!\A_SPW_TOP|SPW|TX|always3~5_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always3~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always3~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always3~2 .lut_mask = 64'h0000000000008000;
defparam \A_SPW_TOP|SPW|TX|always3~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|always3~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|always3~3_combout = ( \A_SPW_TOP|SPW|TX|always3~5_combout & ( \A_SPW_TOP|SPW|TX|last_type.TIMEC~q & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] &
// (!\A_SPW_TOP|SPW|TX|global_counter_transfer [0] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [3]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datae(!\A_SPW_TOP|SPW|TX|always3~5_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|always3~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|always3~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|always3~3 .lut_mask = 64'h0000000000008000;
defparam \A_SPW_TOP|SPW|TX|always3~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~6 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~6_combout = ( \A_SPW_TOP|tx_data|data_out [0] & ( \A_SPW_TOP|SPW|TX|global_counter_transfer [1] & ( (!\A_SPW_TOP|SPW|TX|global_counter_transfer [2] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [3] &
// (!\A_SPW_TOP|tx_data|data_out [8] & !\A_SPW_TOP|SPW|TX|global_counter_transfer [0]))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datac(!\A_SPW_TOP|tx_data|data_out [8]),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(!\A_SPW_TOP|tx_data|data_out [0]),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~6 .lut_mask = 64'h0000000000008000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~7 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout = ( \A_SPW_TOP|SPW|TX|always3~3_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~6_combout & ( (!\A_SPW_TOP|SPW|TX|always3~2_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout )) #
// (\A_SPW_TOP|SPW|TX|always3~2_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always3~3_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~6_combout & ( (!\A_SPW_TOP|SPW|TX|always3~2_combout &
// (!\A_SPW_TOP|SPW|TX|always3~1_combout )) # (\A_SPW_TOP|SPW|TX|always3~2_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|always3~3_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~6_combout & (
// (!\A_SPW_TOP|SPW|TX|always3~2_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout )) # (\A_SPW_TOP|SPW|TX|always3~2_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always3~3_combout & (
// !\A_SPW_TOP|SPW|TX|tx_dout_data~6_combout & ( (\A_SPW_TOP|SPW|TX|always3~2_combout & !\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always3~1_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|always3~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always3~3_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~7 .lut_mask = 64'h0F00CFC0AFA0CFC0;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~14 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~14_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~12_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_data~13_combout &
// \A_SPW_TOP|SPW|TX|tx_dout_data~8_combout )) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~12_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_data~13_combout &
// \A_SPW_TOP|SPW|TX|tx_dout_data~8_combout )) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~12_combout & !\A_SPW_TOP|SPW|TX|tx_dout_data~13_combout ) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~12_combout & (!\A_SPW_TOP|SPW|TX|tx_dout_data~13_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ) #
// (\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~12_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~13_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~14 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~14 .lut_mask = 64'h80C0C0C000C000C0;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~0_combout = ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( \A_SPW_TOP|SPW|TX|last_type.EOP~q & ( (\A_SPW_TOP|SPW|TX|always7~2_combout & (!\A_SPW_TOP|SPW|TX|always7~0_combout & (!\A_SPW_TOP|SPW|TX|always3~4_combout &
// !\A_SPW_TOP|SPW|TX|LessThan2~0_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|always7~1_combout & ( !\A_SPW_TOP|SPW|TX|last_type.EOP~q & ( (\A_SPW_TOP|SPW|TX|always7~2_combout & (!\A_SPW_TOP|SPW|TX|always7~0_combout & !\A_SPW_TOP|SPW|TX|LessThan2~0_combout
// )) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|always7~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|always7~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|always3~4_combout ),
.datad(!\A_SPW_TOP|SPW|TX|LessThan2~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|always7~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~0 .lut_mask = 64'h4400000040000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~15 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout = ( \A_SPW_TOP|SPW|TX|always3~4_combout & ( \A_SPW_TOP|tx_data|data_out [1] & ( (\A_SPW_TOP|SPW|TX|last_type.DATA~q ) # (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ) ) ) ) # ( \A_SPW_TOP|SPW|TX|always3~4_combout & (
// !\A_SPW_TOP|tx_data|data_out [1] & ( (((!\A_SPW_TOP|tx_data|data_out [0] & \A_SPW_TOP|SPW|TX|last_type.EOP~q )) # (\A_SPW_TOP|SPW|TX|last_type.DATA~q )) # (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ) ) ) )
.dataa(!\A_SPW_TOP|tx_data|data_out [0]),
.datab(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datac(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datad(!\A_SPW_TOP|SPW|TX|last_type.EOP~q ),
.datae(!\A_SPW_TOP|SPW|TX|always3~4_combout ),
.dataf(!\A_SPW_TOP|tx_data|data_out [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~15 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~15 .lut_mask = 64'h00003FBF00003F3F;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N51
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~4 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~4_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout~3_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ) # (!\A_SPW_TOP|SPW|TX|tx_dout~0_combout ))) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout~3_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout~0_combout ) # ((!\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout & \A_SPW_TOP|SPW|TX|tx_dout_data~14_combout )))) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout~0_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~4 .lut_mask = 64'hCC08CC08CC88CC88;
defparam \A_SPW_TOP|SPW|TX|tx_dout~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_sout~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_sout~2_combout = ( \A_SPW_TOP|SPW|TX|tx_sout~1_combout & ( \A_SPW_TOP|SPW|TX|tx_dout~4_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~9_combout & (!\A_SPW_TOP|SPW|TX|tx_sout~0_combout & \A_SPW_TOP|SPW|FSM|enable_tx~q )) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_sout~1_combout & ( \A_SPW_TOP|SPW|TX|tx_dout~4_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout~9_combout & (!\A_SPW_TOP|SPW|TX|tx_sout~0_combout & \A_SPW_TOP|SPW|FSM|enable_tx~q )) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_sout~1_combout & (
// !\A_SPW_TOP|SPW|TX|tx_dout~4_combout & ( (!\A_SPW_TOP|SPW|TX|tx_sout~0_combout & (\A_SPW_TOP|SPW|FSM|enable_tx~q & ((\A_SPW_TOP|SPW|TX|tx_dout~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_sout~1_combout & (
// !\A_SPW_TOP|SPW|TX|tx_dout~4_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout~5_combout & (!\A_SPW_TOP|SPW|TX|tx_dout~9_combout & (!\A_SPW_TOP|SPW|TX|tx_sout~0_combout & \A_SPW_TOP|SPW|FSM|enable_tx~q ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_sout~0_combout ),
.datad(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.datae(!\A_SPW_TOP|SPW|TX|tx_sout~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_sout~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_sout~2 .lut_mask = 64'h0080007000C00030;
defparam \A_SPW_TOP|SPW|TX|tx_sout~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N31
dffeas \A_SPW_TOP|SPW|TX|last_tx_sout (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|tx_sout~2_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_tx_sout~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_tx_sout .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_tx_sout .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~25 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~25_combout = ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] & ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] & ( (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] $
// (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2] $ (\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] & ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] & (
// (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2] $ (!\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout )))) ) ) ) # ( \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]
// & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] & ( (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] $ (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2] $ (!\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ))))
// ) ) ) # ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0] & ( !\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3] & ( (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1] $
// (!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2] $ (\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datab(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [1]),
.datac(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [2]),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ),
.datae(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [0]),
.dataf(!\A_SPW_TOP|SPW|TX|last_timein_control_flag_tx [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~25_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~25 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~25 .lut_mask = 64'h2882822882282882;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~25 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~24 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~24_combout = ( !\A_SPW_TOP|tx_data|data_out [1] & ( \A_SPW_TOP|SPW|TX|tx_dout_data~5_combout & ( (!\A_SPW_TOP|SPW|TX|last_type.DATA~q & (!\A_SPW_TOP|tx_data|data_out [8] & (\A_SPW_TOP|SPW|TX|last_type.TIMEC~q &
// !\A_SPW_TOP|tx_data|data_out [0]))) ) ) ) # ( !\A_SPW_TOP|tx_data|data_out [1] & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout & ( (!\A_SPW_TOP|tx_data|data_out [8] & (!\A_SPW_TOP|tx_data|data_out [0] & ((\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ) #
// (\A_SPW_TOP|SPW|TX|last_type.DATA~q )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|last_type.DATA~q ),
.datab(!\A_SPW_TOP|tx_data|data_out [8]),
.datac(!\A_SPW_TOP|SPW|TX|last_type.TIMEC~q ),
.datad(!\A_SPW_TOP|tx_data|data_out [0]),
.datae(!\A_SPW_TOP|tx_data|data_out [1]),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~24_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~24 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~24 .lut_mask = 64'h4C00000008000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~24 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~26 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~26_combout = ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout & ( (((!\A_SPW_TOP|SPW|TX|tx_dout_data~25_combout & \A_SPW_TOP|SPW|TX|tx_dout_data~24_combout )) #
// (\A_SPW_TOP|SPW|TX|tx_dout_data~10_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|Equal5~2_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ) #
// (\A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|Equal5~2_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~11_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~25_combout & \A_SPW_TOP|SPW|TX|tx_dout_data~24_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~25_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~24_combout ),
.datae(!\A_SPW_TOP|SPW|TX|Equal5~2_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~26 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~26 .lut_mask = 64'h000000F0777777F7;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~26 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_data~18 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_data~18_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ) #
// (\A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ) #
// (\A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ))) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout_data~26_combout & !\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout & ( (!\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & (((!\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout & \A_SPW_TOP|SPW|TX|tx_dout_data~0_combout )) #
// (\A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_data~1_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_data~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~18 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~18 .lut_mask = 64'h2F000F00AF00AF00;
defparam \A_SPW_TOP|SPW|TX|tx_dout_data~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~11 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~11_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_data~17_combout & ( \A_SPW_TOP|SPW|TX|tx_dout~3_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout & ( \A_SPW_TOP|SPW|TX|tx_dout~3_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout_data~17_combout & (
// !\A_SPW_TOP|SPW|TX|tx_dout~3_combout & ( ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout & \A_SPW_TOP|SPW|TX|tx_dout~0_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout~9_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout & (
// !\A_SPW_TOP|SPW|TX|tx_dout~3_combout & ( ((\A_SPW_TOP|SPW|TX|tx_dout~5_combout & (\A_SPW_TOP|SPW|TX|tx_dout~0_combout & \A_SPW_TOP|SPW|TX|tx_dout_data~18_combout ))) # (\A_SPW_TOP|SPW|TX|tx_dout~9_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout~0_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~18_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~11 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~11 .lut_mask = 64'h01FF11FF55FF55FF;
defparam \A_SPW_TOP|SPW|TX|tx_dout~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N8
dffeas \A_SPW_TOP|SPW|TX|last_tx_dout (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|tx_dout~11_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|last_tx_dout~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|last_tx_dout .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|last_tx_dout .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_sout~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_sout~1_combout = ( \A_SPW_TOP|SPW|TX|last_tx_dout~q & ( !\A_SPW_TOP|SPW|TX|last_tx_sout~q ) ) # ( !\A_SPW_TOP|SPW|TX|last_tx_dout~q & ( \A_SPW_TOP|SPW|TX|last_tx_sout~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|last_tx_sout~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|last_tx_dout~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_sout~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_sout~1 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \A_SPW_TOP|SPW|TX|tx_sout~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout~10 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout~10_combout = ( \A_SPW_TOP|SPW|TX|tx_dout~0_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~5_combout & ((\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~3_combout
// ))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~0_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~5_combout & \A_SPW_TOP|SPW|TX|tx_dout~3_combout ) ) ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout~0_combout & (
// !\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~5_combout & (((!\A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout~3_combout ))) ) ) ) # (
// !\A_SPW_TOP|SPW|TX|tx_dout~0_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout & ( (\A_SPW_TOP|SPW|TX|tx_dout~5_combout & \A_SPW_TOP|SPW|TX|tx_dout~3_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout~0_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout~10 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout~10 .lut_mask = 64'h1111515511111155;
defparam \A_SPW_TOP|SPW|TX|tx_dout~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N0
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_sout_e~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_sout_e~1_combout = ( \A_SPW_TOP|SPW|FSM|enable_tx~q & ( \A_SPW_TOP|SPW|TX|tx_dout~10_combout & ( ((!\A_SPW_TOP|SPW|TX|tx_sout~0_combout & \A_SPW_TOP|SPW|TX|tx_sout~1_combout )) # (\A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ) ) ) ) # (
// !\A_SPW_TOP|SPW|FSM|enable_tx~q & ( \A_SPW_TOP|SPW|TX|tx_dout~10_combout & ( \A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ) ) ) # ( \A_SPW_TOP|SPW|FSM|enable_tx~q & ( !\A_SPW_TOP|SPW|TX|tx_dout~10_combout & ( ((!\A_SPW_TOP|SPW|TX|tx_sout~0_combout &
// (!\A_SPW_TOP|SPW|TX|tx_dout~9_combout $ (\A_SPW_TOP|SPW|TX|tx_sout~1_combout )))) # (\A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ) ) ) ) # ( !\A_SPW_TOP|SPW|FSM|enable_tx~q & ( !\A_SPW_TOP|SPW|TX|tx_dout~10_combout & ( \A_SPW_TOP|SPW|TX|tx_sout_e~0_combout
// ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_sout~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_sout~1_combout ),
.datae(!\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_sout_e~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout_e~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_sout_e~1 .lut_mask = 64'h0F0F8F2F0F0F0FAF;
defparam \A_SPW_TOP|SPW|TX|tx_sout_e~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N50
dffeas \A_SPW_TOP|SPW|TX|tx_sout_e (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|tx_sout_e~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_sout_e .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_sout_e .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N27
cyclonev_lcell_comb \m_x|always3~0 (
// Equation(s):
// \m_x|always3~0_combout = LCELL(( \A_SPW_TOP|SPW|TX|tx_dout_e~q & ( !\A_SPW_TOP|SPW|TX|tx_sout_e~q ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_e~q & ( \A_SPW_TOP|SPW|TX|tx_sout_e~q ) ))
.dataa(!\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always3~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always3~0 .extended_lut = "off";
defparam \m_x|always3~0 .lut_mask = 64'h55555555AAAAAAAA;
defparam \m_x|always3~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y8_N45
cyclonev_lcell_comb \m_x|control_r[1]~feeder (
// Equation(s):
// \m_x|control_r[1]~feeder_combout = ( \m_x|bit_c_1~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_c_1~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_r[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_r[1]~feeder .extended_lut = "off";
defparam \m_x|control_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y8_N47
dffeas \m_x|control_r[1] (
.clk(\m_x|always1~0_combout ),
.d(\m_x|control_r[1]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[1] .is_wysiwyg = "true";
defparam \m_x|control_r[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X35_Y8_N15
cyclonev_lcell_comb \m_x|control_p_r[1]~feeder (
// Equation(s):
// \m_x|control_p_r[1]~feeder_combout = ( \m_x|control_r [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control_r [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_p_r[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_p_r[1]~feeder .extended_lut = "off";
defparam \m_x|control_p_r[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_p_r[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y8_N16
dffeas \m_x|control_p_r[1] (
.clk(\m_x|always2~0_combout ),
.d(\m_x|control_p_r[1]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_p_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[1] .is_wysiwyg = "true";
defparam \m_x|control_p_r[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N29
dffeas \m_x|control[1] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control_p_r [1]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control[1] .is_wysiwyg = "true";
defparam \m_x|control[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N32
dffeas \m_x|control_l_r[1] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [1]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_l_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[1] .is_wysiwyg = "true";
defparam \m_x|control_l_r[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N33
cyclonev_lcell_comb \m_x|info[11]~feeder (
// Equation(s):
// \m_x|info[11]~feeder_combout = ( \m_x|control_l_r [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control_l_r [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|info[11]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|info[11]~feeder .extended_lut = "off";
defparam \m_x|info[11]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|info[11]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N34
dffeas \m_x|info[11] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|info[11]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [11]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[11] .is_wysiwyg = "true";
defparam \m_x|info[11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N54
cyclonev_lcell_comb \u0|data_info|read_mux_out[11] (
// Equation(s):
// \u0|data_info|read_mux_out [11] = (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \m_x|info [11]))
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\m_x|info [11]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [11]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[11] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[11] .lut_mask = 64'h0808080808080808;
defparam \u0|data_info|read_mux_out[11] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N56
dffeas \u0|data_info|readdata[11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [11]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [11]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[11] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[11] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y10_N20
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [11]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[11] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N37
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [11]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .lut_mask = 64'h1111111105050505;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~32 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( (\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & (\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .lut_mask = 64'h0000000001010101;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h5000A0F05303A3F3;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout
// & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout
// ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0000FFFF8000FFFF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N38
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout = (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h404F404F40404040;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N41
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h1010101015151515;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N8
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y20_N1
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h5055505550005000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N11
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y20_N55
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h8F808F8080808080;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [0]) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0404040415151515;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N47
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N47
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]
// & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout )) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hABABABABEFEFEFEF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 .lut_mask = 64'h3333000033330000;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N8
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0B0B0B0B08080808;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N22
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N50
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000CCF0CCF0;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N23
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000000005000;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout
// ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h02AA02AAFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y20_N20
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N14
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h5140514051515151;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N29
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]))) ) ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0101ABAB01ABABAB;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N59
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y8_N36
cyclonev_lcell_comb \m_x|control_r[0]~feeder (
// Equation(s):
// \m_x|control_r[0]~feeder_combout = ( \m_x|bit_c_0~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_c_0~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|control_r[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|control_r[0]~feeder .extended_lut = "off";
defparam \m_x|control_r[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|control_r[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y8_N38
dffeas \m_x|control_r[0] (
.clk(\m_x|always1~0_combout ),
.d(\m_x|control_r[0]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_r [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_r[0] .is_wysiwyg = "true";
defparam \m_x|control_r[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X35_Y8_N43
dffeas \m_x|control_p_r[0] (
.clk(\m_x|always2~0_combout ),
.d(gnd),
.asdata(\m_x|control_r [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_p_r [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_p_r[0] .is_wysiwyg = "true";
defparam \m_x|control_p_r[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N59
dffeas \m_x|control[0] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control_p_r [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control[0] .is_wysiwyg = "true";
defparam \m_x|control[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X32_Y7_N53
dffeas \m_x|control_l_r[0] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|control_l_r [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|control_l_r[0] .is_wysiwyg = "true";
defparam \m_x|control_l_r[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N30
cyclonev_lcell_comb \m_x|info[10]~feeder (
// Equation(s):
// \m_x|info[10]~feeder_combout = ( \m_x|control_l_r [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control_l_r [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|info[10]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|info[10]~feeder .extended_lut = "off";
defparam \m_x|info[10]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|info[10]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N32
dffeas \m_x|info[10] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|info[10]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [10]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[10] .is_wysiwyg = "true";
defparam \m_x|info[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N33
cyclonev_lcell_comb \u0|data_info|read_mux_out[10] (
// Equation(s):
// \u0|data_info|read_mux_out [10] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \m_x|info [10] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\m_x|info [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [10]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[10] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[10] .lut_mask = 64'h00000000F0F00000;
defparam \u0|data_info|read_mux_out[10] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N34
dffeas \u0|data_info|readdata[10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [10]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [10]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[10] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[10] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N8
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [10]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[10] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N5
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N29
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & (
// (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q & (
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [10]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 .lut_mask = 64'h0000555505050505;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~31 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 .lut_mask = 64'h00AA00AA00000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout & ((\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARBURST [0])))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout & (
// (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout & ((\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]) # (\u0|hps_0|fpga_interfaces|h2f_ARBURST [0])))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 .lut_mask = 64'h0007000700700070;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARBURST [1] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ) # (\u0|hps_0|fpga_interfaces|h2f_ARBURST [0])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARBURST [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2 .lut_mask = 64'h008C008C00CC00CC;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N17
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout & (
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N26
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ( ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1F1F00001F1F00FF;
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y20_N5
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X33_Y7_N40
dffeas \m_x|info[9] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [3]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [9]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[9] .is_wysiwyg = "true";
defparam \m_x|info[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N9
cyclonev_lcell_comb \u0|data_info|read_mux_out[9] (
// Equation(s):
// \u0|data_info|read_mux_out [9] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \m_x|info [9] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\m_x|info [9]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [9]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[9] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[9] .lut_mask = 64'h00000000F0F00000;
defparam \u0|data_info|read_mux_out[9] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N11
dffeas \u0|data_info|readdata[9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [9]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [9]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[9] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder_combout = \u0|data_info|readdata [9]
.dataa(gnd),
.datab(gnd),
.datac(!\u0|data_info|readdata [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N35
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N53
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9] ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [9]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 .lut_mask = 64'h0055005505050505;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~30 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]
// & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_010|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[82] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_010|src_data [82]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|src_data [82]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y22_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_010|src_data [86] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_data [86] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0500050005550555;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y22_N58
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y22_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [3] ) + ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout &
// ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])))) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout
// )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [3]))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1D1D1D1D1DDD1DDD;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N59
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N51
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[8] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [8] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|write_data_fifo_tx|data_out [8]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\u0|write_data_fifo_tx|data_out [8]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [8]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[8] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[8] .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|write_data_fifo_tx|readdata[8] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [8]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|comb~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|comb~0_combout = ( \A_SPW_TOP|SPW|RX|rx_buffer_write~q & ( (!\A_SPW_TOP|rx_data|f_full~q & (!\A_SPW_TOP|rx_data|block_write~q & (!\db_system_spwulight_b|aux_pb~q & \A_SPW_TOP|SPW|FSM|state_fsm.run~q ))) ) )
.dataa(!\A_SPW_TOP|rx_data|f_full~q ),
.datab(!\A_SPW_TOP|rx_data|block_write~q ),
.datac(!\db_system_spwulight_b|aux_pb~q ),
.datad(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|comb~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|comb~0 .lut_mask = 64'h0000000000800080;
defparam \A_SPW_TOP|rx_data|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|block_read~_wirecell (
// Equation(s):
// \A_SPW_TOP|rx_data|block_read~_wirecell_combout = ( !\A_SPW_TOP|rx_data|block_read~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|block_read~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|block_read~_wirecell_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|block_read~_wirecell .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|block_read~_wirecell .lut_mask = 64'hFFFFFFFF00000000;
defparam \A_SPW_TOP|rx_data|block_read~_wirecell .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout = ( \A_SPW_TOP|SPW|RX|control [1] & ( \A_SPW_TOP|SPW|RX|dta_timec_p [0] & ( ((\A_SPW_TOP|SPW|RX|control [2] & !\A_SPW_TOP|SPW|RX|control [0])) # (\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) ) ) ) # (
// !\A_SPW_TOP|SPW|RX|control [1] & ( \A_SPW_TOP|SPW|RX|dta_timec_p [0] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) ) ) # ( \A_SPW_TOP|SPW|RX|control [1] & ( !\A_SPW_TOP|SPW|RX|dta_timec_p [0] & ( (!\A_SPW_TOP|SPW|RX|ready_data_p_r~q &
// (\A_SPW_TOP|SPW|RX|control [2] & !\A_SPW_TOP|SPW|RX|control [0])) ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(!\A_SPW_TOP|SPW|RX|control [2]),
.datac(!\A_SPW_TOP|SPW|RX|control [0]),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|RX|control [1]),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~0 .lut_mask = 64'h0000202055557575;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout = ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q & ( (((!\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ) # ((\A_SPW_TOP|SPW|RX|last_is_data~q ))) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q )) ) ) # (
// \A_SPW_TOP|SPW|RX|ready_data_p_r~q & ( ((\A_SPW_TOP|SPW|RX|control [0] & (\A_SPW_TOP|SPW|RX|control [2] & ((\A_SPW_TOP|SPW|RX|control [1]))))) # (\A_SPW_TOP|SPW|RX|ready_control_p_r~q ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|control [0]),
.datab(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.datac(!\A_SPW_TOP|SPW|RX|control [2]),
.datad(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.datae(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.dataf(!\A_SPW_TOP|SPW|RX|control [1]),
.datag(!\A_SPW_TOP|SPW|RX|rx_data_take~0_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9 .extended_lut = "on";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9 .lut_mask = 64'hF3FF3333F3FF3737;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N20
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[0] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|wr_ptr[0]~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|wr_ptr[0]~0_combout = !\A_SPW_TOP|rx_data|wr_ptr [0]
.dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[0]~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|wr_ptr[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \A_SPW_TOP|rx_data|wr_ptr[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N53
dffeas \A_SPW_TOP|rx_data|wr_ptr[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|wr_ptr [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add4~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add4~1_combout = !\A_SPW_TOP|rx_data|wr_ptr [1] $ (!\A_SPW_TOP|rx_data|wr_ptr [0])
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|wr_ptr [1]),
.datad(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add4~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add4~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add4~1 .lut_mask = 64'h0FF00FF00FF00FF0;
defparam \A_SPW_TOP|rx_data|Add4~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N20
dffeas \A_SPW_TOP|rx_data|wr_ptr[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add4~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|wr_ptr [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add4~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add4~2_combout = !\A_SPW_TOP|rx_data|wr_ptr [2] $ (((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (!\A_SPW_TOP|rx_data|wr_ptr [1])))
.dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
.datad(!\A_SPW_TOP|rx_data|wr_ptr [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add4~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add4~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add4~2 .lut_mask = 64'h0F5A0F5A0F5A0F5A;
defparam \A_SPW_TOP|rx_data|Add4~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N23
dffeas \A_SPW_TOP|rx_data|wr_ptr[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add4~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|wr_ptr [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add4~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add4~3_combout = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [3] $ (((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (!\A_SPW_TOP|rx_data|wr_ptr [2]))) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [3] ) )
.dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|wr_ptr [3]),
.datad(!\A_SPW_TOP|rx_data|wr_ptr [2]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add4~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add4~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add4~3 .lut_mask = 64'h0F0F0F0F0F5A0F5A;
defparam \A_SPW_TOP|rx_data|Add4~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N8
dffeas \A_SPW_TOP|rx_data|wr_ptr[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add4~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|wr_ptr [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add4~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add4~4_combout = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [4] $ (((!\A_SPW_TOP|rx_data|wr_ptr [2]) # ((!\A_SPW_TOP|rx_data|wr_ptr [0]) # (!\A_SPW_TOP|rx_data|wr_ptr [3])))) ) ) # ( !\A_SPW_TOP|rx_data|wr_ptr [1] &
// ( \A_SPW_TOP|rx_data|wr_ptr [4] ) )
.dataa(!\A_SPW_TOP|rx_data|wr_ptr [2]),
.datab(!\A_SPW_TOP|rx_data|wr_ptr [4]),
.datac(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.datad(!\A_SPW_TOP|rx_data|wr_ptr [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add4~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add4~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add4~4 .lut_mask = 64'h3333333333363336;
defparam \A_SPW_TOP|rx_data|Add4~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N14
dffeas \A_SPW_TOP|rx_data|wr_ptr[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add4~4_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|wr_ptr [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|Add4~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|Add4~0_combout = ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|wr_ptr [0]) # ((!\A_SPW_TOP|rx_data|wr_ptr [3]) # ((!\A_SPW_TOP|rx_data|wr_ptr [2]) # (!\A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )
// # ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( \A_SPW_TOP|rx_data|wr_ptr [5] ) ) # ( \A_SPW_TOP|rx_data|wr_ptr [1] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (\A_SPW_TOP|rx_data|wr_ptr [0] & (\A_SPW_TOP|rx_data|wr_ptr [3] & (\A_SPW_TOP|rx_data|wr_ptr [2] &
// \A_SPW_TOP|rx_data|wr_ptr [4]))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
.datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
.datad(!\A_SPW_TOP|rx_data|wr_ptr [4]),
.datae(!\A_SPW_TOP|rx_data|wr_ptr [1]),
.dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|Add4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|Add4~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|Add4~0 .lut_mask = 64'h00000001FFFFFFFE;
defparam \A_SPW_TOP|rx_data|Add4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y11_N41
dffeas \A_SPW_TOP|rx_data|wr_ptr[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|Add4~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~12_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|wr_ptr [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|wr_ptr[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|wr_ptr[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N45
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~1 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~1_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [1] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~1 .lut_mask = 64'h0000000055555555;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N47
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[1] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N6
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~2 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~2_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [2] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N8
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[2] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N39
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~3 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [3] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~3 .lut_mask = 64'h0000000055555555;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N41
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[3] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N24
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~4 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [4] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~4 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~4 .lut_mask = 64'h0000000055555555;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N26
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[4] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~5 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout = (\A_SPW_TOP|SPW|RX|ready_data_p_r~q & \A_SPW_TOP|SPW|RX|dta_timec_p [5])
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|RX|dta_timec_p [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~5 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~5 .lut_mask = 64'h0055005500550055;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N29
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[5] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N54
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~6 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [6] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~6 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~6 .lut_mask = 64'h0000000055555555;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N56
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[6] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N57
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~7 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [7] & ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~7 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~7 .lut_mask = 64'h0000000055555555;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N59
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[7] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y14_N48
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_data_flag~8 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout = ( \A_SPW_TOP|SPW|RX|dta_timec_p [8] ) # ( !\A_SPW_TOP|SPW|RX|dta_timec_p [8] & ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|dta_timec_p [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~8 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~8 .lut_mask = 64'hF0F0F0F0FFFFFFFF;
defparam \A_SPW_TOP|SPW|RX|rx_data_flag~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y14_N50
dffeas \A_SPW_TOP|SPW|RX|rx_data_flag[8] (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(\A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_data_flag[8] .power_up = "low";
// synopsys translate_on
// Location: M10K_X20_Y12_N0
cyclonev_ram_block \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 (
.portawe(\A_SPW_TOP|rx_data|comb~0_combout ),
.portare(vcc),
.portaaddrstall(gnd),
.portbwe(gnd),
.portbre(vcc),
.portbaddrstall(!\A_SPW_TOP|rx_data|block_read~_wirecell_combout ),
.clk0(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.clk1(gnd),
.ena0(vcc),
.ena1(vcc),
.ena2(vcc),
.ena3(vcc),
.clr0(gnd),
.clr1(gnd),
.nerror(vcc),
.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\A_SPW_TOP|SPW|RX|rx_data_flag [8],\A_SPW_TOP|SPW|RX|rx_data_flag [7],\A_SPW_TOP|SPW|RX|rx_data_flag [6],\A_SPW_TOP|SPW|RX|rx_data_flag [5],\A_SPW_TOP|SPW|RX|rx_data_flag [4],
\A_SPW_TOP|SPW|RX|rx_data_flag [3],\A_SPW_TOP|SPW|RX|rx_data_flag [2],\A_SPW_TOP|SPW|RX|rx_data_flag [1],\A_SPW_TOP|SPW|RX|rx_data_flag [0]}),
.portaaddr({\A_SPW_TOP|rx_data|wr_ptr [5],\A_SPW_TOP|rx_data|wr_ptr [4],\A_SPW_TOP|rx_data|wr_ptr [3],\A_SPW_TOP|rx_data|wr_ptr [2],\A_SPW_TOP|rx_data|wr_ptr [1],\A_SPW_TOP|rx_data|wr_ptr [0]}),
.portabyteenamasks(1'b1),
.portbdatain(40'b0000000000000000000000000000000000000000),
.portbaddr({\A_SPW_TOP|rx_data|rd_ptr~0_combout ,\A_SPW_TOP|rx_data|rd_ptr~5_combout ,\A_SPW_TOP|rx_data|rd_ptr~4_combout ,\A_SPW_TOP|rx_data|rd_ptr~3_combout ,\A_SPW_TOP|rx_data|rd_ptr~2_combout ,\A_SPW_TOP|rx_data|rd_ptr~1_combout }),
.portbbyteenamasks(1'b1),
.devclrn(devclrn),
.devpor(devpor),
.portadataout(),
.portbdataout(\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ),
.eccstatus(),
.dftout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .logical_ram_name = "spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|altsyncram:mem_rtl_0|altsyncram_pfo1:auto_generated|ALTSYNCRAM";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "old";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .operation_mode = "dual_port";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_address_width = 6;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_data_width = 40;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_last_address = 63;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_clear = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_address_width = 6;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_data_width = 40;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_first_address = 0;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_last_address = 63;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_logical_ram_width = 9;
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0";
defparam \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0 .ram_block_type = "M20K";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem~0feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem~0feeder_combout = VCC
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem~0feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~0feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem~0feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem~0feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N5
dffeas \A_SPW_TOP|rx_data|mem~0 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem~0feeder_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~0_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~0 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~0 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|mem~14_combout = ( !\A_SPW_TOP|rx_data|wr_ptr [4] & ( !\A_SPW_TOP|rx_data|wr_ptr [1] & ( (\A_SPW_TOP|SPW|RX|rx_buffer_write~q & (!\A_SPW_TOP|rx_data|wr_ptr [3] & (!\A_SPW_TOP|rx_data|wr_ptr [2] & !\db_system_spwulight_b|aux_pb~q ))) )
// ) )
.dataa(!\A_SPW_TOP|SPW|RX|rx_buffer_write~q ),
.datab(!\A_SPW_TOP|rx_data|wr_ptr [3]),
.datac(!\A_SPW_TOP|rx_data|wr_ptr [2]),
.datad(!\db_system_spwulight_b|aux_pb~q ),
.datae(!\A_SPW_TOP|rx_data|wr_ptr [4]),
.dataf(!\A_SPW_TOP|rx_data|wr_ptr [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem~14 .lut_mask = 64'h4000000000000000;
defparam \A_SPW_TOP|rx_data|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y11_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|mem~13_combout = ( !\A_SPW_TOP|rx_data|wr_ptr [0] & ( !\A_SPW_TOP|rx_data|wr_ptr [5] & ( (!\A_SPW_TOP|rx_data|f_full~q & (!\A_SPW_TOP|rx_data|block_write~q & (\A_SPW_TOP|SPW|FSM|state_fsm.run~q & \A_SPW_TOP|rx_data|mem~14_combout
// ))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|f_full~q ),
.datab(!\A_SPW_TOP|rx_data|block_write~q ),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datad(!\A_SPW_TOP|rx_data|mem~14_combout ),
.datae(!\A_SPW_TOP|rx_data|wr_ptr [0]),
.dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem~13 .lut_mask = 64'h0008000000000000;
defparam \A_SPW_TOP|rx_data|mem~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N47
dffeas \A_SPW_TOP|rx_data|mem~9 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~9_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~9 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~9 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~16 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~16_combout = ( \A_SPW_TOP|rx_data|mem~9_q & ( (!\A_SPW_TOP|rx_data|mem~0_q ) # (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 ) ) ) # ( !\A_SPW_TOP|rx_data|mem~9_q & (
// (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 & \A_SPW_TOP|rx_data|mem~0_q ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|rx_data|mem~0_q ),
.datae(!\A_SPW_TOP|rx_data|mem~9_q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~16 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~16 .lut_mask = 64'h0055FF550055FF55;
defparam \A_SPW_TOP|rx_data|data_out~16 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N18
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder_combout = ( \A_SPW_TOP|rx_data|wr_ptr [5] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|wr_ptr [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N20
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N21
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder_combout = ( \A_SPW_TOP|rx_data|comb~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N22
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N1
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|wr_ptr [1]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N58
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|wr_ptr [0]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y12_N44
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~2_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y12_N41
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~1_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|mem~10_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [2] & ( (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [0] & (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [1] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [3] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass
// [4])))) ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [2] & ( (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [0] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [1] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [3] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [4])))) ) )
.dataa(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [0]),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [3]),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [1]),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [4]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem~10 .lut_mask = 64'h4010401004010401;
defparam \A_SPW_TOP|rx_data|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N26
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[21] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [8]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [21]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[21] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[21] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y12_N26
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~3_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N4
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[9] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|wr_ptr [4]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [9]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[9] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[9] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y12_N29
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~4_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[8] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N28
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|wr_ptr [2]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y12_N56
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[10] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~5_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [10]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[10] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[10] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N56
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|wr_ptr [3]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|mem~11_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [10] & ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [7] & ( (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [9] & (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [8] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [6]
// $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [10] & ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [7] & ( (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [9] & (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [8] &
// (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [6] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [5])))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [10] & ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [7] & ( (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [9] &
// (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [8] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [6] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [5])))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [10] & ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [7] & (
// (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [9] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [8] & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [6] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [5])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [6]),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [9]),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [8]),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [5]),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [10]),
.dataf(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem~11 .lut_mask = 64'h8040201008040201;
defparam \A_SPW_TOP|rx_data|mem~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y12_N59
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[12] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|rx_data|rd_ptr~0_combout ),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|rx_data|block_read~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[12] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[12] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N42
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~17 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~17_combout = ( \A_SPW_TOP|rx_data|mem~11_combout & ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [12] & ( (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] & (\A_SPW_TOP|rx_data|data_out~16_combout )) # (\A_SPW_TOP|rx_data|mem_rtl_0_bypass
// [11] & ((!\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|data_out~16_combout )) # (\A_SPW_TOP|rx_data|mem~10_combout & ((\A_SPW_TOP|rx_data|mem_rtl_0_bypass [21]))))) ) ) ) # ( !\A_SPW_TOP|rx_data|mem~11_combout & (
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass [12] & ( \A_SPW_TOP|rx_data|data_out~16_combout ) ) ) # ( \A_SPW_TOP|rx_data|mem~11_combout & ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12] & ( (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] &
// ((!\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|data_out~16_combout )) # (\A_SPW_TOP|rx_data|mem~10_combout & ((\A_SPW_TOP|rx_data|mem_rtl_0_bypass [21]))))) # (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] &
// (\A_SPW_TOP|rx_data|data_out~16_combout )) ) ) ) # ( !\A_SPW_TOP|rx_data|mem~11_combout & ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12] & ( \A_SPW_TOP|rx_data|data_out~16_combout ) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out~16_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [21]),
.datae(!\A_SPW_TOP|rx_data|mem~11_combout ),
.dataf(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~17 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~17 .lut_mask = 64'h5555515D55555457;
defparam \A_SPW_TOP|rx_data|data_out~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y12_N45
cyclonev_lcell_comb \A_SPW_TOP|rx_data|always1~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|always1~0_combout = ( \A_SPW_TOP|rx_data|block_read~q ) # ( !\A_SPW_TOP|rx_data|block_read~q & ( (!\u0|data_read_en_rx|data_out~q ) # (!\A_SPW_TOP|rx_data|f_empty~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|data_read_en_rx|data_out~q ),
.datad(!\A_SPW_TOP|rx_data|f_empty~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|block_read~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|always1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|always1~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|always1~0 .lut_mask = 64'hFFF0FFF0FFFFFFFF;
defparam \A_SPW_TOP|rx_data|always1~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N43
dffeas \A_SPW_TOP|rx_data|data_out[8] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~17_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [8]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[8] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[8] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y34_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N8
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h058D058D00880088;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hD580D58080808080;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0404040415151515;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000000200020;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])
// # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0D0D0D0D08080808;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hFF05FF05FFF5FFF5;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & !\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0A0A0A0A0F000F00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N58
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])))) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout
// ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )
// ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0FAF0FAF2FAF2FAF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout = (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 .lut_mask = 64'h3300330033003300;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y34_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h0F030F030C000C00;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & (
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) ) ) #
// ( !\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h37003700370037FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_003|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000033553355;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N55
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X8_Y34_N1
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]))))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00AC00AC00AF00AF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N16
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) ) # (
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000F1111FFFF1111;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y34_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N33
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[8] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [8] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [8] ) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out [8]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [8]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[8] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[8] .lut_mask = 64'h5555000000000000;
defparam \u0|data_flag_rx|read_mux_out[8] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N35
dffeas \u0|data_flag_rx|readdata[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [8]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[8] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[8] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N34
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [8]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 .lut_mask = 64'h303030303F3F3F3F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFF0FFF0FFF0FFF0F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N35
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y18_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N36
cyclonev_lcell_comb \m_x|info[8]~feeder (
// Equation(s):
// \m_x|info[8]~feeder_combout = ( \m_x|control [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|info[8]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|info[8]~feeder .extended_lut = "off";
defparam \m_x|info[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|info[8]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N37
dffeas \m_x|info[8] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|info[8]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [8]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[8] .is_wysiwyg = "true";
defparam \m_x|info[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N12
cyclonev_lcell_comb \u0|data_info|read_mux_out[8] (
// Equation(s):
// \u0|data_info|read_mux_out [8] = ( \m_x|info [8] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [8]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[8] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[8] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[8] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N13
dffeas \u0|data_info|readdata[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [8]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[8] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[8] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N19
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [8]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N34
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout &
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q )) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ((\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [8]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 .lut_mask = 64'h0000000027272727;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & (!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [8]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 .lut_mask = 64'hFD5DFD5D00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & (
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ) # (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ) #
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q & (
// !\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q & (
// !\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [8]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 .lut_mask = 64'hF0F0F0F0F0F5FFF5;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) # (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFAFAFAFAAAAAAAAA;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y30_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & ( (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .lut_mask = 64'h37FFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h5050505050FF50FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// (((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h000000000EEE0EEE;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h3737373700000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .lut_mask = 64'h000000003FFF3FFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout = (\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & \u0|hps_0|fpga_interfaces|h2f_RREADY [0])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0A0A0A0A0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0FBF0FBF0FFF0FFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00F300F3515D515D;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ))
// ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hEEEEEEEEAEAEAEAE;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) )
// )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h50A050A05CAC5CAC;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N43
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h4400BB00440FBB0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hFF00FF005FA05FA0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hCC00CC00CF03CF03;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout &
// ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))
// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h01CD01CDCD01CD01;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h3000CF003055CF55;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h4F0F0F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y31_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
.datag(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F470F0F0F550F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00FF00FF08880888;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))
// # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1B33FFFF1B330303;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .lut_mask = 64'h00FF00FF30FC30FC;
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N50
dffeas \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout = (!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (((!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout &
// ((!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))))
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .lut_mask = 64'hE0F1E0F1E0F1E0F1;
defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y31_N11
dffeas \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// ((\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF0011F0F1;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00F800F800000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) #
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used
// [1])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) #
// ((\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h2322202233220022;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFEFFFEFF00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F1F0F1F00110011;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N53
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y30_N34
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout = (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0444044404440444;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000003030303;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] &
// !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000030303030;
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y31_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout
// )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 .lut_mask = 64'h3300330033003300;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000E2F3E2F3;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N37
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y33_N16
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_001|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h083B083B08080808;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h1111111100330033;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout & !\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'hC0C0C0C0AA00AA00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h00000000505F505F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & !\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h3030303033003300;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N14
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant
// [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N32
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout = (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout
// )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 .lut_mask = 64'h0F000F000F000F00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0C0C0C0C0F000F00;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N2
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ) #
// (\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ) # ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hFF03FF03FFCFFFCF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N7
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datag(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h555F0000555F3030;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N49
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0010001000000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h04CC04CCFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N56
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF00000000FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant
// [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ) # (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))
// ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00FA00FA000A000A;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N5
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0303FFFF00550055;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y33_N55
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y33_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) ) ) ) #
// ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datae(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h00CC11DD0CCC1DDD;
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y33_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y33_N59
dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N57
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[7] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [7] = ( \A_SPW_TOP|SPW|RX|timecode [7] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|timecode [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [7]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[7] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[7] .lut_mask = 64'h0000000088888888;
defparam \u0|timecode_rx|read_mux_out[7] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N59
dffeas \u0|timecode_rx|readdata[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [7]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[7] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [7]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y18_N17
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7])) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q )))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q )) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] &
// ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 .lut_mask = 64'h2070207030303030;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder_combout = ( \A_SPW_TOP|SPW|RX|rx_data_flag [7] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N55
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [20]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N53
dffeas \A_SPW_TOP|rx_data|mem~8 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [7]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~8_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~8 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~8 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~14 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~14_combout = (!\A_SPW_TOP|rx_data|mem~0_q & ((\A_SPW_TOP|rx_data|mem~8_q ))) # (\A_SPW_TOP|rx_data|mem~0_q & (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a7 ))
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a7 ),
.datad(!\A_SPW_TOP|rx_data|mem~8_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~14 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~14 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|rx_data|data_out~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N57
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~15 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~15_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [20] & ( \A_SPW_TOP|rx_data|data_out~14_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [20] & ( \A_SPW_TOP|rx_data|data_out~14_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [20] & (
// !\A_SPW_TOP|rx_data|data_out~14_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datad(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [20]),
.dataf(!\A_SPW_TOP|rx_data|data_out~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~15 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~15 .lut_mask = 64'h00000041FFBEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N58
dffeas \A_SPW_TOP|rx_data|data_out[7] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~15_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [7]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[7] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N51
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[7] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [7] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [7] ) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out [7]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [7]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[7] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[7] .lut_mask = 64'h5555000000000000;
defparam \u0|data_flag_rx|read_mux_out[7] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N52
dffeas \u0|data_flag_rx|readdata[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [7]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[7] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N50
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [7]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N59
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7] & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout )))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7] & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 .lut_mask = 64'h55D555D55DDD5DDD;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N48
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[7] (
// Equation(s):
// \u0|timecode_tx_data|readdata [7] = ( \u0|timecode_tx_data|data_out [7] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|timecode_tx_data|data_out [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [7]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[7] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[7] .lut_mask = 64'h00000000F000F000;
defparam \u0|timecode_tx_data|readdata[7] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [7]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y16_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N56
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 .lut_mask = 64'h000B000B040F040F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N58
dffeas \m_x|info[7] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [1]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [7]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[7] .is_wysiwyg = "true";
defparam \m_x|info[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N36
cyclonev_lcell_comb \u0|data_info|read_mux_out[7] (
// Equation(s):
// \u0|data_info|read_mux_out [7] = ( \m_x|info [7] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [7]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[7] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[7] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[7] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N38
dffeas \u0|data_info|readdata[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [7]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[7] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y10_N37
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [7]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N33
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[7] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [7] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|write_data_fifo_tx|data_out [7] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\u0|write_data_fifo_tx|data_out [7]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [7]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[7] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[7] .lut_mask = 64'h5050505000000000;
defparam \u0|write_data_fifo_tx|readdata[7] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [7]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y18_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q & (
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [7]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 .lut_mask = 64'h000000000505AFAF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N29
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q &
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ) ) ) #
// ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7] & \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [7]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 .lut_mask = 64'h777F777FFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [19] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [19] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 .lut_mask = 64'h05050505AFAFAFAF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [18])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54
// ))
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 = CARRY(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [18])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54
// ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [18]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ),
.cout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 .lut_mask = 64'h0000FFFF00000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout = SUM(( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|hps_0|fpga_interfaces|h2f_AWADDR [19])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]))) ) + ( GND ) + ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2
// ))
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 .lut_mask = 64'h0000FFFF00000A5F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N23
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[19] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[19] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[19] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal14~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal14~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((\u0|hps_0|fpga_interfaces|h2f_AWADDR [19])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [19]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [19]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [18]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal14~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal14~0 .lut_mask = 64'h1B0A1B0A11001100;
defparam \u0|mm_interconnect_0|router|Equal14~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal16~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal16~0_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|router|Equal14~0_combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal16~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal16~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal16~0 .lut_mask = 64'h0000000005050000;
defparam \u0|mm_interconnect_0|router|Equal16~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y27_N38
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router|Equal16~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [10]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src10_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [10]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [10]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src10_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src10_valid~0 .lut_mask = 64'h0F0F0F0F000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|src10_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout = !\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ) # (((!\u0|mm_interconnect_0|router|Equal7~6_combout ) # (!\u0|mm_interconnect_0|router|Equal14~0_combout )) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout )) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 .lut_mask = 64'hFFFFFFFB00000000;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & (
// \u0|mm_interconnect_0|cmd_mux_010|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & (
// (\u0|mm_interconnect_0|cmd_mux_010|src_payload [0] & \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout &
// ((!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout & (\u0|mm_interconnect_0|cmd_mux_010|src_payload [0])) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout &
// (((!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout & (\u0|mm_interconnect_0|cmd_mux_010|src_payload [0] &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 .lut_mask = 64'hCC05CC5505055555;
defparam \u0|mm_interconnect_0|cmd_mux_010|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y25_N41
dffeas \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_010|src_payload [0] & ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_010|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout & ((!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout & (!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_payload [0] & (
// !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout & (!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q & !\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_010|src_payload [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 .lut_mask = 64'h880088A00000A0A0;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y25_N23
dffeas \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y25_N4
dffeas \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|router|Equal16~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout &
// ((!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|router|Equal16~0_combout & (
// (\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout & !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
.datae(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|router|Equal16~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 .lut_mask = 64'h000000000F000F0A;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y25_N35
dffeas \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB
// [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[34] .lut_mask = 64'h000F000FFFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_010|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 .lut_mask = 64'h8800000080000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .lut_mask = 64'h0020F0F02000F0F0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF0F0F0F0FFFFFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout =
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h50FF50FF50FF50FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0C3F0C3F4C7F4C7F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h030203020F0A0F0A;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout = (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0055005500550055;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0FDF0FDF0FFF0FFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) #
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used
// [0] ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y22_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q )))
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N12
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[6] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [6] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|write_data_fifo_tx|data_out [6] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(!\u0|write_data_fifo_tx|data_out [6]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [6]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[6] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[6] .lut_mask = 64'h3300330000000000;
defparam \u0|write_data_fifo_tx|readdata[6] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [6]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y18_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N5
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [6]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 .lut_mask = 64'h0000555505050505;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N39
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[6] (
// Equation(s):
// \u0|timecode_tx_data|readdata [6] = ( \u0|timecode_tx_data|data_out [6] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|timecode_tx_data|data_out [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [6]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[6] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[6] .lut_mask = 64'h00000000F000F000;
defparam \u0|timecode_tx_data|readdata[6] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [6]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y16_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ))))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [6]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 .lut_mask = 64'h0055005510151015;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N46
dffeas \m_x|info[6] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|control [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [6]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[6] .is_wysiwyg = "true";
defparam \m_x|info[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N27
cyclonev_lcell_comb \u0|data_info|read_mux_out[6] (
// Equation(s):
// \u0|data_info|read_mux_out [6] = ( \m_x|info [6] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [6]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[6] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[6] .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|data_info|read_mux_out[6] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N29
dffeas \u0|data_info|readdata[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [6]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[6] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y10_N28
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [6]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N0
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder_combout = ( \A_SPW_TOP|SPW|RX|rx_data_flag [6] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N2
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [19]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N50
dffeas \A_SPW_TOP|rx_data|mem~7 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [6]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~7_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~7 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~7 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~12 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~12_combout = (!\A_SPW_TOP|rx_data|mem~0_q & ((\A_SPW_TOP|rx_data|mem~7_q ))) # (\A_SPW_TOP|rx_data|mem~0_q & (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a6 ))
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a6 ),
.datad(!\A_SPW_TOP|rx_data|mem~7_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~12 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~12 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|rx_data|data_out~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N54
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~13 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~13_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [19] & ( \A_SPW_TOP|rx_data|data_out~12_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [19] & ( \A_SPW_TOP|rx_data|data_out~12_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [19] & (
// !\A_SPW_TOP|rx_data|data_out~12_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [19]),
.dataf(!\A_SPW_TOP|rx_data|data_out~12_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~13 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~13 .lut_mask = 64'h00000401FBFEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N56
dffeas \A_SPW_TOP|rx_data|data_out[6] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~13_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [6]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[6] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N3
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[6] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [6] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\A_SPW_TOP|rx_data|data_out [6] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out [6]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [6]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[6] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[6] .lut_mask = 64'h5500550000000000;
defparam \u0|data_flag_rx|read_mux_out[6] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N5
dffeas \u0|data_flag_rx|readdata[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [6]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[6] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N4
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [6]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N36
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[6] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [6] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \A_SPW_TOP|SPW|RX|timecode [6] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|timecode [6]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [6]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[6] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[6] .lut_mask = 64'h0F0F000000000000;
defparam \u0|timecode_rx|read_mux_out[6] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N38
dffeas \u0|timecode_rx|readdata[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [6]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[6] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N10
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [6]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y18_N25
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) ) ) ) # (
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 .lut_mask = 64'h0000A2A20808AAAA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N26
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N14
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6])))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q & ( ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [6]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 .lut_mask = 64'h02FF02FFA2FFA2FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6])) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q )))
.dataa(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6]),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 .lut_mask = 64'h4747474747474747;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q &
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ) ) ) #
// ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6] & \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [6]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 .lut_mask = 64'h777F777FFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]) # (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & ( (\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & (\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 .lut_mask = 64'h00110011FFEEFFEE;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCC3CCC3CCCCCCCCC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hAAAFAAAF00050005;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [4] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h01F101F1F101F101;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h5053A0A30003F0F3;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y21_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y21_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y21_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) # (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFCFCFCFCF0F0F0F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .lut_mask = 64'h0C000C00CCCCCCCC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ) #
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3330333003000300;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// & (\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FF010001FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N55
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y21_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &
// ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
// # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h4040404044444444;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout
// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) #
// ((!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout &
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2000FFFF0000FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0300030033003300;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q
// & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0000FFFF45054505;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFFF0FFF000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ))))
// ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )))) )
// )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h4544454447444744;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
// ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h22E222E222222222;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hBF00AA0000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'h8880888088008800;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 .lut_mask = 64'h00FF00FF03F303F3;
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N50
dffeas \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & ( \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q & ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q
// & ( (!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout
// & ( !\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 .lut_mask = 64'hFFFFFAFA00005050;
defparam \u0|mm_interconnect_0|cmd_mux_021|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N35
dffeas \u0|mm_interconnect_0|cmd_mux_021|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_021|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y21_N1
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 .lut_mask = 64'h8080800000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N32
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0])))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) # ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0000000054FC54FC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1])))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h02AA02AA02AA02AA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N41
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00DF00DFFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout )))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h5305530553535353;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hAFAAAFAAFFAAFFAA;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q
// & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0000000F5555555F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N41
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y19_N26
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0333033300000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0505050500000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]
// ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter
// [0] & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter
// [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .lut_mask = 64'hAA00AA00A000A000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N50
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y21_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h00A000A00CAC0CAC;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000FC0CFC0C;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N43
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hB380B38080808080;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout =
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ))))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h001B001B001B001B;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] &
// (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0010001000000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N8
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// !\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hF0F0FAFAF5F5FFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] )
// + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N20
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ))))
.dataa(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h3022302230223022;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( ((((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N13
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) +
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0C0F0C0F0C000C00;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N47
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h57FF57FF55555555;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N43
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]
// ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 .lut_mask = 64'h3300330033003300;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [2] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (!\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00FC00FC00300030;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] &
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1111FFFF000F000F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N59
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout = (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 .lut_mask = 64'h3300330033003300;
defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y21_N55
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y21_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000A000A050F050F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y21_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]
// ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ))))
// ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000B8BBB8BB;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] &
// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h1111FFFF000F000F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y21_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N12
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[5]~5 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[5]~5_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|rx_data|counter [5]))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\A_SPW_TOP|rx_data|counter [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_rx_fifo|read_mux_out[5]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[5]~5 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[5]~5 .lut_mask = 64'h00C000C000C000C0;
defparam \u0|counter_rx_fifo|read_mux_out[5]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N13
dffeas \u0|counter_rx_fifo|readdata[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_rx_fifo|read_mux_out[5]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_rx_fifo|readdata [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[5] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N58
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_rx_fifo|readdata [5]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N38
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N53
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 .lut_mask = 64'h00A200A208AA08AA;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N12
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[5] (
// Equation(s):
// \u0|timecode_tx_data|readdata [5] = ( \u0|timecode_tx_data|data_out [5] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|timecode_tx_data|data_out [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [5]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[5] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[5] .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|timecode_tx_data|readdata[5] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N14
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [5]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y16_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ))
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 .lut_mask = 64'h00FF00FF0A5F0A5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N6
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[5] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [5] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|write_data_fifo_tx|data_out [5]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(gnd),
.datad(!\u0|write_data_fifo_tx|data_out [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [5]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[5] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[5] .lut_mask = 64'h00CC00CC00000000;
defparam \u0|write_data_fifo_tx|readdata[5] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [5]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y18_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y18_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5] & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [5]),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 .lut_mask = 64'h00000F0F03030303;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout & !\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout )))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout & !\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout )) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h030003008B888B88;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000F000F05050505;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout = ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 .lut_mask = 64'h0000AAAA0000AAAA;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h3300330022222222;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N56
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout & !\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout & !\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hB888B88830003000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h000F000F03030303;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout )) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hFFFFFFFF03F303F3;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]
// ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) +
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + ( !VCC ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (!\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ((!\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ) #
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h5550555000500050;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N25
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( ((((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N19
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) +
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000FF00000000FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000004000400;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N13
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h02FF02FFAAFFAAFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N17
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) +
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] &
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0033FFFF05050505;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y20_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) +
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout = (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 .lut_mask = 64'h5050505050505050;
defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ))))
// ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000AFA3AFA3;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N55
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h00FF33FF05050505;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y20_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N3
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[5]~5 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[5]~5_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|tx_data|counter [5] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|tx_data|counter [5]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_tx_fifo|read_mux_out[5]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[5]~5 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[5]~5 .lut_mask = 64'h3030303000000000;
defparam \u0|counter_tx_fifo|read_mux_out[5]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N4
dffeas \u0|counter_tx_fifo|readdata[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_tx_fifo|read_mux_out[5]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_tx_fifo|readdata [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[5] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_tx_fifo|readdata [5]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y17_N25
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h00F000F00FFF0FFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCFCFCFCF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N53
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]) #
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5])) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 .lut_mask = 64'h04040404BFBFBFBF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N23
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[18] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [18]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[18] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[18] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y12_N53
dffeas \A_SPW_TOP|rx_data|mem~6 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [5]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~6_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~6 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~6 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N51
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~10 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~10_combout = (!\A_SPW_TOP|rx_data|mem~0_q & ((\A_SPW_TOP|rx_data|mem~6_q ))) # (\A_SPW_TOP|rx_data|mem~0_q & (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a5 ))
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a5 ),
.datad(!\A_SPW_TOP|rx_data|mem~6_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~10 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~10 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|rx_data|data_out~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N15
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~11 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~11_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [18] & ( \A_SPW_TOP|rx_data|data_out~10_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [18] & ( \A_SPW_TOP|rx_data|data_out~10_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [18] & (
// !\A_SPW_TOP|rx_data|data_out~10_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [18]),
.dataf(!\A_SPW_TOP|rx_data|data_out~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~11 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~11 .lut_mask = 64'h00000401FBFEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N16
dffeas \A_SPW_TOP|rx_data|data_out[5] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~11_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [5]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[5] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N24
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[5] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [5] = ( \A_SPW_TOP|rx_data|data_out [5] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(!\A_SPW_TOP|rx_data|data_out [5]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [5]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[5] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[5] .lut_mask = 64'h0000A0A00000A0A0;
defparam \u0|data_flag_rx|read_mux_out[5] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N26
dffeas \u0|data_flag_rx|readdata[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [5]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[5] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N29
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [5]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y18_N5
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N17
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [5]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 .lut_mask = 64'h0F330F3300000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N20
dffeas \m_x|bit_d_1 (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_1~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_1 .is_wysiwyg = "true";
defparam \m_x|bit_d_1 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N42
cyclonev_lcell_comb \m_x|bit_d_3~feeder (
// Equation(s):
// \m_x|bit_d_3~feeder_combout = ( \m_x|bit_d_1~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_1~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|bit_d_3~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|bit_d_3~feeder .extended_lut = "off";
defparam \m_x|bit_d_3~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_3~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N44
dffeas \m_x|bit_d_3 (
.clk(\m_x|always3~0_combout ),
.d(\m_x|bit_d_3~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_3~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_3 .is_wysiwyg = "true";
defparam \m_x|bit_d_3 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N57
cyclonev_lcell_comb \m_x|bit_d_5~feeder (
// Equation(s):
// \m_x|bit_d_5~feeder_combout = ( \m_x|bit_d_3~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_3~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|bit_d_5~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|bit_d_5~feeder .extended_lut = "off";
defparam \m_x|bit_d_5~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_5~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N59
dffeas \m_x|bit_d_5 (
.clk(\m_x|always3~0_combout ),
.d(\m_x|bit_d_5~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_5~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_5 .is_wysiwyg = "true";
defparam \m_x|bit_d_5 .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y7_N14
dffeas \m_x|dta_timec[2] (
.clk(\m_x|ready_data_p~combout ),
.d(gnd),
.asdata(\m_x|bit_d_5~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[2] .is_wysiwyg = "true";
defparam \m_x|dta_timec[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N9
cyclonev_lcell_comb \m_x|dta_timec_p[2]~feeder (
// Equation(s):
// \m_x|dta_timec_p[2]~feeder_combout = ( \m_x|dta_timec [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[2]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N10
dffeas \m_x|dta_timec_p[2] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[2]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[2] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N33
cyclonev_lcell_comb \m_x|data~9 (
// Equation(s):
// \m_x|data~9_combout = ( \m_x|dta_timec_p [2] & ( \m_x|ready_data_p_r~q ) )
.dataa(gnd),
.datab(!\m_x|ready_data_p_r~q ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec_p [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~9 .extended_lut = "off";
defparam \m_x|data~9 .lut_mask = 64'h0000000033333333;
defparam \m_x|data~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N0
cyclonev_lcell_comb \m_x|last_is_timec~0 (
// Equation(s):
// \m_x|last_is_timec~0_combout = ( \m_x|control [2] & ( (\m_x|control [0] & (!\m_x|ready_control_p_r~q & \m_x|control [1])) ) )
.dataa(gnd),
.datab(!\m_x|control [0]),
.datac(!\m_x|ready_control_p_r~q ),
.datad(!\m_x|control [1]),
.datae(gnd),
.dataf(!\m_x|control [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|last_is_timec~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|last_is_timec~0 .extended_lut = "off";
defparam \m_x|last_is_timec~0 .lut_mask = 64'h0000000000300030;
defparam \m_x|last_is_timec~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N2
dffeas \m_x|last_is_timec (
.clk(\m_x|always3~0_combout ),
.d(\m_x|last_is_timec~0_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|last_is_timec~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|last_is_timec .is_wysiwyg = "true";
defparam \m_x|last_is_timec .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N15
cyclonev_lcell_comb \m_x|last_is_control~0 (
// Equation(s):
// \m_x|last_is_control~0_combout = ( \m_x|ready_control_p_r~q ) # ( !\m_x|ready_control_p_r~q & ( (\m_x|last_is_control~q & !\m_x|ready_data_p_r~q ) ) )
.dataa(gnd),
.datab(!\m_x|last_is_control~q ),
.datac(!\m_x|ready_data_p_r~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|ready_control_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|last_is_control~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|last_is_control~0 .extended_lut = "off";
defparam \m_x|last_is_control~0 .lut_mask = 64'h30303030FFFFFFFF;
defparam \m_x|last_is_control~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N56
dffeas \m_x|last_is_control (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|last_is_control~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|last_is_control~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|last_is_control .is_wysiwyg = "true";
defparam \m_x|last_is_control .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X36_Y7_N9
cyclonev_lcell_comb \m_x|last_is_data~0 (
// Equation(s):
// \m_x|last_is_data~0_combout = ( !\m_x|ready_control_p_r~q & ( (!\m_x|control [2]) # ((!\m_x|control [0]) # (!\m_x|control [1])) ) )
.dataa(!\m_x|control [2]),
.datab(gnd),
.datac(!\m_x|control [0]),
.datad(!\m_x|control [1]),
.datae(gnd),
.dataf(!\m_x|ready_control_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|last_is_data~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|last_is_data~0 .extended_lut = "off";
defparam \m_x|last_is_data~0 .lut_mask = 64'hFFFAFFFA00000000;
defparam \m_x|last_is_data~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N11
dffeas \m_x|last_is_data (
.clk(\m_x|always3~0_combout ),
.d(\m_x|last_is_data~0_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|last_is_data~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|last_is_data .is_wysiwyg = "true";
defparam \m_x|last_is_data .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N18
cyclonev_lcell_comb \m_x|data[8]~1 (
// Equation(s):
// \m_x|data[8]~1_combout = ( \m_x|last_is_control~q & ( !\m_x|last_is_data~q & ( (\m_x|control [2] & (!\m_x|last_is_timec~q & ((\m_x|control [0]) # (\m_x|control [1])))) ) ) )
.dataa(!\m_x|control [2]),
.datab(!\m_x|control [1]),
.datac(!\m_x|control [0]),
.datad(!\m_x|last_is_timec~q ),
.datae(!\m_x|last_is_control~q ),
.dataf(!\m_x|last_is_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data[8]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data[8]~1 .extended_lut = "off";
defparam \m_x|data[8]~1 .lut_mask = 64'h0000150000000000;
defparam \m_x|data[8]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N54
cyclonev_lcell_comb \m_x|data[8]~2 (
// Equation(s):
// \m_x|data[8]~2_combout = ( \m_x|control [2] & ( \m_x|ready_data_p_r~q & ( (!\m_x|ready_control_p_r~q & ((!\m_x|control [1]) # (!\m_x|control [0]))) ) ) ) # ( !\m_x|control [2] & ( \m_x|ready_data_p_r~q & ( !\m_x|ready_control_p_r~q ) ) ) # (
// \m_x|control [2] & ( !\m_x|ready_data_p_r~q & ( (\m_x|data[8]~1_combout & (!\m_x|ready_control_p_r~q & ((!\m_x|control [1]) # (!\m_x|control [0])))) ) ) ) # ( !\m_x|control [2] & ( !\m_x|ready_data_p_r~q & ( (\m_x|data[8]~1_combout &
// !\m_x|ready_control_p_r~q ) ) ) )
.dataa(!\m_x|control [1]),
.datab(!\m_x|data[8]~1_combout ),
.datac(!\m_x|ready_control_p_r~q ),
.datad(!\m_x|control [0]),
.datae(!\m_x|control [2]),
.dataf(!\m_x|ready_data_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data[8]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data[8]~2 .extended_lut = "off";
defparam \m_x|data[8]~2 .lut_mask = 64'h30303020F0F0F0A0;
defparam \m_x|data[8]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N5
dffeas \m_x|data[2] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data~9_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[2] .is_wysiwyg = "true";
defparam \m_x|data[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N24
cyclonev_lcell_comb \m_x|dta_timec[6]~feeder (
// Equation(s):
// \m_x|dta_timec[6]~feeder_combout = ( \m_x|bit_d_1~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_1~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec[6]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec[6]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[6]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N26
dffeas \m_x|dta_timec[6] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec[6]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [6]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[6] .is_wysiwyg = "true";
defparam \m_x|dta_timec[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N33
cyclonev_lcell_comb \m_x|dta_timec_p[6]~feeder (
// Equation(s):
// \m_x|dta_timec_p[6]~feeder_combout = ( \m_x|dta_timec [6] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[6]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[6]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[6]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N34
dffeas \m_x|dta_timec_p[6] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[6]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [6]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[6] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N21
cyclonev_lcell_comb \m_x|data~5 (
// Equation(s):
// \m_x|data~5_combout = ( \m_x|ready_data_p_r~q & ( \m_x|dta_timec_p [6] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|dta_timec_p [6]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|ready_data_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~5 .extended_lut = "off";
defparam \m_x|data~5 .lut_mask = 64'h000000000F0F0F0F;
defparam \m_x|data~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N44
dffeas \m_x|data[6] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data~5_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [6]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[6] .is_wysiwyg = "true";
defparam \m_x|data[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X37_Y7_N8
dffeas \m_x|bit_d_0 (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_0~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_0 .is_wysiwyg = "true";
defparam \m_x|bit_d_0 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N57
cyclonev_lcell_comb \m_x|bit_d_2~feeder (
// Equation(s):
// \m_x|bit_d_2~feeder_combout = ( \m_x|bit_d_0~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_0~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|bit_d_2~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|bit_d_2~feeder .extended_lut = "off";
defparam \m_x|bit_d_2~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_2~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N59
dffeas \m_x|bit_d_2 (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|bit_d_2~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_2~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_2 .is_wysiwyg = "true";
defparam \m_x|bit_d_2 .power_up = "low";
// synopsys translate_on
// Location: FF_X37_Y7_N56
dffeas \m_x|bit_d_4 (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|bit_d_2~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_4~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_4 .is_wysiwyg = "true";
defparam \m_x|bit_d_4 .power_up = "low";
// synopsys translate_on
// Location: FF_X37_Y7_N32
dffeas \m_x|dta_timec[3] (
.clk(\m_x|ready_data_p~combout ),
.d(gnd),
.asdata(\m_x|bit_d_4~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[3] .is_wysiwyg = "true";
defparam \m_x|dta_timec[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N0
cyclonev_lcell_comb \m_x|dta_timec_p[3]~feeder (
// Equation(s):
// \m_x|dta_timec_p[3]~feeder_combout = ( \m_x|dta_timec [3] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[3]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N1
dffeas \m_x|dta_timec_p[3] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[3]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[3] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N30
cyclonev_lcell_comb \m_x|data~8 (
// Equation(s):
// \m_x|data~8_combout = (\m_x|ready_data_p_r~q & \m_x|dta_timec_p [3])
.dataa(gnd),
.datab(!\m_x|ready_data_p_r~q ),
.datac(!\m_x|dta_timec_p [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~8 .extended_lut = "off";
defparam \m_x|data~8 .lut_mask = 64'h0303030303030303;
defparam \m_x|data~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N38
dffeas \m_x|data[3] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data~8_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[3] .is_wysiwyg = "true";
defparam \m_x|data[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X37_Y7_N47
dffeas \m_x|dta_timec[5] (
.clk(\m_x|ready_data_p~combout ),
.d(gnd),
.asdata(\m_x|bit_d_2~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[5] .is_wysiwyg = "true";
defparam \m_x|dta_timec[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X37_Y7_N22
dffeas \m_x|dta_timec_p[5] (
.clk(\m_x|ready_data_p~combout ),
.d(gnd),
.asdata(\m_x|dta_timec [5]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[5] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N39
cyclonev_lcell_comb \m_x|data~6 (
// Equation(s):
// \m_x|data~6_combout = (\m_x|ready_data_p_r~q & \m_x|dta_timec_p [5])
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|ready_data_p_r~q ),
.datad(!\m_x|dta_timec_p [5]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~6 .extended_lut = "off";
defparam \m_x|data~6 .lut_mask = 64'h000F000F000F000F;
defparam \m_x|data~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N41
dffeas \m_x|data[5] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|data~6_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[5] .is_wysiwyg = "true";
defparam \m_x|data[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N48
cyclonev_lcell_comb \m_x|dta_timec[4]~feeder (
// Equation(s):
// \m_x|dta_timec[4]~feeder_combout = ( \m_x|bit_d_3~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_3~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec[4]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N50
dffeas \m_x|dta_timec[4] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec[4]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[4] .is_wysiwyg = "true";
defparam \m_x|dta_timec[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y7_N51
cyclonev_lcell_comb \m_x|dta_timec_p[4]~feeder (
// Equation(s):
// \m_x|dta_timec_p[4]~feeder_combout = ( \m_x|dta_timec [4] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[4]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[4]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[4]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N52
dffeas \m_x|dta_timec_p[4] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[4]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[4] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N54
cyclonev_lcell_comb \m_x|data~7 (
// Equation(s):
// \m_x|data~7_combout = ( \m_x|ready_data_p_r~q & ( \m_x|dta_timec_p [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|dta_timec_p [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|ready_data_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~7 .extended_lut = "off";
defparam \m_x|data~7 .lut_mask = 64'h000000000F0F0F0F;
defparam \m_x|data~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N2
dffeas \m_x|data[4] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data~7_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[4] .is_wysiwyg = "true";
defparam \m_x|data[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N33
cyclonev_lcell_comb \m_x|dta_timec[7]~feeder (
// Equation(s):
// \m_x|dta_timec[7]~feeder_combout = ( \m_x|bit_d_0~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_0~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec[7]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec[7]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[7]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N35
dffeas \m_x|dta_timec[7] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec[7]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [7]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[7] .is_wysiwyg = "true";
defparam \m_x|dta_timec[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N3
cyclonev_lcell_comb \m_x|dta_timec_p[7]~feeder (
// Equation(s):
// \m_x|dta_timec_p[7]~feeder_combout = ( \m_x|dta_timec [7] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[7]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[7]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[7]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N4
dffeas \m_x|dta_timec_p[7] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[7]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [7]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[7] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N9
cyclonev_lcell_comb \m_x|data~4 (
// Equation(s):
// \m_x|data~4_combout = ( \m_x|ready_data_p_r~q & ( \m_x|dta_timec_p [7] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\m_x|dta_timec_p [7]),
.datae(gnd),
.dataf(!\m_x|ready_data_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~4 .extended_lut = "off";
defparam \m_x|data~4 .lut_mask = 64'h0000000000FF00FF;
defparam \m_x|data~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N11
dffeas \m_x|data[7] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|data~4_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [7]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[7] .is_wysiwyg = "true";
defparam \m_x|data[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N0
cyclonev_lcell_comb \m_x|always9~4 (
// Equation(s):
// \m_x|always9~4_combout = ( \m_x|data [4] & ( \m_x|data [7] & ( !\m_x|data [2] $ (!\m_x|data [6] $ (!\m_x|data [3] $ (!\m_x|data [5]))) ) ) ) # ( !\m_x|data [4] & ( \m_x|data [7] & ( !\m_x|data [2] $ (!\m_x|data [6] $ (!\m_x|data [3] $ (\m_x|data [5]))) )
// ) ) # ( \m_x|data [4] & ( !\m_x|data [7] & ( !\m_x|data [2] $ (!\m_x|data [6] $ (!\m_x|data [3] $ (\m_x|data [5]))) ) ) ) # ( !\m_x|data [4] & ( !\m_x|data [7] & ( !\m_x|data [2] $ (!\m_x|data [6] $ (!\m_x|data [3] $ (!\m_x|data [5]))) ) ) )
.dataa(!\m_x|data [2]),
.datab(!\m_x|data [6]),
.datac(!\m_x|data [3]),
.datad(!\m_x|data [5]),
.datae(!\m_x|data [4]),
.dataf(!\m_x|data [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always9~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always9~4 .extended_lut = "off";
defparam \m_x|always9~4 .lut_mask = 64'h6996966996696996;
defparam \m_x|always9~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N17
dffeas \m_x|bit_d_6 (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|bit_d_4~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_6~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_6 .is_wysiwyg = "true";
defparam \m_x|bit_d_6 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N12
cyclonev_lcell_comb \m_x|bit_d_8~feeder (
// Equation(s):
// \m_x|bit_d_8~feeder_combout = ( \m_x|bit_d_6~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_6~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|bit_d_8~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|bit_d_8~feeder .extended_lut = "off";
defparam \m_x|bit_d_8~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|bit_d_8~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N14
dffeas \m_x|bit_d_8 (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|bit_d_8~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_8~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_8 .is_wysiwyg = "true";
defparam \m_x|bit_d_8 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N48
cyclonev_lcell_comb \m_x|dta_timec[8]~feeder (
// Equation(s):
// \m_x|dta_timec[8]~feeder_combout = ( \m_x|bit_d_8~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_8~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec[8]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec[8]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[8]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N50
dffeas \m_x|dta_timec[8] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec[8]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [8]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[8] .is_wysiwyg = "true";
defparam \m_x|dta_timec[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N51
cyclonev_lcell_comb \m_x|dta_timec_p[8]~feeder (
// Equation(s):
// \m_x|dta_timec_p[8]~feeder_combout = ( \m_x|dta_timec [8] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[8]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[8]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[8]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N52
dffeas \m_x|dta_timec_p[8] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[8]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [8]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[8] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N45
cyclonev_lcell_comb \m_x|data~0 (
// Equation(s):
// \m_x|data~0_combout = ( \m_x|dta_timec_p [8] ) # ( !\m_x|dta_timec_p [8] & ( !\m_x|ready_data_p_r~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|ready_data_p_r~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec_p [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~0 .extended_lut = "off";
defparam \m_x|data~0 .lut_mask = 64'hF0F0F0F0FFFFFFFF;
defparam \m_x|data~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N47
dffeas \m_x|data[8] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|data~0_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [8]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[8] .is_wysiwyg = "true";
defparam \m_x|data[8] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N6
cyclonev_lcell_comb \m_x|rx_error~6 (
// Equation(s):
// \m_x|rx_error~6_combout = ( \m_x|last_is_data~q & ( (!\m_x|last_is_control~q & (!\m_x|data [8] $ (!\m_x|control [1] $ (!\m_x|control [0])))) ) )
.dataa(!\m_x|last_is_control~q ),
.datab(!\m_x|data [8]),
.datac(!\m_x|control [1]),
.datad(!\m_x|control [0]),
.datae(gnd),
.dataf(!\m_x|last_is_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~6 .extended_lut = "off";
defparam \m_x|rx_error~6 .lut_mask = 64'h0000000082288228;
defparam \m_x|rx_error~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y7_N5
dffeas \m_x|bit_d_7 (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|bit_d_5~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|bit_d_7~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|bit_d_7 .is_wysiwyg = "true";
defparam \m_x|bit_d_7 .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y7_N38
dffeas \m_x|dta_timec[0] (
.clk(\m_x|ready_data_p~combout ),
.d(gnd),
.asdata(\m_x|bit_d_7~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[0] .is_wysiwyg = "true";
defparam \m_x|dta_timec[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y7_N22
dffeas \m_x|dta_timec_p[0] (
.clk(\m_x|ready_data_p~combout ),
.d(gnd),
.asdata(\m_x|dta_timec [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[0] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N12
cyclonev_lcell_comb \m_x|data~3 (
// Equation(s):
// \m_x|data~3_combout = ( \m_x|dta_timec_p [0] & ( ((\m_x|control [2] & (\m_x|control [1] & !\m_x|control [0]))) # (\m_x|ready_data_p_r~q ) ) ) # ( !\m_x|dta_timec_p [0] & ( (\m_x|control [2] & (!\m_x|ready_data_p_r~q & (\m_x|control [1] & !\m_x|control
// [0]))) ) )
.dataa(!\m_x|control [2]),
.datab(!\m_x|ready_data_p_r~q ),
.datac(!\m_x|control [1]),
.datad(!\m_x|control [0]),
.datae(gnd),
.dataf(!\m_x|dta_timec_p [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~3 .extended_lut = "off";
defparam \m_x|data~3 .lut_mask = 64'h0400040037333733;
defparam \m_x|data~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N14
dffeas \m_x|data[0] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|data~3_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[0] .is_wysiwyg = "true";
defparam \m_x|data[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N42
cyclonev_lcell_comb \m_x|dta_timec[1]~feeder (
// Equation(s):
// \m_x|dta_timec[1]~feeder_combout = ( \m_x|bit_d_6~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|bit_d_6~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec[1]~feeder .extended_lut = "off";
defparam \m_x|dta_timec[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N44
dffeas \m_x|dta_timec[1] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec[1]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec[1] .is_wysiwyg = "true";
defparam \m_x|dta_timec[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X37_Y7_N18
cyclonev_lcell_comb \m_x|dta_timec_p[1]~feeder (
// Equation(s):
// \m_x|dta_timec_p[1]~feeder_combout = ( \m_x|dta_timec [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|dta_timec_p[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|dta_timec_p[1]~feeder .extended_lut = "off";
defparam \m_x|dta_timec_p[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|dta_timec_p[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X37_Y7_N19
dffeas \m_x|dta_timec_p[1] (
.clk(\m_x|ready_data_p~combout ),
.d(\m_x|dta_timec_p[1]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(!\m_x|is_control~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|dta_timec_p [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|dta_timec_p[1] .is_wysiwyg = "true";
defparam \m_x|dta_timec_p[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N21
cyclonev_lcell_comb \m_x|data~10 (
// Equation(s):
// \m_x|data~10_combout = ( \m_x|ready_data_p_r~q & ( \m_x|dta_timec_p [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|dta_timec_p [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|ready_data_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data~10 .extended_lut = "off";
defparam \m_x|data~10 .lut_mask = 64'h000000000F0F0F0F;
defparam \m_x|data~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X32_Y7_N17
dffeas \m_x|data[1] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data~10_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data[8]~2_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data[1] .is_wysiwyg = "true";
defparam \m_x|data[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N33
cyclonev_lcell_comb \m_x|always9~5 (
// Equation(s):
// \m_x|always9~5_combout = ( \m_x|data [1] & ( !\m_x|control [2] $ (!\m_x|data [0] $ (!\m_x|control [3])) ) ) # ( !\m_x|data [1] & ( !\m_x|control [2] $ (!\m_x|data [0] $ (\m_x|control [3])) ) )
.dataa(!\m_x|control [2]),
.datab(gnd),
.datac(!\m_x|data [0]),
.datad(!\m_x|control [3]),
.datae(gnd),
.dataf(!\m_x|data [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always9~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always9~5 .extended_lut = "off";
defparam \m_x|always9~5 .lut_mask = 64'h5AA55AA5A55AA55A;
defparam \m_x|always9~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X36_Y7_N47
dffeas \m_x|last_was_data (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|last_is_data~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|last_was_data~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|last_was_data .is_wysiwyg = "true";
defparam \m_x|last_was_data .power_up = "low";
// synopsys translate_on
// Location: FF_X36_Y7_N23
dffeas \m_x|last_was_timec (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|last_is_timec~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|last_was_timec~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|last_was_timec .is_wysiwyg = "true";
defparam \m_x|last_was_timec .power_up = "low";
// synopsys translate_on
// Location: FF_X36_Y7_N35
dffeas \m_x|last_was_control (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|last_is_control~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|last_was_control~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|last_was_control .is_wysiwyg = "true";
defparam \m_x|last_was_control .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N18
cyclonev_lcell_comb \m_x|rx_error~8 (
// Equation(s):
// \m_x|rx_error~8_combout = ( \m_x|last_is_control~q & ( (\m_x|last_was_data~q & (!\m_x|last_was_timec~q & !\m_x|last_was_control~q )) ) )
.dataa(!\m_x|last_was_data~q ),
.datab(!\m_x|last_was_timec~q ),
.datac(!\m_x|last_was_control~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|last_is_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~8 .extended_lut = "off";
defparam \m_x|rx_error~8 .lut_mask = 64'h0000000040404040;
defparam \m_x|rx_error~8 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N36
cyclonev_lcell_comb \m_x|rx_error~7 (
// Equation(s):
// \m_x|rx_error~7_combout = ( \m_x|control [3] & ( (\m_x|last_is_control~q & (!\m_x|control [2] $ (!\m_x|control_l_r [1] $ (\m_x|control_l_r [0])))) ) ) # ( !\m_x|control [3] & ( (\m_x|last_is_control~q & (!\m_x|control [2] $ (!\m_x|control_l_r [1] $
// (!\m_x|control_l_r [0])))) ) )
.dataa(!\m_x|control [2]),
.datab(!\m_x|control_l_r [1]),
.datac(!\m_x|control_l_r [0]),
.datad(!\m_x|last_is_control~q ),
.datae(gnd),
.dataf(!\m_x|control [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~7 .extended_lut = "off";
defparam \m_x|rx_error~7 .lut_mask = 64'h0096009600690069;
defparam \m_x|rx_error~7 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N48
cyclonev_lcell_comb \m_x|rx_error~9 (
// Equation(s):
// \m_x|rx_error~9_combout = ( !\m_x|rx_error~7_combout & ( \m_x|last_was_control~q & ( (!\m_x|rx_error~6_combout & ((!\m_x|rx_error~8_combout ) # (!\m_x|always9~4_combout $ (!\m_x|always9~5_combout )))) ) ) ) # ( \m_x|rx_error~7_combout & (
// !\m_x|last_was_control~q & ( (!\m_x|rx_error~8_combout ) # (!\m_x|always9~4_combout $ (!\m_x|always9~5_combout )) ) ) ) # ( !\m_x|rx_error~7_combout & ( !\m_x|last_was_control~q & ( (!\m_x|rx_error~8_combout ) # (!\m_x|always9~4_combout $
// (!\m_x|always9~5_combout )) ) ) )
.dataa(!\m_x|always9~4_combout ),
.datab(!\m_x|rx_error~6_combout ),
.datac(!\m_x|always9~5_combout ),
.datad(!\m_x|rx_error~8_combout ),
.datae(!\m_x|rx_error~7_combout ),
.dataf(!\m_x|last_was_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~9 .extended_lut = "off";
defparam \m_x|rx_error~9 .lut_mask = 64'hFF5AFF5ACC480000;
defparam \m_x|rx_error~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N42
cyclonev_lcell_comb \m_x|rx_error~2 (
// Equation(s):
// \m_x|rx_error~2_combout = ( \m_x|rx_error~q & ( \m_x|last_is_data~q & ( (!\m_x|last_was_timec~q & (!\m_x|last_was_data~q & !\m_x|last_was_control~q )) ) ) ) # ( \m_x|rx_error~q & ( !\m_x|last_is_data~q & ( (!\m_x|last_is_control~q ) #
// ((!\m_x|last_was_timec~q & (!\m_x|last_was_data~q & !\m_x|last_was_control~q ))) ) ) )
.dataa(!\m_x|last_was_timec~q ),
.datab(!\m_x|last_was_data~q ),
.datac(!\m_x|last_was_control~q ),
.datad(!\m_x|last_is_control~q ),
.datae(!\m_x|rx_error~q ),
.dataf(!\m_x|last_is_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~2 .extended_lut = "off";
defparam \m_x|rx_error~2 .lut_mask = 64'h0000FF8000008080;
defparam \m_x|rx_error~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N45
cyclonev_lcell_comb \m_x|timecode[5]~feeder (
// Equation(s):
// \m_x|timecode[5]~feeder_combout = ( \m_x|dta_timec [5] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|dta_timec [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|timecode[5]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|timecode[5]~feeder .extended_lut = "off";
defparam \m_x|timecode[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|timecode[5]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N18
cyclonev_lcell_comb \m_x|timecode[7]~0 (
// Equation(s):
// \m_x|timecode[7]~0_combout = ( \m_x|control [2] & ( (!\m_x|ready_control_p_r~q & (\m_x|ready_data_p_r~q & (\m_x|control [1] & \m_x|control [0]))) ) )
.dataa(!\m_x|ready_control_p_r~q ),
.datab(!\m_x|ready_data_p_r~q ),
.datac(!\m_x|control [1]),
.datad(!\m_x|control [0]),
.datae(gnd),
.dataf(!\m_x|control [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|timecode[7]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|timecode[7]~0 .extended_lut = "off";
defparam \m_x|timecode[7]~0 .lut_mask = 64'h0000000000020002;
defparam \m_x|timecode[7]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y7_N47
dffeas \m_x|timecode[5] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|timecode[5]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[5] .is_wysiwyg = "true";
defparam \m_x|timecode[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N29
dffeas \m_x|timecode[4] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [4]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[4] .is_wysiwyg = "true";
defparam \m_x|timecode[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N44
dffeas \m_x|timecode[6] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [6]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [6]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[6] .is_wysiwyg = "true";
defparam \m_x|timecode[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N26
dffeas \m_x|timecode[3] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [3]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[3] .is_wysiwyg = "true";
defparam \m_x|timecode[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N11
dffeas \m_x|timecode[7] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [7]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [7]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[7] .is_wysiwyg = "true";
defparam \m_x|timecode[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N24
cyclonev_lcell_comb \m_x|always9~0 (
// Equation(s):
// \m_x|always9~0_combout = ( \m_x|timecode [3] & ( \m_x|timecode [7] & ( !\m_x|timecode [5] $ (!\m_x|timecode [4] $ (\m_x|timecode [6])) ) ) ) # ( !\m_x|timecode [3] & ( \m_x|timecode [7] & ( !\m_x|timecode [5] $ (!\m_x|timecode [4] $ (!\m_x|timecode [6]))
// ) ) ) # ( \m_x|timecode [3] & ( !\m_x|timecode [7] & ( !\m_x|timecode [5] $ (!\m_x|timecode [4] $ (!\m_x|timecode [6])) ) ) ) # ( !\m_x|timecode [3] & ( !\m_x|timecode [7] & ( !\m_x|timecode [5] $ (!\m_x|timecode [4] $ (\m_x|timecode [6])) ) ) )
.dataa(gnd),
.datab(!\m_x|timecode [5]),
.datac(!\m_x|timecode [4]),
.datad(!\m_x|timecode [6]),
.datae(!\m_x|timecode [3]),
.dataf(!\m_x|timecode [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always9~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always9~0 .extended_lut = "off";
defparam \m_x|always9~0 .lut_mask = 64'h3CC3C33CC33C3CC3;
defparam \m_x|always9~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y7_N8
dffeas \m_x|timecode[0] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [0]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[0] .is_wysiwyg = "true";
defparam \m_x|timecode[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N38
dffeas \m_x|timecode[2] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [2]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[2] .is_wysiwyg = "true";
defparam \m_x|timecode[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N41
dffeas \m_x|timecode[1] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|dta_timec [1]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|timecode[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|timecode [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|timecode[1] .is_wysiwyg = "true";
defparam \m_x|timecode[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N39
cyclonev_lcell_comb \m_x|rx_error~0 (
// Equation(s):
// \m_x|rx_error~0_combout = ( \m_x|timecode [1] & ( \m_x|data [8] & ( (\m_x|last_was_timec~q & (!\m_x|always9~0_combout $ (!\m_x|timecode [0] $ (!\m_x|timecode [2])))) ) ) ) # ( !\m_x|timecode [1] & ( \m_x|data [8] & ( (\m_x|last_was_timec~q &
// (!\m_x|always9~0_combout $ (!\m_x|timecode [0] $ (\m_x|timecode [2])))) ) ) ) # ( \m_x|timecode [1] & ( !\m_x|data [8] & ( (\m_x|last_was_timec~q & (!\m_x|always9~0_combout $ (!\m_x|timecode [0] $ (\m_x|timecode [2])))) ) ) ) # ( !\m_x|timecode [1] & (
// !\m_x|data [8] & ( (\m_x|last_was_timec~q & (!\m_x|always9~0_combout $ (!\m_x|timecode [0] $ (!\m_x|timecode [2])))) ) ) )
.dataa(!\m_x|always9~0_combout ),
.datab(!\m_x|last_was_timec~q ),
.datac(!\m_x|timecode [0]),
.datad(!\m_x|timecode [2]),
.datae(!\m_x|timecode [1]),
.dataf(!\m_x|data [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~0 .extended_lut = "off";
defparam \m_x|rx_error~0 .lut_mask = 64'h2112122112212112;
defparam \m_x|rx_error~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N12
cyclonev_lcell_comb \m_x|rx_error~3 (
// Equation(s):
// \m_x|rx_error~3_combout = ( !\m_x|last_was_control~q & ( (\m_x|last_is_control~q & \m_x|last_was_timec~q ) ) )
.dataa(gnd),
.datab(!\m_x|last_is_control~q ),
.datac(gnd),
.datad(!\m_x|last_was_timec~q ),
.datae(gnd),
.dataf(!\m_x|last_was_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~3 .extended_lut = "off";
defparam \m_x|rx_error~3 .lut_mask = 64'h0033003300000000;
defparam \m_x|rx_error~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N30
cyclonev_lcell_comb \m_x|always9~3 (
// Equation(s):
// \m_x|always9~3_combout = ( \m_x|control [3] & ( !\m_x|control [2] ) ) # ( !\m_x|control [3] & ( \m_x|control [2] ) )
.dataa(!\m_x|control [2]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|control [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always9~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always9~3 .extended_lut = "off";
defparam \m_x|always9~3 .lut_mask = 64'h55555555AAAAAAAA;
defparam \m_x|always9~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N6
cyclonev_lcell_comb \m_x|rx_error~4 (
// Equation(s):
// \m_x|rx_error~4_combout = ( \m_x|timecode [0] & ( \m_x|always9~3_combout & ( (\m_x|rx_error~3_combout & (!\m_x|always9~0_combout $ (!\m_x|timecode [2] $ (!\m_x|timecode [1])))) ) ) ) # ( !\m_x|timecode [0] & ( \m_x|always9~3_combout & (
// (\m_x|rx_error~3_combout & (!\m_x|always9~0_combout $ (!\m_x|timecode [2] $ (\m_x|timecode [1])))) ) ) ) # ( \m_x|timecode [0] & ( !\m_x|always9~3_combout & ( (\m_x|rx_error~3_combout & (!\m_x|always9~0_combout $ (!\m_x|timecode [2] $ (\m_x|timecode
// [1])))) ) ) ) # ( !\m_x|timecode [0] & ( !\m_x|always9~3_combout & ( (\m_x|rx_error~3_combout & (!\m_x|always9~0_combout $ (!\m_x|timecode [2] $ (!\m_x|timecode [1])))) ) ) )
.dataa(!\m_x|always9~0_combout ),
.datab(!\m_x|rx_error~3_combout ),
.datac(!\m_x|timecode [2]),
.datad(!\m_x|timecode [1]),
.datae(!\m_x|timecode [0]),
.dataf(!\m_x|always9~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~4 .extended_lut = "off";
defparam \m_x|rx_error~4 .lut_mask = 64'h2112122112212112;
defparam \m_x|rx_error~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N42
cyclonev_lcell_comb \m_x|rx_error~5 (
// Equation(s):
// \m_x|rx_error~5_combout = ( !\m_x|last_was_control~q & ( (\m_x|last_is_data~q & !\m_x|last_is_control~q ) ) )
.dataa(gnd),
.datab(!\m_x|last_is_data~q ),
.datac(!\m_x|last_is_control~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|last_was_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~5 .extended_lut = "off";
defparam \m_x|rx_error~5 .lut_mask = 64'h3030303000000000;
defparam \m_x|rx_error~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N15
cyclonev_lcell_comb \m_x|data_l_r[7]~1 (
// Equation(s):
// \m_x|data_l_r[7]~1_combout = ( !\m_x|ready_control_p_r~q & ( (!\m_x|ready_data_p_r~q & \m_x|last_is_data~q ) ) )
.dataa(gnd),
.datab(!\m_x|ready_data_p_r~q ),
.datac(!\m_x|last_is_data~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|ready_control_p_r~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|data_l_r[7]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|data_l_r[7]~1 .extended_lut = "off";
defparam \m_x|data_l_r[7]~1 .lut_mask = 64'h0C0C0C0C00000000;
defparam \m_x|data_l_r[7]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y7_N59
dffeas \m_x|data_l_r[3] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [3]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[3] .is_wysiwyg = "true";
defparam \m_x|data_l_r[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N5
dffeas \m_x|data_l_r[1] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [1]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[1] .is_wysiwyg = "true";
defparam \m_x|data_l_r[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N20
dffeas \m_x|data_l_r[2] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [2]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[2] .is_wysiwyg = "true";
defparam \m_x|data_l_r[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N3
cyclonev_lcell_comb \m_x|always9~2 (
// Equation(s):
// \m_x|always9~2_combout = ( \m_x|data_l_r [2] & ( !\m_x|data_l_r [3] $ (\m_x|data_l_r [1]) ) ) # ( !\m_x|data_l_r [2] & ( !\m_x|data_l_r [3] $ (!\m_x|data_l_r [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\m_x|data_l_r [3]),
.datad(!\m_x|data_l_r [1]),
.datae(gnd),
.dataf(!\m_x|data_l_r [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always9~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always9~2 .extended_lut = "off";
defparam \m_x|always9~2 .lut_mask = 64'h0FF00FF0F00FF00F;
defparam \m_x|always9~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y7_N2
dffeas \m_x|data_l_r[4] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [4]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[4] .is_wysiwyg = "true";
defparam \m_x|data_l_r[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N53
dffeas \m_x|data_l_r[6] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [6]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [6]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[6] .is_wysiwyg = "true";
defparam \m_x|data_l_r[6] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N17
dffeas \m_x|data_l_r[7] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [7]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [7]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[7] .is_wysiwyg = "true";
defparam \m_x|data_l_r[7] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y7_N50
dffeas \m_x|data_l_r[5] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|data [5]),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|data_l_r [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|data_l_r[5] .is_wysiwyg = "true";
defparam \m_x|data_l_r[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N48
cyclonev_lcell_comb \m_x|always9~1 (
// Equation(s):
// \m_x|always9~1_combout = ( \m_x|data_l_r [5] & ( !\m_x|data_l_r [6] $ (!\m_x|data [0] $ (!\m_x|data [8] $ (\m_x|data_l_r [7]))) ) ) # ( !\m_x|data_l_r [5] & ( !\m_x|data_l_r [6] $ (!\m_x|data [0] $ (!\m_x|data [8] $ (!\m_x|data_l_r [7]))) ) )
.dataa(!\m_x|data_l_r [6]),
.datab(!\m_x|data [0]),
.datac(!\m_x|data [8]),
.datad(!\m_x|data_l_r [7]),
.datae(!\m_x|data_l_r [5]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always9~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always9~1 .extended_lut = "off";
defparam \m_x|always9~1 .lut_mask = 64'h6996966969969669;
defparam \m_x|always9~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y7_N0
cyclonev_lcell_comb \m_x|rx_error~1 (
// Equation(s):
// \m_x|rx_error~1_combout = ( \m_x|always9~1_combout & ( (\m_x|last_was_data~q & (!\m_x|last_was_timec~q & (!\m_x|always9~2_combout $ (!\m_x|data_l_r [4])))) ) ) # ( !\m_x|always9~1_combout & ( (\m_x|last_was_data~q & (!\m_x|last_was_timec~q &
// (!\m_x|always9~2_combout $ (\m_x|data_l_r [4])))) ) )
.dataa(!\m_x|last_was_data~q ),
.datab(!\m_x|last_was_timec~q ),
.datac(!\m_x|always9~2_combout ),
.datad(!\m_x|data_l_r [4]),
.datae(gnd),
.dataf(!\m_x|always9~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~1 .extended_lut = "off";
defparam \m_x|rx_error~1 .lut_mask = 64'h4004400404400440;
defparam \m_x|rx_error~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X32_Y7_N24
cyclonev_lcell_comb \m_x|rx_error~10 (
// Equation(s):
// \m_x|rx_error~10_combout = ( \m_x|rx_error~5_combout & ( \m_x|rx_error~1_combout ) ) # ( !\m_x|rx_error~5_combout & ( \m_x|rx_error~1_combout & ( (!\m_x|rx_error~9_combout ) # ((\m_x|rx_error~4_combout ) # (\m_x|rx_error~2_combout )) ) ) ) # (
// \m_x|rx_error~5_combout & ( !\m_x|rx_error~1_combout & ( (!\m_x|rx_error~9_combout ) # (((\m_x|rx_error~4_combout ) # (\m_x|rx_error~0_combout )) # (\m_x|rx_error~2_combout )) ) ) ) # ( !\m_x|rx_error~5_combout & ( !\m_x|rx_error~1_combout & (
// (!\m_x|rx_error~9_combout ) # ((\m_x|rx_error~4_combout ) # (\m_x|rx_error~2_combout )) ) ) )
.dataa(!\m_x|rx_error~9_combout ),
.datab(!\m_x|rx_error~2_combout ),
.datac(!\m_x|rx_error~0_combout ),
.datad(!\m_x|rx_error~4_combout ),
.datae(!\m_x|rx_error~5_combout ),
.dataf(!\m_x|rx_error~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_error~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_error~10 .extended_lut = "off";
defparam \m_x|rx_error~10 .lut_mask = 64'hBBFFBFFFBBFFFFFF;
defparam \m_x|rx_error~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N29
dffeas \m_x|rx_error (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|rx_error~10_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|rx_error~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|rx_error .is_wysiwyg = "true";
defparam \m_x|rx_error .power_up = "low";
// synopsys translate_on
// Location: FF_X33_Y7_N16
dffeas \m_x|info[5] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|rx_error~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [5]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[5] .is_wysiwyg = "true";
defparam \m_x|info[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N39
cyclonev_lcell_comb \u0|data_info|read_mux_out[5] (
// Equation(s):
// \u0|data_info|read_mux_out [5] = ( \m_x|info [5] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [5]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[5] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[5] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[5] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N41
dffeas \u0|data_info|readdata[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [5]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[5] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N34
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [5]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y18_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N32
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q & (
// (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 .lut_mask = 64'h0003000330333033;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N23
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N54
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[5] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [5] = (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|SPW|RX|timecode [5]))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\A_SPW_TOP|SPW|RX|timecode [5]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [5]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[5] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[5] .lut_mask = 64'h0808080808080808;
defparam \u0|timecode_rx|read_mux_out[5] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N56
dffeas \u0|timecode_rx|readdata[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [5]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[5] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N1
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [5]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N37
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 .lut_mask = 64'h0B0B0B0B4F4F4F4F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout
// & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout & !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout &
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout & (
// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout & !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout & !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 .lut_mask = 64'hA000F00020003000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 .lut_mask = 64'hFFFFFFFF5757FFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]
// & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & (
// (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout )))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 .lut_mask = 64'hA080800080000000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout )) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1 .lut_mask = 64'h8A8A8A8A02020202;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant
// [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[81] .lut_mask = 64'h3F333F330F000F00;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N2
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|src_data [81]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_014|src_data [81] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [81] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [2]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00DD00DD00880088;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout & ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])))
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0537053705370537;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & ( (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [2] & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))
// # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h0A2A0A2A5F7F5F7F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y20_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N24
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[4] (
// Equation(s):
// \u0|timecode_tx_data|readdata [4] = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\u0|timecode_tx_data|data_out [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [4]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[4] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[4] .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|timecode_tx_data|readdata[4] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_tx_data|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y16_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N25
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 .lut_mask = 64'h0000000023732373;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N12
cyclonev_lcell_comb \m_x|always0~0 (
// Equation(s):
// \m_x|always0~0_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_e~q & ( \A_SPW_TOP|SPW|TX|tx_sout_e~q ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout_e~q & ( \A_SPW_TOP|SPW|TX|tx_sout_e~q ) ) # ( \A_SPW_TOP|SPW|TX|tx_dout_e~q & ( !\A_SPW_TOP|SPW|TX|tx_sout_e~q ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_sout_e~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always0~0 .extended_lut = "off";
defparam \m_x|always0~0 .lut_mask = 64'h0000FFFFFFFFFFFF;
defparam \m_x|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N13
dffeas \m_x|info[4] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|always0~0_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [4]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[4] .is_wysiwyg = "true";
defparam \m_x|info[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N42
cyclonev_lcell_comb \u0|data_info|read_mux_out[4] (
// Equation(s):
// \u0|data_info|read_mux_out [4] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \m_x|info [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\m_x|info [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [4]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[4] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[4] .lut_mask = 64'h0C0C00000C0C0000;
defparam \u0|data_info|read_mux_out[4] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N43
dffeas \u0|data_info|readdata[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [4]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[4] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y18_N11
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y12_N2
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[17] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [17]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[17] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[17] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y12_N50
dffeas \A_SPW_TOP|rx_data|mem~5 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [4]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~5_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~5 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~5 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N48
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~8 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~8_combout = (!\A_SPW_TOP|rx_data|mem~0_q & ((\A_SPW_TOP|rx_data|mem~5_q ))) # (\A_SPW_TOP|rx_data|mem~0_q & (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a4 ))
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a4 ),
.datac(gnd),
.datad(!\A_SPW_TOP|rx_data|mem~5_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~8 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~8 .lut_mask = 64'h11BB11BB11BB11BB;
defparam \A_SPW_TOP|rx_data|data_out~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~9 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~9_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [17] & ( \A_SPW_TOP|rx_data|data_out~8_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [17] & ( \A_SPW_TOP|rx_data|data_out~8_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [17] & (
// !\A_SPW_TOP|rx_data|data_out~8_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datad(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [17]),
.dataf(!\A_SPW_TOP|rx_data|data_out~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~9 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~9 .lut_mask = 64'h00000041FFBEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N13
dffeas \A_SPW_TOP|rx_data|data_out[4] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~9_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [4]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[4] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N12
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[4] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [4] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [4] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|data_out [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [4]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[4] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[4] .lut_mask = 64'h0F0F000000000000;
defparam \u0|data_flag_rx|read_mux_out[4] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N14
dffeas \u0|data_flag_rx|readdata[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [4]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[4] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N13
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y18_N2
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]))) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ))
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N31
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4] ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 .lut_mask = 64'h0F0F555500000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N27
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[4] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [4] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \A_SPW_TOP|SPW|RX|timecode [4] ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|timecode [4]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [4]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[4] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[4] .lut_mask = 64'h5555000000000000;
defparam \u0|timecode_rx|read_mux_out[4] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N29
dffeas \u0|timecode_rx|readdata[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [4]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[4] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N26
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y18_N20
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N8
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4] ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 .lut_mask = 64'h33330F0F33333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [4] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WDATA [4]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~4 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y26_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[82] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N50
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N10
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [86] = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (
// \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[86] .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y26_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (
// (\u0|mm_interconnect_0|cmd_mux|src_data [87] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|cmd_mux|src_data [88])) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux|src_data [87] & ((!\u0|mm_interconnect_0|cmd_mux|src_data [88])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|src_data [87]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h1D0C1D0C11001100;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux|src_data [86])))))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h1013101310131013;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux|src_data [86])))))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h2230223022302230;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N59
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[81] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( !\u0|mm_interconnect_0|cmd_mux|src_data [87] & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|cmd_mux|src_data [88]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux|src_data [87] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|src_data [87] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux|src_data [88])) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux|src_data [88]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(!\u0|mm_interconnect_0|cmd_mux|src_data [87]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hFC30CC0030300000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux|src_data [86]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h0000000055335533;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [80] = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[80] .lut_mask = 64'h5F5F0F0F55550000;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y25_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux|src_data [86])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|src_data [86]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N7
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h0000555533337777;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_data [79] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_data[79] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_data [79]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux|src_data [79]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux|src_data [79]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F5A0F5A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h333F0000333F5555;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N49
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// ((\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux|src_data [80] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [80] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])
// # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [80]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N16
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h03030055FFFF0055;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N1
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux|src_data [81] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [81] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00AF00AF00A000A0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( ((\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & (
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h1F001F001FFF1FFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y25_N46
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux|src_data [82] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] &
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|src_data [82] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|src_data [82]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y26_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h05330533FF33FF33;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y25_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N36
cyclonev_lcell_comb \u0|led_pio_test|always0~0 (
// Equation(s):
// \u0|led_pio_test|always0~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout & (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter
// [0]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|led_pio_test|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|led_pio_test|always0~0 .extended_lut = "off";
defparam \u0|led_pio_test|always0~0 .lut_mask = 64'h2000200000000000;
defparam \u0|led_pio_test|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y26_N56
dffeas \u0|led_pio_test|data_out[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|led_pio_test|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|led_pio_test|data_out [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[4] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N33
cyclonev_lcell_comb \u0|led_pio_test|readdata[4] (
// Equation(s):
// \u0|led_pio_test|readdata [4] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \u0|led_pio_test|data_out [4] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|led_pio_test|data_out [4]),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|led_pio_test|readdata [4]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[4] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[4] .lut_mask = 64'h00FF000000000000;
defparam \u0|led_pio_test|readdata[4] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|led_pio_test|readdata [4]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4] ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4] & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h00000F0FF0F0FFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCFCFCFCF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N49
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4])) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [4]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 .lut_mask = 64'h3535353533333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout )) # (\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ) # (\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 .lut_mask = 64'h00FFF0FF55FFF5FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N17
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout )) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h2722272205000500;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000035353535;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y22_N37
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N26
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0010001000000000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00BB00BB00880088;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N40
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// ( (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout )) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout & ((!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hE2C0E2C022002200;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h000000001B1B1B1B;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N59
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// ( ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout
// ) # ((\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hF0F3F0F3FFF3FFF3;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout =
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N58
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N47
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h5055505550005000;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N25
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h05050030FFFF0030;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y22_N49
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & (
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) #
// ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0FCF0FCF4FCF4FCF;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y23_N37
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N14
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0101CDCD01CDCDCD;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N32
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00E200E200F300F3;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N19
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y22_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) ) # (
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout &
// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h03030055FFFF0055;
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y22_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y22_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N51
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[4]~4 (
// Equation(s):
// \u0|fsm_info|read_mux_out[4]~4_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|FSM|state_fsm.run~q &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.run~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fsm_info|read_mux_out[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[4]~4 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[4]~4 .lut_mask = 64'h5050505000000000;
defparam \u0|fsm_info|read_mux_out[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N52
dffeas \u0|fsm_info|readdata[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fsm_info|read_mux_out[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fsm_info|readdata [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[4] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N2
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fsm_info|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N5
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4])) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q )))
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h4477447744774477;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFFFFFFF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N13
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q )))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q &
// !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 .lut_mask = 64'h3030303010B010B0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N27
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[4] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [4] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|write_data_fifo_tx|data_out [4] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\u0|write_data_fifo_tx|data_out [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [4]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[4] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[4] .lut_mask = 64'h5050505000000000;
defparam \u0|write_data_fifo_tx|readdata[4] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N29
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [4]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N45
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[4]~4 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[4]~4_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|rx_data|counter [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\A_SPW_TOP|rx_data|counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_rx_fifo|read_mux_out[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[4]~4 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[4]~4 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|counter_rx_fifo|read_mux_out[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N47
dffeas \u0|counter_rx_fifo|readdata[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_rx_fifo|read_mux_out[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_rx_fifo|readdata [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[4] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N23
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_rx_fifo|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N25
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N31
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [4]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 .lut_mask = 64'h00004040B0B0F0F0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N6
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[4]~4 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[4]~4_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|tx_data|counter [4]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\A_SPW_TOP|tx_data|counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_tx_fifo|read_mux_out[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[4]~4 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[4]~4 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|counter_tx_fifo|read_mux_out[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N8
dffeas \u0|counter_tx_fifo|readdata[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_tx_fifo|read_mux_out[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_tx_fifo|readdata [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[4] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N55
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_tx_fifo|readdata [4]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y17_N29
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ))))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [4]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 .lut_mask = 64'h00AA00AA082A082A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N56
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4])) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [4]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ),
.datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N49
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout )
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4])) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [4]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout & \u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 .lut_mask = 64'h000F000FFF0FFF0F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y29_N50
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[16] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[16] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[16] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~7 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~7 .lut_mask = 64'hE4A0E4A044004400;
defparam \u0|mm_interconnect_0|router|Equal7~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~8 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~8_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout & ( \u0|mm_interconnect_0|router|Equal7~7_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|router|Equal7~7_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~8 .lut_mask = 64'h00FF00FF00000000;
defparam \u0|mm_interconnect_0|router|Equal7~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[103]~5 (
// Equation(s):
// \u0|mm_interconnect_0|router|src_data[103]~5_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (((\u0|mm_interconnect_0|router|Equal6~2_combout & \u0|mm_interconnect_0|router|Equal6~0_combout )))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (((\u0|mm_interconnect_0|router|Equal6~2_combout &
// \u0|mm_interconnect_0|router|Equal6~0_combout )) # (\u0|mm_interconnect_0|router|Equal7~8_combout ))) ) ) # ( !\u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|router|Equal6~2_combout &
// \u0|mm_interconnect_0|router|Equal6~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal7~8_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|src_data[103]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|src_data[103]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|src_data[103]~5 .lut_mask = 64'h000F000F111F111F;
defparam \u0|mm_interconnect_0|router|src_data[103]~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout = ( !\u0|mm_interconnect_0|router|src_data[103]~4_combout & ( (!\u0|mm_interconnect_0|router|src_data[103]~5_combout & \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|src_data[103]~5_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|src_data[103]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &
// ((!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout & (!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout & ((\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ))))) #
// (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & (
// (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & (!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ((\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout & \u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 .lut_mask = 64'h30300033A0F580F7;
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N1
dffeas \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0] & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout & \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0] & ( (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout & ((!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ) # (\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 .lut_mask = 64'h0C0F0C0F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1_combout = ( !\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N35
dffeas \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]) # ((!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout &
// \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 .lut_mask = 64'h00000000F0FCF0FC;
defparam \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y26_N26
dffeas \u0|mm_interconnect_0|cmd_mux|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y26_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1])))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout & (((\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1])) # (\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h0000000007B707B7;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & !\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter [0]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 .lut_mask = 64'h330033003B00B300;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0F0F0F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y26_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y26_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h227722770A5F0A5F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y30_N53
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q )) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout
// & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0404000007040300;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N44
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00FF00FF005F005F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout )) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00AA00AA000A000A;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y30_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h00000F0F00000F0F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q &
// ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout & !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ) #
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FC00FC00F800F8;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ))) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout & (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1030103050F050F0;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00BF00BFFFFFFFFF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0] &
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q & (
// (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid .lut_mask = 64'hC0C0C0C080808080;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux|src1_valid~combout = (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux|src1_valid .lut_mask = 64'hF000F000F000F000;
defparam \u0|mm_interconnect_0|rsp_demux|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y12_N29
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[16] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [16]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[16] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[16] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y12_N11
dffeas \A_SPW_TOP|rx_data|mem~4 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [3]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~4_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~4 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~4 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N9
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~6 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~6_combout = (!\A_SPW_TOP|rx_data|mem~0_q & ((\A_SPW_TOP|rx_data|mem~4_q ))) # (\A_SPW_TOP|rx_data|mem~0_q & (\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a3 ))
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a3 ),
.datad(!\A_SPW_TOP|rx_data|mem~4_q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~6 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~6 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \A_SPW_TOP|rx_data|data_out~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N33
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~7 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~7_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [16] & ( \A_SPW_TOP|rx_data|data_out~6_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [16] & ( \A_SPW_TOP|rx_data|data_out~6_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [16] & (
// !\A_SPW_TOP|rx_data|data_out~6_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [16]),
.dataf(!\A_SPW_TOP|rx_data|data_out~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~7 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~7 .lut_mask = 64'h00000401FBFEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N35
dffeas \A_SPW_TOP|rx_data|data_out[3] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~7_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [3]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[3] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N57
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[3] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [3] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [3] ) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out [3]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[3] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[3] .lut_mask = 64'h5555000000000000;
defparam \u0|data_flag_rx|read_mux_out[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N59
dffeas \u0|data_flag_rx|readdata[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[3] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N56
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [3]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N38
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3] & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 .lut_mask = 64'h00C000C00CCC0CCC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [3] ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_WDATA [3]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~3 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y26_N38
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y26_N5
dffeas \u0|led_pio_test|data_out[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [3]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|led_pio_test|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|led_pio_test|data_out [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[3] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N12
cyclonev_lcell_comb \u0|led_pio_test|readdata[3] (
// Equation(s):
// \u0|led_pio_test|readdata [3] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \u0|led_pio_test|data_out [3] ) ) )
.dataa(gnd),
.datab(!\u0|led_pio_test|data_out [3]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|led_pio_test|readdata [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[3] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[3] .lut_mask = 64'h3333000000000000;
defparam \u0|led_pio_test|readdata[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|led_pio_test|readdata [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y26_N26
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N5
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ))) #
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3])) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [3]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 .lut_mask = 64'h05AF05AF00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N47
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N51
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[3] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [3] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \A_SPW_TOP|SPW|RX|timecode [3] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|timecode [3]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[3] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[3] .lut_mask = 64'h0F0F000000000000;
defparam \u0|timecode_rx|read_mux_out[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N53
dffeas \u0|timecode_rx|readdata[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[3] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N52
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [3]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N55
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q )) #
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [3]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 .lut_mask = 64'h330F330F33333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( ((\u0|mm_interconnect_0|rsp_demux|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (((\u0|mm_interconnect_0|rsp_demux|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 .lut_mask = 64'h37FF37FF37373737;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N54
cyclonev_lcell_comb \m_x|always10~0 (
// Equation(s):
// \m_x|always10~0_combout = ( \m_x|last_is_control~q & ( !\m_x|control [1] & ( (\m_x|control [2] & !\m_x|control [0]) ) ) )
.dataa(!\m_x|control [2]),
.datab(gnd),
.datac(!\m_x|control [0]),
.datad(gnd),
.datae(!\m_x|last_is_control~q ),
.dataf(!\m_x|control [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|always10~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|always10~0 .extended_lut = "off";
defparam \m_x|always10~0 .lut_mask = 64'h0000505000000000;
defparam \m_x|always10~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N15
cyclonev_lcell_comb \m_x|rx_got_null~1 (
// Equation(s):
// \m_x|rx_got_null~1_combout = ( !\m_x|last_is_data~q & ( \m_x|always10~0_combout & ( (\m_x|control_l_r [1] & (\m_x|control_l_r [0] & \m_x|control_l_r [2])) ) ) ) # ( !\m_x|last_is_data~q & ( !\m_x|always10~0_combout ) )
.dataa(!\m_x|control_l_r [1]),
.datab(!\m_x|control_l_r [0]),
.datac(gnd),
.datad(!\m_x|control_l_r [2]),
.datae(!\m_x|last_is_data~q ),
.dataf(!\m_x|always10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_got_null~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_got_null~1 .extended_lut = "off";
defparam \m_x|rx_got_null~1 .lut_mask = 64'hFFFF000000110000;
defparam \m_x|rx_got_null~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N48
cyclonev_lcell_comb \m_x|rx_got_null~0 (
// Equation(s):
// \m_x|rx_got_null~0_combout = ( \m_x|last_is_data~q & ( \m_x|last_is_control~q ) ) # ( !\m_x|last_is_data~q & ( \m_x|last_is_control~q & ( (!\m_x|control [1] & (!\m_x|control [0] & \m_x|control [2])) ) ) ) # ( \m_x|last_is_data~q & (
// !\m_x|last_is_control~q ) )
.dataa(!\m_x|control [1]),
.datab(!\m_x|control [0]),
.datac(!\m_x|control [2]),
.datad(gnd),
.datae(!\m_x|last_is_data~q ),
.dataf(!\m_x|last_is_control~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_got_null~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_got_null~0 .extended_lut = "off";
defparam \m_x|rx_got_null~0 .lut_mask = 64'h0000FFFF0808FFFF;
defparam \m_x|rx_got_null~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y7_N16
dffeas \m_x|rx_got_null (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|rx_got_null~1_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|rx_got_null~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|rx_got_null~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_null .is_wysiwyg = "true";
defparam \m_x|rx_got_null .power_up = "low";
// synopsys translate_on
// Location: FF_X33_Y7_N11
dffeas \m_x|info[3] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|rx_got_null~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [3]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[3] .is_wysiwyg = "true";
defparam \m_x|info[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N48
cyclonev_lcell_comb \u0|data_info|read_mux_out[3] (
// Equation(s):
// \u0|data_info|read_mux_out [3] = (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \m_x|info [3]))
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\m_x|info [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[3] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[3] .lut_mask = 64'h0808080808080808;
defparam \u0|data_info|read_mux_out[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N49
dffeas \u0|data_info|readdata[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[3] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder_combout = \u0|data_info|readdata [3]
.dataa(gnd),
.datab(gnd),
.datac(!\u0|data_info|readdata [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N10
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y17_N20
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N48
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[3]~3 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[3]~3_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|tx_data|counter [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(gnd),
.datad(!\A_SPW_TOP|tx_data|counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_tx_fifo|read_mux_out[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[3]~3 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[3]~3 .lut_mask = 64'h00CC00CC00000000;
defparam \u0|counter_tx_fifo|read_mux_out[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N49
dffeas \u0|counter_tx_fifo|readdata[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_tx_fifo|read_mux_out[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_tx_fifo|readdata [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[3] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N23
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_tx_fifo|readdata [3]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q )))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 .lut_mask = 64'h2222222202A202A2;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N29
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N42
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[3]~3 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[3]~3_combout = ( \A_SPW_TOP|rx_data|counter [3] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_rx_fifo|read_mux_out[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[3]~3 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[3]~3 .lut_mask = 64'h0000000088888888;
defparam \u0|counter_rx_fifo|read_mux_out[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N43
dffeas \u0|counter_rx_fifo|readdata[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_rx_fifo|read_mux_out[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_rx_fifo|readdata [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[3] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_rx_fifo|readdata [3]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N34
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]))))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [3]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 .lut_mask = 64'h5300530055005500;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N36
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[3] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [3] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|write_data_fifo_tx|data_out [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\u0|write_data_fifo_tx|data_out [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[3] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[3] .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|write_data_fifo_tx|readdata[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N38
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N39
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[3]~3 (
// Equation(s):
// \u0|fsm_info|read_mux_out[3]~3_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fsm_info|read_mux_out[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[3]~3 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[3]~3 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|fsm_info|read_mux_out[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N41
dffeas \u0|fsm_info|readdata[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fsm_info|read_mux_out[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fsm_info|readdata [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[3] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N8
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fsm_info|readdata [3]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N11
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3] &
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h303030303F3F3F3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N44
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q
// ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] &
// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3])) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [3]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ),
.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 .lut_mask = 64'h03F300FF00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N41
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3] ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N49
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q &
// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3] & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [3]),
.datad(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ),
.datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 .lut_mask = 64'h777F777FFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N9
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[3] (
// Equation(s):
// \u0|timecode_tx_data|readdata [3] = ( \u0|timecode_tx_data|data_out [3] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datae(gnd),
.dataf(!\u0|timecode_tx_data|data_out [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[3] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[3] .lut_mask = 64'h00000000AA00AA00;
defparam \u0|timecode_tx_data|readdata[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y16_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] &
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 .lut_mask = 64'h0000000004BF04BF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N47
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N38
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout )
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3])) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [3]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) # ((!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFCCCFCCCFCCCFCCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y19_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .lut_mask = 64'h20202020AAAAAAAA;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y19_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F0A0F0A000A000A;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFEFFFEF00000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h3300FFCC3300FFCC;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q
// )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q
// & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00310011CCFDCCDD;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0333033300000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) )
// ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hF0F0F0F0F000F000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &
// (\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h001100110F1F0F1F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y19_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N47
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h00000F000F000F00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000000F000F0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout
// ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N26
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .lut_mask = 64'h0055005500000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &
// ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFF55FFFFFF0000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N41
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y20_N44
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h53A353A350A050A0;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N31
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .lut_mask = 64'h4040B0B0404FB0BF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hBFBFBFBF40404040;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .lut_mask = 64'hAAAFAAAF00050005;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &
// ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h01AB01ABAB01AB01;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N8
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h3035C0C50005F0F5;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h40000000FFFFFFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y20_N50
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) )
// ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hF070F00000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h08080808FF00FF00;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout
// & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout
// ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hC0C0C0C080008000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q & ( (!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q & ( (\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout
// & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 .lut_mask = 64'h0101FBFB0101FBFB;
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N56
dffeas \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (
// !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 .lut_mask = 64'hF0F0F0F0F0F0FF00;
defparam \u0|mm_interconnect_0|cmd_mux_020|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y19_N26
dffeas \u0|mm_interconnect_0|cmd_mux_020|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_020|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_020|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y19_N31
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &
// ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .lut_mask = 64'h8000800080000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y17_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h1111111111FF11FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N2
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .lut_mask = 64'hE0E0E0E000000000;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N21
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[2]~2 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[2]~2_combout = ( \A_SPW_TOP|tx_data|counter [2] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_tx_fifo|read_mux_out[2]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[2]~2 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[2]~2 .lut_mask = 64'h0000000088888888;
defparam \u0|counter_tx_fifo|read_mux_out[2]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N22
dffeas \u0|counter_tx_fifo|readdata[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_tx_fifo|read_mux_out[2]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_tx_fifo|readdata [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[2] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_tx_fifo|readdata [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] ) ) # (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2] ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h00FF00FF0000FFFF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N11
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ))))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 .lut_mask = 64'h00AA00AA082A082A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N6
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[2] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [2] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|write_data_fifo_tx|data_out [2]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\u0|write_data_fifo_tx|data_out [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[2] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[2] .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|write_data_fifo_tx|readdata[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N8
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N33
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[2]~2 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[2]~2_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \A_SPW_TOP|rx_data|counter [2]))
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\A_SPW_TOP|rx_data|counter [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_rx_fifo|read_mux_out[2]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[2]~2 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[2]~2 .lut_mask = 64'h00A000A000A000A0;
defparam \u0|counter_rx_fifo|read_mux_out[2]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N34
dffeas \u0|counter_rx_fifo|readdata[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_rx_fifo|read_mux_out[2]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_rx_fifo|readdata [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[2] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N11
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_rx_fifo|readdata [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N5
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2])) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N44
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2] & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [2]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 .lut_mask = 64'h00002020AAAA2A2A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N35
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N36
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[2]~2 (
// Equation(s):
// \u0|fsm_info|read_mux_out[2]~2_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|SPW|FSM|state_fsm.started~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.started~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fsm_info|read_mux_out[2]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[2]~2 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[2]~2 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|fsm_info|read_mux_out[2]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N38
dffeas \u0|fsm_info|readdata[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fsm_info|read_mux_out[2]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fsm_info|readdata [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[2] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N41
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fsm_info|readdata [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N46
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// (((!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 .lut_mask = 64'h3010301030B030B0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N11
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2])) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ),
.datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N21
cyclonev_lcell_comb \m_x|rx_got_nchar~0 (
// Equation(s):
// \m_x|rx_got_nchar~0_combout = ( \m_x|last_is_data~q & ( (!\m_x|control [2]) # ((!\m_x|control [0]) # (!\m_x|control [1])) ) )
.dataa(!\m_x|control [2]),
.datab(gnd),
.datac(!\m_x|control [0]),
.datad(!\m_x|control [1]),
.datae(!\m_x|last_is_data~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_got_nchar~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_got_nchar~0 .extended_lut = "off";
defparam \m_x|rx_got_nchar~0 .lut_mask = 64'h0000FFFA0000FFFA;
defparam \m_x|rx_got_nchar~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N36
cyclonev_lcell_comb \m_x|rx_got_nchar~1 (
// Equation(s):
// \m_x|rx_got_nchar~1_combout = ( \m_x|control_l_r [2] & ( \m_x|control_l_r [1] & ( (\m_x|rx_got_nchar~0_combout & ((!\m_x|always10~0_combout ) # (\m_x|control_l_r [0]))) ) ) ) # ( !\m_x|control_l_r [2] & ( \m_x|control_l_r [1] & (
// (\m_x|rx_got_nchar~0_combout & !\m_x|always10~0_combout ) ) ) ) # ( \m_x|control_l_r [2] & ( !\m_x|control_l_r [1] & ( (\m_x|rx_got_nchar~0_combout & !\m_x|always10~0_combout ) ) ) ) # ( !\m_x|control_l_r [2] & ( !\m_x|control_l_r [1] & (
// (\m_x|rx_got_nchar~0_combout & !\m_x|always10~0_combout ) ) ) )
.dataa(!\m_x|rx_got_nchar~0_combout ),
.datab(!\m_x|control_l_r [0]),
.datac(!\m_x|always10~0_combout ),
.datad(gnd),
.datae(!\m_x|control_l_r [2]),
.dataf(!\m_x|control_l_r [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_got_nchar~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_got_nchar~1 .extended_lut = "off";
defparam \m_x|rx_got_nchar~1 .lut_mask = 64'h5050505050505151;
defparam \m_x|rx_got_nchar~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y7_N37
dffeas \m_x|rx_got_nchar (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|rx_got_nchar~1_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|rx_got_null~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|rx_got_nchar~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_nchar .is_wysiwyg = "true";
defparam \m_x|rx_got_nchar .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N6
cyclonev_lcell_comb \m_x|info[2]~feeder (
// Equation(s):
// \m_x|info[2]~feeder_combout = ( \m_x|rx_got_nchar~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|rx_got_nchar~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|info[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|info[2]~feeder .extended_lut = "off";
defparam \m_x|info[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|info[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N7
dffeas \m_x|info[2] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|info[2]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [2]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[2] .is_wysiwyg = "true";
defparam \m_x|info[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N57
cyclonev_lcell_comb \u0|data_info|read_mux_out[2] (
// Equation(s):
// \u0|data_info|read_mux_out [2] = ( \m_x|info [2] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[2] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[2] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N59
dffeas \u0|data_info|readdata[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[2] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X31_Y10_N7
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout = ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~2 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y26_N31
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y26_N8
dffeas \u0|led_pio_test|data_out[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|led_pio_test|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|led_pio_test|data_out [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[2] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N9
cyclonev_lcell_comb \u0|led_pio_test|readdata[2] (
// Equation(s):
// \u0|led_pio_test|readdata [2] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \u0|led_pio_test|data_out [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|led_pio_test|data_out [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|led_pio_test|readdata [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[2] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[2] .lut_mask = 64'h0F0F000000000000;
defparam \u0|led_pio_test|readdata[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N11
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|led_pio_test|readdata [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N1
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2] & ( ((!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 .lut_mask = 64'h515151515D5D5D5D;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder_combout = ( \A_SPW_TOP|SPW|RX|rx_data_flag [2] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N5
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [15]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y12_N8
dffeas \A_SPW_TOP|rx_data|mem~3 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [2]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~3_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~3 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~3 .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N6
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~4 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~4_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 & ( (\A_SPW_TOP|rx_data|mem~3_q ) # (\A_SPW_TOP|rx_data|mem~0_q ) ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 & (
// (!\A_SPW_TOP|rx_data|mem~0_q & \A_SPW_TOP|rx_data|mem~3_q ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(gnd),
.datac(gnd),
.datad(!\A_SPW_TOP|rx_data|mem~3_q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~4 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~4 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \A_SPW_TOP|rx_data|data_out~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~5 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~5_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [15] & ( \A_SPW_TOP|rx_data|data_out~4_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [15] & ( \A_SPW_TOP|rx_data|data_out~4_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [15] & (
// !\A_SPW_TOP|rx_data|data_out~4_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datad(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [15]),
.dataf(!\A_SPW_TOP|rx_data|data_out~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~5 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~5 .lut_mask = 64'h00000041FFBEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N31
dffeas \A_SPW_TOP|rx_data|data_out[2] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~5_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [2]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[2] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N21
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[2] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [2] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|data_out [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[2] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[2] .lut_mask = 64'h0F0F000000000000;
defparam \u0|data_flag_rx|read_mux_out[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N23
dffeas \u0|data_flag_rx|readdata[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[2] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N20
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y18_N19
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0F000F000FFF0FFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N55
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2])) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [2]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 .lut_mask = 64'h1D1D1D1D00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N15
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[2] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [2] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|RX|timecode [2] &
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|timecode [2]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[2] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[2] .lut_mask = 64'h0F000F0000000000;
defparam \u0|timecode_rx|read_mux_out[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N17
dffeas \u0|timecode_rx|readdata[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[2] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N16
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y18_N44
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2] &
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h4444444477777777;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N52
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 .lut_mask = 64'h0F550F550F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ) # ((\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout & \u0|mm_interconnect_0|rsp_demux|src1_valid~combout )) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout & \u0|mm_interconnect_0|rsp_demux|src1_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 .lut_mask = 64'h0505FFFFCDCDFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h30FF30FF30303030;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout )) ) )
// # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant
// [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h208A208A75DF75DF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [3] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hC3F0C3F0F0F0F0F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) ) ) )
// # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]))) #
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) ) )
// )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 .lut_mask = 64'hF0F5F3F700050307;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout )) ) )
// # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .lut_mask = 64'h05AF05AFAF05AF05;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout )))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h05AF05AF8D278D27;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'hFFFFFFFF20000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y20_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[81] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [81] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [81]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[81] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[81] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[81] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N23
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [81]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [81] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [81] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [81]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y20_N28
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[86] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [86] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[86] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[86] .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[86] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y23_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y23_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_018|src_data [87] & (!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|src_data [87] & (!\u0|mm_interconnect_0|cmd_mux_018|src_data [88] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h04040404F404F404;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N35
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [87] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|cmd_mux_018|src_data [88]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|src_data [87] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_018|src_data [87] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|src_data [88]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|src_data [87]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'hB8B8888830300000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h1010101015151515;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'h4455445544004400;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[79] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [79] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ) )
// ) # ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ) #
// (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [79]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[79] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[79] .lut_mask = 64'h5555DDDD0000CCCC;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[79] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|src_data [79]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout &
// ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_018|src_data [79]))))
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_data [79]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00E200E200E200E2;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N17
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h030303FF030303FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ( ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .lut_mask = 64'h03FF000003FF5555;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N37
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout &
// ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h00550F5F00550F5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[80] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [80] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant
// [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [80]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[80] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[80] .lut_mask = 64'h7733773355005500;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[80] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [80]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [80] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [80] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [80]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N25
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) )
// # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]
// & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )))) )
// ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h00110C1DCCDDCCDD;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N44
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2])))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .lut_mask = 64'h1D1D1D1D1DDD1DDD;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_data[82] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_data [82] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ) ) )
// # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant
// [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_data [82]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[82] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[82] .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_data[82] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y20_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_data [82]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout )) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [3] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]
// & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0033003355775577;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N4
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_data [86] & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_data [86]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h03000300030F030F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F000005555;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_018|src_data [82]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|src_data [82]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000BB88BB88;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y20_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout )))) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h03470347CFCFCFCF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y20_N41
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N27
cyclonev_lcell_comb \u0|clock_sel|readdata[2]~2 (
// Equation(s):
// \u0|clock_sel|readdata[2]~2_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\u0|clock_sel|data_out [2] &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(gnd),
.datab(!\u0|clock_sel|data_out [2]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|clock_sel|readdata[2]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|clock_sel|readdata[2]~2 .extended_lut = "off";
defparam \u0|clock_sel|readdata[2]~2 .lut_mask = 64'h3030303000000000;
defparam \u0|clock_sel|readdata[2]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N38
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|clock_sel|readdata[2]~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y18_N50
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N20
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]))) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q )) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 .lut_mask = 64'h555555551D1D1D1D;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N30
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[2] (
// Equation(s):
// \u0|timecode_tx_data|readdata [2] = (\u0|timecode_tx_data|data_out [2] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]))
.dataa(!\u0|timecode_tx_data|data_out [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[2] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[2] .lut_mask = 64'h5000500050005000;
defparam \u0|timecode_tx_data|readdata[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y16_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N4
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 .lut_mask = 64'h0F0F0F0F27272727;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout & ( ((\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout )) #
// (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N7
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]))) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y18_N19
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout )
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2])) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [2]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal2~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal2~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [15] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [13]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [15]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [13]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal2~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal2~0 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|router_001|Equal2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal4~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal4~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( \u0|mm_interconnect_0|router_001|Equal2~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal4~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal4~0 .lut_mask = 64'h0000000000001000;
defparam \u0|mm_interconnect_0|router_001|Equal4~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N44
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[17] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[17] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[17] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17] & ( \u0|mm_interconnect_0|router_001|Equal4~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17] & ( \u0|mm_interconnect_0|router_001|Equal4~0_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_ARVALID
// [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [17]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 .lut_mask = 64'h000000000C0C0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q &
// ((!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 .lut_mask = 64'h05FF05FF00FA00FA;
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y20_N8
dffeas \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & ((!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ))) #
// (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 .lut_mask = 64'hF0F0F0F0F033F033;
defparam \u0|mm_interconnect_0|cmd_mux_017|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y20_N17
dffeas \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y20_N53
dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) # (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) #
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 .lut_mask = 64'h5F7FFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout = (\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q &
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ))
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0005000500050005;
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout &
// \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N44
dffeas \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & (
// ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N38
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout = (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ) #
// (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0])))
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .lut_mask = 64'h070F070F070F070F;
defparam \u0|mm_interconnect_0|data_info_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout = (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0505050505050505;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N53
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]
// & ((!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// ((\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h025702578ADF8ADF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N53
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0055005522772277;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N23
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg
// [5]))) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ))))
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0257025702570257;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h005500550A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y17_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y17_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used
// [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000F000F303F303F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N11
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q &
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q )) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q
// & ( (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q )))
// # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ))) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h3210230110320123;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N44
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]
// & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5F5F5F5FA0A0A0A0;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q $
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000C30F0000AAAA;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]
// & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( ((\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FFF5FFFA000A000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q &
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CCC3CCCCCCCCCCC;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout )
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00F000F000CC00CC;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N14
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter
// [4] & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q $
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0060006F006F0060;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N8
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout &
// ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )))) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout
// & (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h000000A0000044E4;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N2
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q & (
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F5FFF5FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout &
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00C000C000F000F0;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y18_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q
// ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q & (
// (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q & (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y20_N5
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y20_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]
// & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N20
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FECCFECC;
defparam \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1])) #
// (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00DF00DFFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N17
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & (
// ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent|rp_valid .lut_mask = 64'h0F3F0F3FFFFFFFFF;
defparam \u0|mm_interconnect_0|data_info_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N27
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder_combout = \A_SPW_TOP|SPW|RX|rx_data_flag [1]
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N29
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [14]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N14
dffeas \A_SPW_TOP|rx_data|mem~2 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [1]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~2_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~2 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~2 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N12
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~2 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~2_combout = ( \A_SPW_TOP|rx_data|mem~2_q & ( \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 ) ) # ( !\A_SPW_TOP|rx_data|mem~2_q & ( \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 & (
// \A_SPW_TOP|rx_data|mem~0_q ) ) ) # ( \A_SPW_TOP|rx_data|mem~2_q & ( !\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 & ( !\A_SPW_TOP|rx_data|mem~0_q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|rx_data|mem~0_q ),
.datad(gnd),
.datae(!\A_SPW_TOP|rx_data|mem~2_q ),
.dataf(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~2 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~2 .lut_mask = 64'h0000F0F00F0FFFFF;
defparam \A_SPW_TOP|rx_data|data_out~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N39
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~3 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~3_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [14] & ( \A_SPW_TOP|rx_data|data_out~2_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [14] & ( \A_SPW_TOP|rx_data|data_out~2_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [14] & (
// !\A_SPW_TOP|rx_data|data_out~2_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [14]),
.dataf(!\A_SPW_TOP|rx_data|data_out~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~3 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~3 .lut_mask = 64'h00001001EFFEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N41
dffeas \A_SPW_TOP|rx_data|data_out[1] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~3_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [1]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[1] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N39
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[1] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [1] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [1] ) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[1] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[1] .lut_mask = 64'h5555000000000000;
defparam \u0|data_flag_rx|read_mux_out[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N41
dffeas \u0|data_flag_rx|readdata[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[1] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N40
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y18_N47
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout = (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1])) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q )))
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N11
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ) # (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]))) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q & (
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1] & (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout )) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [1]),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 .lut_mask = 64'h1010D0D01010D0D0;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N35
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N30
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[1] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [1] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|SPW|RX|timecode [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\A_SPW_TOP|SPW|RX|timecode [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[1] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[1] .lut_mask = 64'h00F000F000000000;
defparam \u0|timecode_rx|read_mux_out[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N32
dffeas \u0|timecode_rx|readdata[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[1] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N31
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q )) #
// (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 .lut_mask = 64'h2727272733333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [1] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~1 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y26_N47
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y26_N17
dffeas \u0|led_pio_test|data_out[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|led_pio_test|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|led_pio_test|data_out [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[1] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N54
cyclonev_lcell_comb \u0|led_pio_test|readdata[1] (
// Equation(s):
// \u0|led_pio_test|readdata [1] = ( \u0|led_pio_test|data_out [1] & ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(!\u0|led_pio_test|data_out [1]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|led_pio_test|readdata [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[1] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[1] .lut_mask = 64'h0000F0F000000000;
defparam \u0|led_pio_test|readdata[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N56
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|led_pio_test|readdata [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1] & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N8
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 .lut_mask = 64'h0A5F0A5F0F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout & ( (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout )) # (\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 .lut_mask = 64'h33F377F733F377F7;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X35_Y7_N0
cyclonev_lcell_comb \m_x|rx_got_time_code~0 (
// Equation(s):
// \m_x|rx_got_time_code~0_combout = ( \m_x|control [1] & ( (\m_x|last_is_data~q & (\m_x|control [0] & \m_x|control [2])) ) )
.dataa(!\m_x|last_is_data~q ),
.datab(!\m_x|control [0]),
.datac(!\m_x|control [2]),
.datad(gnd),
.datae(!\m_x|control [1]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_got_time_code~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_got_time_code~0 .extended_lut = "off";
defparam \m_x|rx_got_time_code~0 .lut_mask = 64'h0000010100000101;
defparam \m_x|rx_got_time_code~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X35_Y7_N2
dffeas \m_x|rx_got_time_code (
.clk(!\m_x|always3~0_combout ),
.d(\m_x|rx_got_time_code~0_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|rx_got_null~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|rx_got_time_code~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_time_code .is_wysiwyg = "true";
defparam \m_x|rx_got_time_code .power_up = "low";
// synopsys translate_on
// Location: FF_X33_Y7_N5
dffeas \m_x|info[1] (
.clk(\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|rx_got_time_code~q ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [1]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[1] .is_wysiwyg = "true";
defparam \m_x|info[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N15
cyclonev_lcell_comb \u0|data_info|read_mux_out[1] (
// Equation(s):
// \u0|data_info|read_mux_out [1] = ( \m_x|info [1] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[1] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[1] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[1] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N18
cyclonev_lcell_comb \u0|data_info|readdata[1]~feeder (
// Equation(s):
// \u0|data_info|readdata[1]~feeder_combout = ( \u0|data_info|read_mux_out [1] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|data_info|read_mux_out [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|readdata[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|readdata[1]~feeder .extended_lut = "off";
defparam \u0|data_info|readdata[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|data_info|readdata[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N20
dffeas \u0|data_info|readdata[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|readdata[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[1] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N47
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N6
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[1] (
// Equation(s):
// \u0|timecode_tx_data|readdata [1] = (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [1]))
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|timecode_tx_data|data_out [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[1] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[1] .lut_mask = 64'h00A000A000A000A0;
defparam \u0|timecode_tx_data|readdata[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y16_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y16_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 .lut_mask = 64'h0F330F330F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout = (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WDATA [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WDATA [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N43
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N0
cyclonev_lcell_comb \u0|clock_sel|always0~0 (
// Equation(s):
// \u0|clock_sel|always0~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|clock_sel|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|clock_sel|always0~0 .extended_lut = "off";
defparam \u0|clock_sel|always0~0 .lut_mask = 64'h2000200000000000;
defparam \u0|clock_sel|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N35
dffeas \u0|clock_sel|data_out[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|clock_sel|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|clock_sel|data_out [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|clock_sel|data_out[1] .is_wysiwyg = "true";
defparam \u0|clock_sel|data_out[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N18
cyclonev_lcell_comb \u0|clock_sel|readdata[1]~1 (
// Equation(s):
// \u0|clock_sel|readdata[1]~1_combout = (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (\u0|clock_sel|data_out [1] &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|clock_sel|data_out [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|clock_sel|readdata[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|clock_sel|readdata[1]~1 .extended_lut = "off";
defparam \u0|clock_sel|readdata[1]~1 .lut_mask = 64'h0A000A000A000A00;
defparam \u0|clock_sel|readdata[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N8
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|clock_sel|readdata[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y18_N59
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N28
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1] & ( ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1] & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q & ((!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 .lut_mask = 64'h3303330333F333F3;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout )) #
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout & \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N18
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[1]~1 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[1]~1_combout = ( \A_SPW_TOP|tx_data|counter [1] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_tx_fifo|read_mux_out[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[1]~1 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[1]~1 .lut_mask = 64'h0000000088888888;
defparam \u0|counter_tx_fifo|read_mux_out[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N19
dffeas \u0|counter_tx_fifo|readdata[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_tx_fifo|read_mux_out[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_tx_fifo|readdata [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[1] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y17_N14
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_tx_fifo|readdata [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y17_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N35
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1])))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [1]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 .lut_mask = 64'h1B001B000F000F00;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N12
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[1] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [1] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|write_data_fifo_tx|data_out [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\u0|write_data_fifo_tx|data_out [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[1] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[1] .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|write_data_fifo_tx|readdata[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N14
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N6
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[1]~1 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[1]~1_combout = ( \A_SPW_TOP|rx_data|counter [1] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_rx_fifo|read_mux_out[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[1]~1 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[1]~1 .lut_mask = 64'h00000000C0C0C0C0;
defparam \u0|counter_rx_fifo|read_mux_out[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N7
dffeas \u0|counter_rx_fifo|readdata[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_rx_fifo|read_mux_out[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_rx_fifo|readdata [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[1] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N2
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_rx_fifo|readdata [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N19
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F000F000FFF0FFF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N49
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 .lut_mask = 64'h22220A0A22222222;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N53
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N12
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[1]~1 (
// Equation(s):
// \u0|fsm_info|read_mux_out[1]~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datac(!\A_SPW_TOP|SPW|FSM|state_fsm.ready~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fsm_info|read_mux_out[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[1]~1 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[1]~1 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|fsm_info|read_mux_out[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N13
dffeas \u0|fsm_info|readdata[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fsm_info|read_mux_out[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fsm_info|readdata [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[1] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N50
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fsm_info|readdata [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h11111111DDDDDDDD;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N55
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// (((!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q &
// ((!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 .lut_mask = 64'h2202220222A222A2;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N17
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1])) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout )) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [1]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ),
.datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 .lut_mask = 64'h57FF57FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N50
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N56
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout )
// ) ) # ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( ((((\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1])) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [1]),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ),
.datag(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 .extended_lut = "on";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 .lut_mask = 64'h37FF37FFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [4] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [8] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [5] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [7] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [6] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [9]))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [5]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [7]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [6]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [9]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [4]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~0 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal21~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal21~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|mm_interconnect_0|router_001|Equal13~0_combout
// & (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal21~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal21~0 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router_001|Equal21~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N17
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[15] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[15] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[15] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 .lut_mask = 64'h000000000F050F05;
defparam \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout = ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout & ((!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout &
// (!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (((\u0|mm_interconnect_0|cmd_mux_015|src_payload [0] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))))) ) ) # ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &
// ((!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & (((\u0|mm_interconnect_0|cmd_mux_015|src_payload [0] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )))))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_015|src_payload [0] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),
.datag(!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 .extended_lut = "on";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 .lut_mask = 64'h0A0AA0A300030033;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y21_N2
dffeas \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout & \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout & ((!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 .lut_mask = 64'h0C0F0C0F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout = ( !\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y21_N32
dffeas \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]) # ((!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout &
// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [0]),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 .lut_mask = 64'h00000000CCFCCCFC;
defparam \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y21_N44
dffeas \u0|mm_interconnect_0|cmd_mux_015|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_015|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y21_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h03CF03CF03CF03CF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N10
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y21_N1
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N26
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 .lut_mask = 64'h5050505000000000;
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|rsp_demux_015|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y20_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y20_N2
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y20_N11
dffeas \u0|clock_sel|data_out[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|clock_sel|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|clock_sel|data_out [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|clock_sel|data_out[0] .is_wysiwyg = "true";
defparam \u0|clock_sel|data_out[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N21
cyclonev_lcell_comb \u0|clock_sel|readdata[0]~0 (
// Equation(s):
// \u0|clock_sel|readdata[0]~0_combout = (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|clock_sel|data_out [0]))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(!\u0|clock_sel|data_out [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|clock_sel|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|clock_sel|readdata[0]~0 .extended_lut = "off";
defparam \u0|clock_sel|readdata[0]~0 .lut_mask = 64'h00A000A000A000A0;
defparam \u0|clock_sel|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N31
dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|clock_sel|readdata[0]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]))) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ))
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h05F505F505F505F5;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N22
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0] & ( ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0] & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q & ((!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 .lut_mask = 64'h515151515D5D5D5D;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N20
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y21_N24
cyclonev_lcell_comb \u0|timecode_tx_enable|readdata[0]~0 (
// Equation(s):
// \u0|timecode_tx_enable|readdata[0]~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|timecode_tx_enable|data_out~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\u0|timecode_tx_enable|data_out~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_enable|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_enable|readdata[0]~0 .extended_lut = "off";
defparam \u0|timecode_tx_enable|readdata[0]~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|timecode_tx_enable|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y21_N23
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_tx_enable|readdata[0]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N50
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0] & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0] & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 .lut_mask = 64'h4545454575757575;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout & ( (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) #
// (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout & ( \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) )
// # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 .lut_mask = 64'h0000555533337777;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N21
cyclonev_lcell_comb \u0|link_disable|readdata[0]~0 (
// Equation(s):
// \u0|link_disable|readdata[0]~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|link_disable|data_out~q &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\u0|link_disable|data_out~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|link_disable|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|link_disable|readdata[0]~0 .extended_lut = "off";
defparam \u0|link_disable|readdata[0]~0 .lut_mask = 64'h5050505000000000;
defparam \u0|link_disable|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|link_disable|readdata[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y26_N26
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0])) #
// (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q )))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h4477447744774477;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFF0FFF0FFF0FFF0F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0] & (
// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0] & ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0] & ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre [0]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 .lut_mask = 64'h0F0F0F0F0303CFCF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N30
cyclonev_lcell_comb \u0|write_data_fifo_tx|readdata[0] (
// Equation(s):
// \u0|write_data_fifo_tx|readdata [0] = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|write_data_fifo_tx|data_out [0] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|write_data_fifo_tx|data_out [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_data_fifo_tx|readdata [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_data_fifo_tx|readdata[0] .extended_lut = "off";
defparam \u0|write_data_fifo_tx|readdata[0] .lut_mask = 64'h0F000F0000000000;
defparam \u0|write_data_fifo_tx|readdata[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y18_N32
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_data_fifo_tx|readdata [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y18_N35
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y22_N44
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & (
// ((\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout )) # (\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )))) # (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )))) # (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout &
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 .lut_mask = 64'h111111F1111F11FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N0
cyclonev_lcell_comb \u0|write_en_tx|readdata[0]~0 (
// Equation(s):
// \u0|write_en_tx|readdata[0]~0_combout = ( \u0|write_en_tx|data_out~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datae(gnd),
.dataf(!\u0|write_en_tx|data_out~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|write_en_tx|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|write_en_tx|readdata[0]~0 .extended_lut = "off";
defparam \u0|write_en_tx|readdata[0]~0 .lut_mask = 64'h00000000F000F000;
defparam \u0|write_en_tx|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N2
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|write_en_tx|readdata[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y24_N49
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q )))
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h5353535353535353;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFFFFFFFF55555555;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N10
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ))) #
// (\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0])) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 .lut_mask = 64'h0F550F550F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y16_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y16_N15
cyclonev_lcell_comb \u0|timecode_tx_data|readdata[0] (
// Equation(s):
// \u0|timecode_tx_data|readdata [0] = (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & \u0|timecode_tx_data|data_out [0]))
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(!\u0|timecode_tx_data|data_out [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_data|readdata [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_data|readdata[0] .extended_lut = "off";
defparam \u0|timecode_tx_data|readdata[0] .lut_mask = 64'h0088008800880088;
defparam \u0|timecode_tx_data|readdata[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y16_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_data|readdata [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y16_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y16_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 .lut_mask = 64'h0F0F03030F0FCFCF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout )) #
// (\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_008|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_008|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_008|src1_valid .lut_mask = 64'hF0F00000F0F00000;
defparam \u0|mm_interconnect_0|rsp_demux_008|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N30
cyclonev_lcell_comb \u0|counter_tx_fifo|read_mux_out[0]~0 (
// Equation(s):
// \u0|counter_tx_fifo|read_mux_out[0]~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\A_SPW_TOP|tx_data|counter [0] &
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\A_SPW_TOP|tx_data|counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_tx_fifo|read_mux_out[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_tx_fifo|read_mux_out[0]~0 .extended_lut = "off";
defparam \u0|counter_tx_fifo|read_mux_out[0]~0 .lut_mask = 64'h5050505000000000;
defparam \u0|counter_tx_fifo|read_mux_out[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N32
dffeas \u0|counter_tx_fifo|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_tx_fifo|read_mux_out[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_tx_fifo|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_tx_fifo|readdata[0] .is_wysiwyg = "true";
defparam \u0|counter_tx_fifo|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y17_N38
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_tx_fifo|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y17_N13
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0] ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N32
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] &
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0])))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 .lut_mask = 64'h04F704F700000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N44
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y28_N9
cyclonev_lcell_comb \u0|auto_start|readdata[0]~0 (
// Equation(s):
// \u0|auto_start|readdata[0]~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|auto_start|data_out~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\u0|auto_start|data_out~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|auto_start|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|auto_start|readdata[0]~0 .extended_lut = "off";
defparam \u0|auto_start|readdata[0]~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|auto_start|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y28_N11
dffeas \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|auto_start|readdata[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF5F5F5F5F5F5F5F5;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y26_N23
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0] & ( ((!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0] & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q & ((!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg [0]),
.datae(!\u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre [0]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 .lut_mask = 64'h0F030FCF0F030FCF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N3
cyclonev_lcell_comb \u0|counter_rx_fifo|read_mux_out[0]~0 (
// Equation(s):
// \u0|counter_rx_fifo|read_mux_out[0]~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( (\A_SPW_TOP|rx_data|counter [0] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(gnd),
.datab(!\A_SPW_TOP|rx_data|counter [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|counter_rx_fifo|read_mux_out[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|counter_rx_fifo|read_mux_out[0]~0 .extended_lut = "off";
defparam \u0|counter_rx_fifo|read_mux_out[0]~0 .lut_mask = 64'h3030303000000000;
defparam \u0|counter_rx_fifo|read_mux_out[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N4
dffeas \u0|counter_rx_fifo|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|counter_rx_fifo|read_mux_out[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|counter_rx_fifo|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|counter_rx_fifo|readdata[0] .is_wysiwyg = "true";
defparam \u0|counter_rx_fifo|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N56
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|counter_rx_fifo|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y16_N17
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h4444444477777777;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y16_N46
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y16_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0] & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q &
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre [0]),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 .lut_mask = 64'h0A000AAA0A0A0A0A;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y16_N45
cyclonev_lcell_comb \u0|fsm_info|read_mux_out[0]~0 (
// Equation(s):
// \u0|fsm_info|read_mux_out[0]~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q &
// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fsm_info|read_mux_out[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fsm_info|read_mux_out[0]~0 .extended_lut = "off";
defparam \u0|fsm_info|read_mux_out[0]~0 .lut_mask = 64'h5050505000000000;
defparam \u0|fsm_info|read_mux_out[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y16_N47
dffeas \u0|fsm_info|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fsm_info|read_mux_out[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fsm_info|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fsm_info|readdata[0] .is_wysiwyg = "true";
defparam \u0|fsm_info|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N23
dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fsm_info|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y18_N20
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y18_N58
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// (((!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & (!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout &
// (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 .lut_mask = 64'h00080008C4CCC4CC;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout &
// ((!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 .lut_mask = 64'hC8C8000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N5
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y33_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout & \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout )))) )
// ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout & \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h0050005088D888D8;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h000A000A050F050F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// ( (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'hF808F80808080808;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])
// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout
// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0022002211331133;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .lut_mask = 64'h00000000FA50FA50;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N56
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout & (
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ) #
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hCCEECCEEDDFFDDFF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y35_N1
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM((
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]
// ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h3131313120202020;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N19
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [0]))) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h05050030FFFF0030;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N43
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM((
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [1] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000000000C00;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00000000AFA0AFA0;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1] & (
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout &
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h10FF10FFF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y35_N49
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [2] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]
// ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h5055505550005000;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N31
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout
// ))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2])))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [2] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1010101FF0F0F0FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N37
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM((
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )))) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h0F050F050B010B01;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout
// )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ))
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000A111BAAAABBBB;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y35_N40
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y35_N52
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N54
cyclonev_lcell_comb \u0|fifo_full_rx_status|read_mux_out (
// Equation(s):
// \u0|fifo_full_rx_status|read_mux_out~combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \A_SPW_TOP|rx_data|f_full~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\A_SPW_TOP|rx_data|f_full~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fifo_full_rx_status|read_mux_out~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fifo_full_rx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_full_rx_status|read_mux_out .lut_mask = 64'h00F000F000000000;
defparam \u0|fifo_full_rx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N55
dffeas \u0|fifo_full_rx_status|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fifo_full_rx_status|read_mux_out~combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fifo_full_rx_status|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fifo_full_rx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_full_rx_status|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y35_N37
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fifo_full_rx_status|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h00FF00FF0F0F0F0F;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFFFFFFFF55555555;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre [0]),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 .lut_mask = 64'h111111BB131311BB;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N48
cyclonev_lcell_comb \u0|data_read_en_rx|readdata[0]~0 (
// Equation(s):
// \u0|data_read_en_rx|readdata[0]~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \u0|data_read_en_rx|data_out~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(!\u0|data_read_en_rx|data_out~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_read_en_rx|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_read_en_rx|readdata[0]~0 .extended_lut = "off";
defparam \u0|data_read_en_rx|readdata[0]~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|data_read_en_rx|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_read_en_rx|readdata[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y30_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFFFFFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N49
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 .lut_mask = 64'h03CF03CF00FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout
// & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000F0CCF0CC;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N14
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h4073407340404040;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [0])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h0F050F050A000A00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y35_N10
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hB380B38080808080;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h00000000550F550F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0A0F0A0F0A000A00;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout & (
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) )
// ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) )
// )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hDDCCDDCCDDFFDDFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout =
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [0] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000FC30FC30;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N13
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout
// )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N43
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14
// ))
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [1] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0100010000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h37003700FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10
// ))
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [2] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ))
// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ))
// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h37370000373700FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N35
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout &
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])))
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h05000500050F050F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y35_N55
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6
// ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ))))) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00AF00AF00A300A3;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N22
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]
// & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) ) # (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [3] & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ) )
// ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h000F1111FFFF1111;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y35_N59
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y35_N57
cyclonev_lcell_comb \u0|fifo_empty_rx_status|read_mux_out (
// Equation(s):
// \u0|fifo_empty_rx_status|read_mux_out~combout = ( !\A_SPW_TOP|rx_data|f_empty~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|rx_data|f_empty~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fifo_empty_rx_status|read_mux_out~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fifo_empty_rx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_empty_rx_status|read_mux_out .lut_mask = 64'hAA00AA0000000000;
defparam \u0|fifo_empty_rx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y35_N58
dffeas \u0|fifo_empty_rx_status|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fifo_empty_rx_status|read_mux_out~combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fifo_empty_rx_status|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fifo_empty_rx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_empty_rx_status|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder_combout = ( \u0|fifo_empty_rx_status|readdata [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|fifo_empty_rx_status|readdata [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N1
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y37_N26
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N8
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & (
// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) #
// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]
// & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre [0]),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 .lut_mask = 64'h000255570F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout &
// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000F5B1F5B1;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N23
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N17
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N47
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N44
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h085D085D08080808;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000035353535;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N22
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y35_N28
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000CACACACA;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N20
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]
// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [2])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout &
// (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hF088F08800880088;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0000000005AF05AF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N2
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hFF05FF05FFAFFFAF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N37
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM((
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]
// ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000FF0000000F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y35_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y35_N53
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout )) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000FA50FA50;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N19
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [0]))) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N55
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [1] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]
// ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0B0B0B0B08080808;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N10
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0100010000000000;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [1]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h04CC04CCFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N7
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [2] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]
// ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]
// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// ))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N25
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]
// ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]
// & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout )
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1111000FFFFF000F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y35_N55
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [3] ) + ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y35_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3])))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h5500550F7700770F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y35_N16
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X11_Y35_N58
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N33
cyclonev_lcell_comb \u0|fifo_full_tx_status|read_mux_out (
// Equation(s):
// \u0|fifo_full_tx_status|read_mux_out~combout = ( \A_SPW_TOP|tx_data|f_full~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|tx_data|f_full~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fifo_full_tx_status|read_mux_out~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fifo_full_tx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_full_tx_status|read_mux_out .lut_mask = 64'h00000000A0A0A0A0;
defparam \u0|fifo_full_tx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N35
dffeas \u0|fifo_full_tx_status|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fifo_full_tx_status|read_mux_out~combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fifo_full_tx_status|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fifo_full_tx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_full_tx_status|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y35_N43
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fifo_full_tx_status|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y36_N32
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0])) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y36_N38
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y36_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] &
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & (
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre [0]),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 .lut_mask = 64'h0505070705AF05AF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout &
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 .lut_mask = 64'h8AAA000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N3
cyclonev_lcell_comb \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder (
// Equation(s):
// \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder_combout = ( \A_SPW_TOP|SPW|RX|rx_data_flag [0] )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y12_N5
dffeas \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem_rtl_0_bypass [13]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y12_N32
dffeas \A_SPW_TOP|rx_data|mem~1 (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_data_flag [0]),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\A_SPW_TOP|rx_data|mem~13_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|mem~1_q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|mem~1 .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|mem~1 .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~0 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~0_combout = ( \A_SPW_TOP|rx_data|mem~1_q & ( \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ) ) # ( !\A_SPW_TOP|rx_data|mem~1_q & (
// \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout & ( \A_SPW_TOP|rx_data|mem~0_q ) ) ) # ( \A_SPW_TOP|rx_data|mem~1_q & ( !\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout & ( !\A_SPW_TOP|rx_data|mem~0_q ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~0_q ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\A_SPW_TOP|rx_data|mem~1_q ),
.dataf(!\A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~0 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~0 .lut_mask = 64'h0000AAAA5555FFFF;
defparam \A_SPW_TOP|rx_data|data_out~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y12_N36
cyclonev_lcell_comb \A_SPW_TOP|rx_data|data_out~1 (
// Equation(s):
// \A_SPW_TOP|rx_data|data_out~1_combout = ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [13] & ( \A_SPW_TOP|rx_data|data_out~0_combout ) ) # ( !\A_SPW_TOP|rx_data|mem_rtl_0_bypass [13] & ( \A_SPW_TOP|rx_data|data_out~0_combout & (
// (!\A_SPW_TOP|rx_data|mem~10_combout ) # ((!\A_SPW_TOP|rx_data|mem~11_combout ) # (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12] $ (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]))) ) ) ) # ( \A_SPW_TOP|rx_data|mem_rtl_0_bypass [13] & (
// !\A_SPW_TOP|rx_data|data_out~0_combout & ( (\A_SPW_TOP|rx_data|mem~10_combout & (\A_SPW_TOP|rx_data|mem~11_combout & (!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12] $ (\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11])))) ) ) )
.dataa(!\A_SPW_TOP|rx_data|mem~10_combout ),
.datab(!\A_SPW_TOP|rx_data|mem~11_combout ),
.datac(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [12]),
.datad(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [11]),
.datae(!\A_SPW_TOP|rx_data|mem_rtl_0_bypass [13]),
.dataf(!\A_SPW_TOP|rx_data|data_out~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|rx_data|data_out~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out~1 .extended_lut = "off";
defparam \A_SPW_TOP|rx_data|data_out~1 .lut_mask = 64'h00001001EFFEFFFF;
defparam \A_SPW_TOP|rx_data|data_out~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y12_N37
dffeas \A_SPW_TOP|rx_data|data_out[0] (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),
.d(\A_SPW_TOP|rx_data|data_out~1_combout ),
.asdata(vcc),
.clrn(!\A_SPW_TOP|tx_reset_n~0_combout ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\A_SPW_TOP|rx_data|always1~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|rx_data|data_out [0]),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|rx_data|data_out[0] .is_wysiwyg = "true";
defparam \A_SPW_TOP|rx_data|data_out[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y16_N45
cyclonev_lcell_comb \u0|data_flag_rx|read_mux_out[0] (
// Equation(s):
// \u0|data_flag_rx|read_mux_out [0] = ( !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( \A_SPW_TOP|rx_data|data_out [0] ) ) )
.dataa(!\A_SPW_TOP|rx_data|data_out [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_flag_rx|read_mux_out [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_flag_rx|read_mux_out[0] .extended_lut = "off";
defparam \u0|data_flag_rx|read_mux_out[0] .lut_mask = 64'h5555000000000000;
defparam \u0|data_flag_rx|read_mux_out[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y16_N47
dffeas \u0|data_flag_rx|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_flag_rx|read_mux_out [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_flag_rx|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_flag_rx|readdata[0] .is_wysiwyg = "true";
defparam \u0|data_flag_rx|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y16_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_flag_rx|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y18_N44
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0] &
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h505050505F5F5F5F;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y18_N7
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout = ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout &
// ((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ))) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout & (\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 .lut_mask = 64'h03CF03CF00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N3
cyclonev_lcell_comb \u0|link_start|readdata[0]~0 (
// Equation(s):
// \u0|link_start|readdata[0]~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\u0|link_start|data_out~q &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(!\u0|link_start|data_out~q ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|link_start|readdata[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|link_start|readdata[0]~0 .extended_lut = "off";
defparam \u0|link_start|readdata[0]~0 .lut_mask = 64'h3030303000000000;
defparam \u0|link_start|readdata[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N5
dffeas \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|link_start|readdata[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y33_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout & (
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFFFFFFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N26
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & ((\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ))) #
// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 .lut_mask = 64'h0F330F330F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0])
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 .lut_mask = 64'h0033003300330033;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N32
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y34_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X13_Y34_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]
// & ( (\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout )) )
// ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [1])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout &
// (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h10DC10DC10101010;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg
// [0]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000F0AAF0AA;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y34_N55
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (((!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hB380B38080808080;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])))
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0000000033553355;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N26
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0C0F0C0F0C000C00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N53
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0010001000000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) # ((\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hF0F5F0F5FFF5FFF5;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) + (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [0] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 .lut_mask = 64'h5555000055550000;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N35
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// (!\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout & ((!\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ) #
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h0F0A0F0A000A000A;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N22
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// ((((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout
// )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]))) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N38
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14
// ))
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [1] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA00000F0F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout & ( ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0AFF0AFF2AFF2AFF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N50
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10
// ))
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [2] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h0C0F0C0F0C000C00;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]))
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h0F5F00000F5F3333;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N52
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout = (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 .lut_mask = 64'h3030303030303030;
defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N56
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout
// & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])))) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout
// ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000F0DDF0DD;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y34_N19
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])))
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000033553355;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y34_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM((
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3] ) + ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6
// ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3])
// # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) ) ) ) # (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & (
// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]
// ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h3333000F7777000F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y34_N59
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N45
cyclonev_lcell_comb \u0|fifo_empty_tx_status|read_mux_out (
// Equation(s):
// \u0|fifo_empty_tx_status|read_mux_out~combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & ( !\A_SPW_TOP|tx_data|f_empty~q & (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\A_SPW_TOP|tx_data|f_empty~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|fifo_empty_tx_status|read_mux_out~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|fifo_empty_tx_status|read_mux_out .extended_lut = "off";
defparam \u0|fifo_empty_tx_status|read_mux_out .lut_mask = 64'hF0F0000000000000;
defparam \u0|fifo_empty_tx_status|read_mux_out .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y34_N46
dffeas \u0|fifo_empty_tx_status|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|fifo_empty_tx_status|read_mux_out~combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|fifo_empty_tx_status|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|fifo_empty_tx_status|readdata[0] .is_wysiwyg = "true";
defparam \u0|fifo_empty_tx_status|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y34_N44
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|fifo_empty_tx_status|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y34_N47
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0])) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h303F303F303F303F;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hF0FFF0FFF0FFF0FF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N20
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] &
// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q )) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 .lut_mask = 64'h5555555535353535;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|ready_tx_timecode~0 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout = ( \A_SPW_TOP|SPW|TX|global_counter_transfer [2] & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer [3] & (!\A_SPW_TOP|SPW|TX|global_counter_transfer [1] & \A_SPW_TOP|SPW|TX|global_counter_transfer [0])) ) )
.dataa(!\A_SPW_TOP|SPW|TX|global_counter_transfer [3]),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer [1]),
.datac(gnd),
.datad(!\A_SPW_TOP|SPW|TX|global_counter_transfer [0]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|global_counter_transfer [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode~0 .lut_mask = 64'h0000000000440044;
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y11_N33
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|ready_tx_timecode~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|ready_tx_timecode~1_combout = ( \A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (((!\A_SPW_TOP|SPW|TX|last_type~14_combout & \A_SPW_TOP|SPW|TX|ready_tx_timecode~q )) #
// (\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ))) ) ) # ( !\A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout & ( (\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout & (!\A_SPW_TOP|SPW|TX|last_type~14_combout & \A_SPW_TOP|SPW|TX|ready_tx_timecode~q )) )
// )
.dataa(!\A_SPW_TOP|SPW|TX|enable_time_code~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ),
.datac(!\A_SPW_TOP|SPW|TX|last_type~14_combout ),
.datad(!\A_SPW_TOP|SPW|TX|ready_tx_timecode~q ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|ready_tx_timecode~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode~1 .lut_mask = 64'h0030003011311131;
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N38
dffeas \A_SPW_TOP|SPW|TX|ready_tx_timecode (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|TX|ready_tx_timecode~1_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|ready_tx_timecode~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|ready_tx_timecode .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N23
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & ((!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00B800B800BB00BB;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N29
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y34_N1
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N59
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout = (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1])
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout = ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout & ((\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout )))) ) ) #
// ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h000A000AC0CAC0CA;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000003F303F3;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N22
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0] &
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ) #
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000FFCC00CC;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N25
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N53
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout & !\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout & !\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hD888D88850005000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0000000003CF03CF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N49
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hF0FFF0FFF3F3F3F3;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y36_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout = (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y36_N52
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [0] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) +
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N50
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout
// & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N25
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [0]))) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]))))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h03030050FFFF0050;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N43
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]
// ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14
// ))
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) +
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000F0F000003333;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &
// \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000000400040;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & ( \u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 .lut_mask = 64'h3333333300000000;
defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N20
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))
// ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h00F500F500A000A0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N56
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] & ( ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h0FCF0FCF4FCF4FCF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N17
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]
// ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10
// ))
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) +
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC00000F0F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h00000000F3C0F3C0;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N13
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [2])) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h00110F11FF11FF11;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N7
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [3] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6
// ))
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [3] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )
// # ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h0003CCCF4447CCCF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y34_N10
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y34_N4
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N6
cyclonev_lcell_comb \u0|timecode_tx_ready|read_mux_out (
// Equation(s):
// \u0|timecode_tx_ready|read_mux_out~combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( (\A_SPW_TOP|SPW|TX|ready_tx_timecode~q &
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|TX|ready_tx_timecode~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_tx_ready|read_mux_out~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_tx_ready|read_mux_out .extended_lut = "off";
defparam \u0|timecode_tx_ready|read_mux_out .lut_mask = 64'h0F000F0000000000;
defparam \u0|timecode_tx_ready|read_mux_out .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N8
dffeas \u0|timecode_tx_ready|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_tx_ready|read_mux_out~combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_tx_ready|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_tx_ready|readdata[0] .is_wysiwyg = "true";
defparam \u0|timecode_tx_ready|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y33_N44
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_tx_ready|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0])) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q )))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0C3F0C3F0C3F0C3F;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hCCFFCCFFCCFFCCFF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y33_N13
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y33_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & (
// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]))) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & (
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0] & (
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 .lut_mask = 64'h00040F0F33370F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout & (
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout )) # (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 .lut_mask = 64'hF7F700F700000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout & (
// \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y34_N52
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 .lut_mask = 64'h000000000000FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N20
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout & \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .lut_mask = 64'h0C0C0C0C00AA00AA;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0])))
// # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .lut_mask = 64'h00000000E2E2E2E2;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N40
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout & (
// \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 .lut_mask = 64'h5555555500000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [2]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .lut_mask = 64'hA0A0A0A0CCCC0000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .lut_mask = 64'h0000000011BB11BB;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N17
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout )) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .lut_mask = 64'hFFFFFFFF03F303F3;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout =
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .lut_mask = 64'hFF00FF00FF00FF00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly
// [0] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 = CARRY(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0] ) +
// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0] ) + ( !VCC ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.cout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout = (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout &
// \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 .lut_mask = 64'h00AA00AA00AA00AA;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N59
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0] = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [0] & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout )) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .lut_mask = 64'h00F300F300C000C0;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N25
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout = (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( ((((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]
// & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0])))
// ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [0] &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [0]),
.datag(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .lut_mask = 64'h000F1010FFFF1010;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N55
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [1] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ))
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 = CARRY(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]
// ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14
// ))
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.cout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .lut_mask = 64'h0000AAAA000000FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1] = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1])) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout &
// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))
// ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .lut_mask = 64'h0F030F030C000C00;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[1] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N23
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [1]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & !\u0|hps_0|fpga_interfaces|h2f_ARSIZE
// [1]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .lut_mask = 64'h0000000010001000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [1]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .lut_mask = 64'h04CC04CCFFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N31
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [2] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 = CARRY(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2] )
// + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ))
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [2]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.cout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .lut_mask = 64'h0000CCCC000000FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2] = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout
// & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout &
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2])) )
// ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout & (
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [2]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .lut_mask = 64'h5511551144004400;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[2] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N29
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [2]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [2] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|hps_0|fpga_interfaces|h2f_ARADDR [2])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2] & ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg
// [2] & ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2] &
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [2]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [2]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [2]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .lut_mask = 64'h1010F0F0101FF0FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N16
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X10_Y34_N43
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout
// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]))) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .lut_mask = 64'h0000000011DD11DD;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N38
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout = SUM(( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg
// [3] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3] ) + ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6
// ))
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly [3]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg [3]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y34_N32
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3] = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg
// [3])))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]) #
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .lut_mask = 64'h00000000E2F3E2F3;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr[3] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N19
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr [3]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] ) )
// # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]
// & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [3]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg [3]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [3]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .lut_mask = 64'h03030055FFFF0055;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X10_Y34_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout = (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y34_N13
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y14_N27
cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|rx_tick_out~0 (
// Equation(s):
// \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout = ( \A_SPW_TOP|SPW|RX|ready_data_p_r~q & ( \A_SPW_TOP|SPW|RX|rx_tick_out~q ) ) # ( !\A_SPW_TOP|SPW|RX|ready_data_p_r~q & ( ((!\A_SPW_TOP|SPW|RX|last_is_data~q & (!\A_SPW_TOP|SPW|RX|last_is_control~q &
// \A_SPW_TOP|SPW|RX|rx_tick_out~q ))) # (\A_SPW_TOP|SPW|RX|last_is_timec~q ) ) )
.dataa(!\A_SPW_TOP|SPW|RX|last_is_timec~q ),
.datab(!\A_SPW_TOP|SPW|RX|last_is_data~q ),
.datac(!\A_SPW_TOP|SPW|RX|last_is_control~q ),
.datad(!\A_SPW_TOP|SPW|RX|rx_tick_out~q ),
.datae(!\A_SPW_TOP|SPW|RX|ready_data_p_r~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~0 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~0 .lut_mask = 64'h55D500FF55D500FF;
defparam \A_SPW_TOP|SPW|RX|rx_tick_out~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y14_N32
dffeas \A_SPW_TOP|SPW|RX|rx_tick_out (
.clk(\A_SPW_TOP|SPW|RX|always3~0_combout ),
.d(gnd),
.asdata(\A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ),
.clrn(\A_SPW_TOP|SPW|FSM|rx_resetn~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(!\A_SPW_TOP|SPW|RX|ready_control_p_r~q ),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|RX|rx_tick_out~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|RX|rx_tick_out .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|RX|rx_tick_out .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y34_N48
cyclonev_lcell_comb \u0|timecode_ready_rx|read_mux_out (
// Equation(s):
// \u0|timecode_ready_rx|read_mux_out~combout = ( \A_SPW_TOP|SPW|RX|rx_tick_out~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|RX|rx_tick_out~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_ready_rx|read_mux_out~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_ready_rx|read_mux_out .extended_lut = "off";
defparam \u0|timecode_ready_rx|read_mux_out .lut_mask = 64'h00000000CC00CC00;
defparam \u0|timecode_ready_rx|read_mux_out .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y34_N49
dffeas \u0|timecode_ready_rx|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_ready_rx|read_mux_out~combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_ready_rx|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_ready_rx|readdata[0] .is_wysiwyg = "true";
defparam \u0|timecode_ready_rx|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y34_N8
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_ready_rx|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y34_N11
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y34_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0] &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0F000FFF0F000FFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout = (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hAFAFAFAFAFAFAFAF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N55
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q &
// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 .lut_mask = 64'h111311111113BBBB;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [0] & ( \u0|mm_interconnect_0|cmd_mux|saved_grant [0] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~0 .lut_mask = 64'h0000000033333333;
defparam \u0|mm_interconnect_0|cmd_mux|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y26_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X22_Y26_N50
dffeas \u0|led_pio_test|data_out[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|led_pio_test|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|led_pio_test|data_out [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|led_pio_test|data_out[0] .is_wysiwyg = "true";
defparam \u0|led_pio_test|data_out[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N21
cyclonev_lcell_comb \u0|led_pio_test|readdata[0] (
// Equation(s):
// \u0|led_pio_test|readdata [0] = ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \u0|led_pio_test|data_out [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|led_pio_test|data_out [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|led_pio_test|readdata [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|led_pio_test|readdata[0] .extended_lut = "off";
defparam \u0|led_pio_test|readdata[0] .lut_mask = 64'h0F0F000000000000;
defparam \u0|led_pio_test|readdata[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y26_N23
dffeas \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|led_pio_test|readdata [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y26_N20
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1] &
// \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0C0C0C0C3F3F3F3F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N52
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0] & ( ((\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0] &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q & ((!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 .lut_mask = 64'h00AF00AF50FF50FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N29
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y16_N21
cyclonev_lcell_comb \u0|timecode_rx|read_mux_out[0] (
// Equation(s):
// \u0|timecode_rx|read_mux_out [0] = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & (
// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & ( \A_SPW_TOP|SPW|RX|timecode [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\A_SPW_TOP|SPW|RX|timecode [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|timecode_rx|read_mux_out [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|timecode_rx|read_mux_out[0] .extended_lut = "off";
defparam \u0|timecode_rx|read_mux_out[0] .lut_mask = 64'h0F0F000000000000;
defparam \u0|timecode_rx|read_mux_out[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y16_N23
dffeas \u0|timecode_rx|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|timecode_rx|read_mux_out [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|timecode_rx|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|timecode_rx|readdata[0] .is_wysiwyg = "true";
defparam \u0|timecode_rx|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X14_Y16_N41
dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|timecode_rx|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]))) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ))
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h1D1D1D1D1D1D1D1D;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y18_N58
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y18_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0] & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0] & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 .lut_mask = 64'h515151515D5D5D5D;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y26_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout &
// (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout & (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout & (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout & (((!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 .lut_mask = 64'hCC4C0000CC4CCC4C;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N27
cyclonev_lcell_comb \m_x|rx_got_fct~0 (
// Equation(s):
// \m_x|rx_got_fct~0_combout = ( \m_x|always10~0_combout & ( \m_x|last_is_data~q & ( (!\m_x|control_l_r [0]) # ((!\m_x|control_l_r [1]) # (!\m_x|control_l_r [2])) ) ) ) # ( \m_x|always10~0_combout & ( !\m_x|last_is_data~q & ( (!\m_x|control_l_r [0]) #
// ((!\m_x|control_l_r [1]) # (!\m_x|control_l_r [2])) ) ) ) # ( !\m_x|always10~0_combout & ( !\m_x|last_is_data~q & ( \m_x|rx_got_fct~q ) ) )
.dataa(!\m_x|rx_got_fct~q ),
.datab(!\m_x|control_l_r [0]),
.datac(!\m_x|control_l_r [1]),
.datad(!\m_x|control_l_r [2]),
.datae(!\m_x|always10~0_combout ),
.dataf(!\m_x|last_is_data~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|rx_got_fct~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|rx_got_fct~0 .extended_lut = "off";
defparam \m_x|rx_got_fct~0 .lut_mask = 64'h5555FFFC0000FFFC;
defparam \m_x|rx_got_fct~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N26
dffeas \m_x|rx_got_fct (
.clk(!\m_x|always3~0_combout ),
.d(gnd),
.asdata(\m_x|rx_got_fct~0_combout ),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|rx_got_fct~q ),
.prn(vcc));
// synopsys translate_off
defparam \m_x|rx_got_fct .is_wysiwyg = "true";
defparam \m_x|rx_got_fct .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X33_Y7_N0
cyclonev_lcell_comb \m_x|info[0]~feeder (
// Equation(s):
// \m_x|info[0]~feeder_combout = ( \m_x|rx_got_fct~q )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|rx_got_fct~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\m_x|info[0]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \m_x|info[0]~feeder .extended_lut = "off";
defparam \m_x|info[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \m_x|info[0]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X33_Y7_N1
dffeas \m_x|info[0] (
.clk(\m_x|always3~0_combout ),
.d(\m_x|info[0]~feeder_combout ),
.asdata(vcc),
.clrn(!\db_system_spwulight_b|aux_pb~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\m_x|data_l_r[7]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\m_x|info [0]),
.prn(vcc));
// synopsys translate_off
defparam \m_x|info[0] .is_wysiwyg = "true";
defparam \m_x|info[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y10_N51
cyclonev_lcell_comb \u0|data_info|read_mux_out[0] (
// Equation(s):
// \u0|data_info|read_mux_out [0] = ( \m_x|info [0] & ( (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] &
// !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),
.datab(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\m_x|info [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|data_info|read_mux_out [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|data_info|read_mux_out[0] .extended_lut = "off";
defparam \u0|data_info|read_mux_out[0] .lut_mask = 64'h0000000088888888;
defparam \u0|data_info|read_mux_out[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y10_N53
dffeas \u0|data_info|readdata[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|data_info|read_mux_out [0]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|data_info|readdata [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|data_info|readdata[0] .is_wysiwyg = "true";
defparam \u0|data_info|readdata[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N44
dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|data_info|readdata [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y18_N23
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0])) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q )))
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y18_N26
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0] ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 .lut_mask = 64'h555555550F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout &
// (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout &
// ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout & \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 .lut_mask = 64'h0000005000000040;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout & ( ((\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ) #
// (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout )) # (\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ) )
// # ( \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout )
// )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 .lut_mask = 64'hFFFFFFFFFFFF7F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout = (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ))) #
// (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ))
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 .lut_mask = 64'h05AF05AF05AF05AF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y29_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[18] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[18] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[18] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [18] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [18]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [18]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src7_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|router|Equal7~6_combout & \u0|mm_interconnect_0|router|Equal13~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal13~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~1 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout &
// !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout &
// !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ) )
// ) # ( !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]) ) )
// )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [0]),
.datae(!\u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 .lut_mask = 64'h5500555555005500;
defparam \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y32_N38
dffeas \u0|mm_interconnect_0|cmd_mux_007|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_007|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [33] = ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [1])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .lut_mask = 64'h3737373737373737;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y32_N35
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 .lut_mask = 64'h8080800000000000;
defparam \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// !\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000F000F000;
defparam \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout & ( (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q &
// ((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout & (
// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout & (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]) #
// (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1])))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h000D000D00770077;
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N8
dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y32_N53
dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] &
// (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $ (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .lut_mask = 64'h0022008200220022;
defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout & (
// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout & ((\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h004C004C4C4C4C4C;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y32_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout &
// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0])) ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout &
// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout &
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]))))) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y32_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y29_N59
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_007|src_data [116] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11])) # (\u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [11]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y30_N59
dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 (
// Equation(s):
// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y29_N40
dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~56 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout = ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & (
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 .lut_mask = 64'h00000F0F33333F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~55 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~59 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~58 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116]~57 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[116] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [116] = ( \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout & ( \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout & (
// !\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [116]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116] .lut_mask = 64'h7F7FFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[116] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal16~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal16~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [17]) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal16~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal16~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal16~0 .lut_mask = 64'h0000000000CC00CC;
defparam \u0|mm_interconnect_0|router_001|Equal16~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal16~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal16~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~2_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|mm_interconnect_0|router_001|Equal1~1_combout &
// (\u0|mm_interconnect_0|router_001|Equal16~0_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal16~0_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal16~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal16~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal16~1 .lut_mask = 64'h0000000000020002;
defparam \u0|mm_interconnect_0|router_001|Equal16~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y31_N5
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[10] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router_001|Equal16~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[10] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~2_combout & ( (\u0|mm_interconnect_0|router_001|Equal16~0_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal16~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 .lut_mask = 64'h0000000005050505;
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10])))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [10]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 .lut_mask = 64'h0000000000003100;
defparam \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1] & (
// (\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout & (!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0] & ((!\u0|mm_interconnect_0|router|Equal16~0_combout ) # (!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal16~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 .lut_mask = 64'h5040504055555555;
defparam \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y25_N8
dffeas \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y22_N53
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] &
// ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 .lut_mask = 64'h000000000F0FFFFF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h040C040C44CC44CC;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout
// & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0])) ) ) # (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout &
// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]))))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h049D049D05AF05AF;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N2
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h00000000AA00AA00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ))) )
// ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q &
// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0 .lut_mask = 64'h0121012103330333;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y22_N26
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y22_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout & (
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y22_N20
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y22_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0] &
// ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout &
// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),
.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .lut_mask = 64'h0000200000008AAA;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout
// ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y22_N50
dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y22_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] &
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .lut_mask = 64'hA0A0A0A0A000A000;
defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q & ( ((\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q )) # (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q & (
// (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~52 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q &
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~51 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q & (
// (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q & (
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 .lut_mask = 64'h000033330F0F3F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~54 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q & (
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~50 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115]~53 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[115] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [115] = ( \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout & ( \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout & (
// !\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [115]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115] .lut_mask = 64'h77FFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[115] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_008|src_data [114] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) # (\u0|hps_0|fpga_interfaces|h2f_ARID [9]) ) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [9] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [9] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (
// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [9]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [9]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[114] .lut_mask = 64'h00000F0F55555F5F;
defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y29_N43
dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [114]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 (
// Equation(s):
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout = (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [114]))) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ))
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [114]),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 .lut_mask = 64'h0F550F550F550F55;
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y27_N17
dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y26_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) # (
// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q &
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q & (
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 .lut_mask = 64'h111111111111FFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~46 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q &
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout )) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~49 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q &
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~45 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~48 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q &
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q & \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114]~47 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[114] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [114] = ( \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [114]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[114] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [113] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &
// \u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWID [8] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [8]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [8]),
.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [8]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[113] .lut_mask = 64'h003300330033FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N25
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [113]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [113]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 .lut_mask = 64'h05050505F5F5F5F5;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N37
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q & (
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~40 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q &
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~41 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q &
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~44 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~43 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q &
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q & \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113]~42 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[113] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [113] = ( \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [113]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[113] .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & ( \u0|mm_interconnect_0|router_001|Equal17~1_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & ( \u0|mm_interconnect_0|router_001|Equal17~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal17~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .lut_mask = 64'h0000000033003333;
defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout = !\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y26_N29
dffeas \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_011|src_payload [0] &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) )
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_011|src_payload [0] &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) )
// ) ) # ( \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_011|src_payload [0] &
// ((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) )
// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 .lut_mask = 64'hAAAA030F030F030F;
defparam \u0|mm_interconnect_0|cmd_mux_011|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ) # (\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 .lut_mask = 64'h0000000033FF33FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y26_N8
dffeas \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y26_N59
dffeas \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ) #
// (!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]
// ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 .lut_mask = 64'h00000000F0F0FCFC;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y26_N44
dffeas \u0|mm_interconnect_0|cmd_mux_011|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &
// ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y24_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h4474447447774777;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0A0A0A0AFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y24_N5
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y24_N32
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout &
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q &
// (((\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ))) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout &
// ((\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout & (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1])))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0 .lut_mask = 64'h0123012311131113;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N41
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0000000033CC33CC;
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y24_N26
dffeas \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q )) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] &
// (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q )) ) ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] &
// \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q )) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 .lut_mask = 64'h0028002200220022;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ))) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout & (
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout & ((\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h004C004C4C4C4C4C;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ) ) # ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout & ( ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1])) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0000DFDFFFFFFFFF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N44
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 .lut_mask = 64'h0333033333333333;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ) #
// (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FEAAFEAA;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout &
// ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout & ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout &
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout & (((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h331133110F270F27;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N53
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y24_N20
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y24_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|src_data [112] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( \u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (
// (\u0|hps_0|fpga_interfaces|h2f_AWID [7] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [7] &
// \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARID [7] & ( !\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [7] & \u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]) )
// ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWID [7]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [0]),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARID [7]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[112] .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_011|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y24_N58
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_011|src_data [112]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [112]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y24_N14
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q & ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q & (
// !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 .lut_mask = 64'h030303030303FFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~38 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q &
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q & \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~37 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q & (
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q & (
// !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 .lut_mask = 64'h0000333300FF33FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~39 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q &
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ),
.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~36 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q & ( ((\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q & (
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112]~35 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[112] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [112] = ( \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [112]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[112] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout & (
// \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .lut_mask = 64'h0F0F0F0F55555555;
defparam \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout )))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0FBF0FBF0FFF0FFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N32
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0] &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .lut_mask = 64'hF0C0F0C000000000;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q & ( ((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q )) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q & (
// (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~34 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q &
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q & (
// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 .lut_mask = 64'h0505373705053737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~31 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q & \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q &
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~32 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~33 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q & \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q &
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111]~30 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[111] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [111] = ( \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout & ( \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout & (
// !\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [111]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111] .lut_mask = 64'h5FFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[111] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y33_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [2] $ (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & (
// \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 .lut_mask = 64'h0F0F0F0F0FF00FF0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .lut_mask = 64'h7575757530303030;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [2])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h50A050A05FAF5FAF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y29_N50
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout )))
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]
// $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h44BB44BB0F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N14
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hF30CF30CFF00FF00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]
// & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) #
// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hFF03FF5700030057;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h00C000C000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout )) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .lut_mask = 64'h03CF03CFCF03CF03;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N5
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y29_N2
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .lut_mask = 64'h11DD11DDD11DD11D;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )
// ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0111FFFF0111BBBB;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y30_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q
// & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h00000000FAF0FAF0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0404550500000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [88] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .lut_mask = 64'h1414141400000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [32] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [34] = ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [2])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .lut_mask = 64'h3737373737373737;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .lut_mask = 64'h8080808000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .lut_mask = 64'h30303030B0B0B0B0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &
// ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// ) # ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout
// & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h888C888CCC8CCC8C;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout &
// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2000FFFF0000FFFF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y29_N32
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0F00F1F10000F1F1;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & ( !\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (
// (\u0|mm_interconnect_0|cmd_mux_004|src_payload [0] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .lut_mask = 64'h11331133F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y33_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y33_N23
dffeas \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ) # ((!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ) # (!\u0|mm_interconnect_0|router|Equal7~8_combout )))) ) ) # (
// !\u0|mm_interconnect_0|router|Equal7~6_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~8_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 .lut_mask = 64'hCCCCCCCCCCC8CCC8;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (
// (!\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q & !\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & ( (!\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q &
// !\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & ( (!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout & \u0|mm_interconnect_0|cmd_mux_004|src_payload [0]) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & ( (!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout
// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|cmd_mux_004|src_payload [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 .lut_mask = 64'h000C00CC88888888;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y30_N2
dffeas \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y30_N58
dffeas \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src4_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & \u0|mm_interconnect_0|router|Equal7~8_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~8_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~1 .lut_mask = 64'h0000000000030003;
defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]) # ((!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout &
// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 .lut_mask = 64'h00000000AAFAAAFA;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y30_N32
dffeas \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [110] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [5] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [5]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [5]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[110] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N16
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [110]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[110] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [110]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N43
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q & (
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~25 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y29_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~26 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q &
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout )) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q & \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~28 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q )) # (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q & (
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110]~27 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[110] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [110] = ( \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout & ( \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout & (
// !\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [110]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110] .lut_mask = 64'h5FFFFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[110] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y30_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]))) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .lut_mask = 64'h8800800000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0A0A0A0A00000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q
// & (((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]))))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 .lut_mask = 64'h1015101505150515;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter
// [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout
// & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000F0FF0F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y28_N59
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y30_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0008CCCC0080CCCC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0F0F0F0F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y30_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00000000FAF0FAF0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1])))) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h3300330033103310;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000001000100;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h333F333F00000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (
// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout )) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h0FAF0FAF3FBF3FBF;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h0FF30FF30CF00CF0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N41
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout = (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]) # (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]
// & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2]))))) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .lut_mask = 64'h00B8FF740030FFFC;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y30_N2
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y30_N26
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q & (
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0404040437373737;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y30_N56
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h00000000FFFFF0A0;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y30_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout &
// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]))))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0])) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00F500F5313B313B;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y30_N8
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|src_data [109] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [4] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [4]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [4]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[109] .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N13
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [109]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[109] .power_up = "low";
// synopsys translate_on
// Location: FF_X15_Y29_N53
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q )))
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [109]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y29_N31
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q & (
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~20 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q & ( ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q &
// \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q & (
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q & \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q &
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~24 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~23 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout = ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout &
// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & (
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 .lut_mask = 64'h005500550F5F0F5F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109]~22 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[109] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [109] = ( \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [109]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[109] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~2_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [15] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [13] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [13]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [15]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~2 .lut_mask = 64'hFF00FF0000000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout = ( \u0|mm_interconnect_0|router_001|Equal7~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1] & (
// (\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout & (!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 .lut_mask = 64'h3000300033333333;
defparam \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y30_N23
dffeas \u0|mm_interconnect_0|cmd_mux_004|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y30_N1
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F33333333;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N17
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y30_N23
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q )))
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N49
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y30_N29
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q )))
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h505F505F505F505F;
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y30_N11
dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 .lut_mask = 64'h00CC00CC00000000;
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout = ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 .lut_mask = 64'h0000FFFF00000000;
defparam \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q & ( ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout &
// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q & (
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 .lut_mask = 64'h0505050537373737;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~15 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q & \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q &
// \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 .lut_mask = 64'h111111111F1F1F1F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout = ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q
// )) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~18 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q &
// \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout )) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q & \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~19 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108]~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[108] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [108] = ( \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [108]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[108] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[103]~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[103]~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout
// & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) ) ) ) # (
// \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])))) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// !\u0|mm_interconnect_0|router_001|Equal2~1_combout ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_data[103]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[103]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[103]~0 .lut_mask = 64'hFFFFA44ECC038C4E;
defparam \u0|mm_interconnect_0|router_001|src_data[103]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N56
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|src_data[103]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[101]~3 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[101]~3_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]) # (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))))) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) ) ) ) # (
// !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (((\u0|hps_0|fpga_interfaces|h2f_ARADDR
// [18] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &
// ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_data[101]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[101]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[101]~3 .lut_mask = 64'h00002E030FCC2ECB;
defparam \u0|mm_interconnect_0|router_001|src_data[101]~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N25
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|src_data[101]~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[104]~4 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[104]~4_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .lut_mask = 64'h0000119100C011D1;
defparam \u0|mm_interconnect_0|router_001|src_data[104]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N7
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout = ( \u0|mm_interconnect_0|router_001|src_data[104]~4_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4] &
// (!\u0|mm_interconnect_0|router_001|src_data[101]~3_combout $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[104]~4_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4] & (!\u0|mm_interconnect_0|router_001|src_data[101]~3_combout $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|src_data[101]~3_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|src_data[104]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .lut_mask = 64'hA500A50000A500A5;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[102]~2 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[102]~2_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] $ (((\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]
// & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & (
// !\u0|mm_interconnect_0|router_001|Equal2~1_combout ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_data[102]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[102]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[102]~2 .lut_mask = 64'hFFFFBA72F003B042;
defparam \u0|mm_interconnect_0|router_001|src_data[102]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N31
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|src_data[102]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[100]~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|src_data[100]~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR
// [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( \u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR
// [17] & ((\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~3_combout &
// ( !\u0|mm_interconnect_0|router_001|Equal2~1_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] $ (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])))) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] $ (((\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .lut_mask = 64'h000023583CFC21D8;
defparam \u0|mm_interconnect_0|router_001|src_data[100]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y31_N13
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout = ( \u0|mm_interconnect_0|router_001|src_data[100]~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0] &
// (!\u0|mm_interconnect_0|router_001|src_data[102]~2_combout $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]))) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[100]~1_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0] & (!\u0|mm_interconnect_0|router_001|src_data[102]~2_combout $ (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|router_001|src_data[102]~2_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [2]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|src_data[100]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .lut_mask = 64'hC300C30000C300C3;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout = ( \u0|mm_interconnect_0|router_001|src_data[103]~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout & (
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[103]~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout & (
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout )))) ) ) ) # ( \u0|mm_interconnect_0|router_001|src_data[103]~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout & (
// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) ) # ( !\u0|mm_interconnect_0|router_001|src_data[103]~0_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(!\u0|mm_interconnect_0|router_001|src_data[103]~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .lut_mask = 64'h3300330033023301;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] &
// \u0|mm_interconnect_0|router_001|Equal16~1_combout ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1] &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & \u0|mm_interconnect_0|router_001|Equal16~1_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal16~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 .lut_mask = 64'h0003000300330033;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout = ( \u0|mm_interconnect_0|router_001|Equal18~0_combout & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal13~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|router_001|Equal4~0_combout &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|router_001|Equal4~0_combout &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|router_001|Equal4~0_combout &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] & (\u0|mm_interconnect_0|router_001|Equal4~0_combout &
// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|router_001|Equal4~0_combout ),
.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 .lut_mask = 64'h010101FF01FF01FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout
// & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 .lut_mask = 64'h00770077007F00FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( \u0|mm_interconnect_0|router_001|Equal17~1_combout & (
// ((\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout & \u0|mm_interconnect_0|router_001|Equal10~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]) ) ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( \u0|mm_interconnect_0|router_001|Equal17~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] &
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout & ((\u0|mm_interconnect_0|router_001|Equal10~0_combout )))) # (\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1] & (((\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout &
// \u0|mm_interconnect_0|router_001|Equal10~0_combout )) # (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( !\u0|mm_interconnect_0|router_001|Equal17~1_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout &
// \u0|mm_interconnect_0|router_001|Equal10~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( !\u0|mm_interconnect_0|router_001|Equal17~1_combout & (
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout & \u0|mm_interconnect_0|router_001|Equal10~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal10~0_combout ),
.datae(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal17~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 .lut_mask = 64'h0033003305375577;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout = ( \u0|mm_interconnect_0|router_001|Equal19~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal19~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] &
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 .lut_mask = 64'h1133133313331333;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout = ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & ( \u0|mm_interconnect_0|router_001|Equal12~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|router_001|Equal21~0_combout & ( \u0|mm_interconnect_0|router_001|Equal12~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & (
// !\u0|mm_interconnect_0|router_001|Equal12~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal12~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 .lut_mask = 64'h0000033355555777;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h7000700077007700;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( \u0|mm_interconnect_0|router_001|Equal6~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 .lut_mask = 64'h00000000000055FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout = ( !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout & ( (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout &
// (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout & (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout & !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout = ( \u0|mm_interconnect_0|router_001|Equal14~1_combout & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] &
// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datae(!\u0|mm_interconnect_0|router_001|Equal14~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 .lut_mask = 64'h0000000000000002;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout = ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) # (
// !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & \u0|mm_interconnect_0|router_001|Equal8~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & \u0|mm_interconnect_0|router_001|Equal8~0_combout ))) #
// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout & (
// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &
// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & \u0|mm_interconnect_0|router_001|Equal8~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal8~0_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ),
.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 .lut_mask = 64'h040404FF0404FFFF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout = ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])))) #
// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|router_001|Equal1~4_combout & (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datab(!\u0|mm_interconnect_0|cmd_mux_003|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 .lut_mask = 64'h0000000A0000111B;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout &
// ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 .lut_mask = 64'h0000000000000F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout = ( \u0|mm_interconnect_0|router_001|Equal13~1_combout & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout & (
// (((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout )) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) #
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout & (
// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) #
// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &
// \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 .lut_mask = 64'h000011110FFF1FFF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal7~1_combout & \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y32_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|router_001|Equal11~0_combout )) #
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ((\u0|mm_interconnect_0|router_001|Equal11~0_combout )))) #
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|router_001|Equal11~0_combout )) #
// (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) ) ) # (
// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal11~0_combout ),
.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 .lut_mask = 64'h05050F0F05370F3F;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] &
// \u0|mm_interconnect_0|router_001|Equal9~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|router_001|Equal9~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 .lut_mask = 64'h00000000000F000F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// (\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] &
// (!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 .lut_mask = 64'h0404040404050405;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout = ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout & ( (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout &
// (!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout & (!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout & !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout & ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout & (
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout $ (((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ) #
// ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout & \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout & (
// !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 .lut_mask = 64'h6666666666566666;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y31_N23
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] $
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] $ (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0 .lut_mask = 64'h0FF00FF0F00FF00F;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y31_N8
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout = ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ) ) # (
// !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout & ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ) #
// ((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ) # (\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted .lut_mask = 64'h3233323333333333;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout & (
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1] &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count
// [0]) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [1]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 .lut_mask = 64'h00FB00FB80FF80FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y31_N32
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (\u0|mm_interconnect_0|router_001|Equal15~0_combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [9]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 .lut_mask = 64'h0000000044554455;
defparam \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1] & (
// (\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout & (!\u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 .lut_mask = 64'h5000500055555555;
defparam \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y30_N26
dffeas \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h88888888AAAAAAAA;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y27_N38
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q &
// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 .lut_mask = 64'h005A005A00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used
// [1] & \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 .lut_mask = 64'h00C000C0F0F0F0F0;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h0055005500FF00FF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) )
// ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) #
// ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & (
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// )) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0005FFDD0055FFDD;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0F080F0800000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout &
// ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( ((!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0] &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h000000003B3B0A0A;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hBBBBAFAF00000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y28_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F000F00FFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y28_N59
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout &
// !\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h2200220022002200;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q &
// (((\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ))) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout &
// ((\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ))) # (\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout & (\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1])))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h0511051101550155;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout = ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N35
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] $
// (!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y27_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout & ( \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout & (
// \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] &
// \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout & (
// !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1] &
// \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout & (
// !\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .lut_mask = 64'h00AA08AA08AA00AA;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (
// \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0F0F0F0F;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000300030;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout )) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'hC000000000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// ) # ((!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00AA00AA00AE00AE;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout
// & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h5555555540404040;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )
// # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h5050505070707070;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout )) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h55FF00FF5FFF0FFF;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N56
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &
// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h10FC10FC00CC00CC;
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y27_N50
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";
// synopsys translate_on
// Location: FF_X23_Y27_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h202F202F707F707F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N8
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ) #
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000CC0CCC0C;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N23
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q &
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q $ (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ))))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q $ (((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ))))) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D8728D27;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N2
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5AF0F05A5AF0F0;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q
// )) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout &
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q $ (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q )))) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout &
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q & (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q $
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4515055540100050;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N20
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h6C6CCCCC6C6CCCCC;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q &
// !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout &
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ) #
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3330333000300030;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N41
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout & (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout
// & (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000202011003120;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N49
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & ((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout & (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0F0F0F0F050F050F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout
// & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )))
// ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )) #
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0220133113310220;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y25_N44
dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ) #
// ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FECCFECC;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ) # (\u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ) #
// (\u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h1030103050F050F0;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ) #
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1])))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00BF00BFFFFFFFFF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N32
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & (
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q & ( !\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0] & (
// (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .lut_mask = 64'h0303333333333333;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout = (\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout & \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0303030303030303;
defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y25_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout & ((!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout &
// ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0])))) #
// (\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1])))) ) )
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h029B029B03CF03CF;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y25_N11
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y29_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_009|src_data [107] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [2] & ( (\u0|hps_0|fpga_interfaces|h2f_AWID [2] & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [2]),
.datad(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_009|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[107] .lut_mask = 64'h000F000F333F333F;
defparam \u0|mm_interconnect_0|cmd_mux_009|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y29_N1
dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_009|src_data [107]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[107] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y27_N5
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 (
// Equation(s):
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout = (!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg
// [107])) # (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q )))
.dataa(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [107]),
.datad(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 .lut_mask = 64'h0A5F0A5F0A5F0A5F;
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y27_N4
dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q & \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q &
// \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q & ( ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q & (
// (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 .lut_mask = 64'h000F000F555F555F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~11 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q &
// \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q & ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q & (
// !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q & \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 .lut_mask = 64'h050505050505FFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q & ( ((\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q & (
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ),
.datad(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107]~13 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[107] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [107] = ( \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [107]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[107] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) #
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 .lut_mask = 64'h00000000505F505F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y26_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout &
// (((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0])))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout &
// ((\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ) #
// (\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ))) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00BB00BB0B4F0B4F;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X15_Y26_N32
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X17_Y26_N29
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( (!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (
// (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y26_N14
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y26_N2
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ) ) # (
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h3333333300FF00FF;
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y26_N35
dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q &
// !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~0 .lut_mask = 64'h3300330000000000;
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout = ( !\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|rsp_demux|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y30_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q & ( ((\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout &
// \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q )) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q & (
// (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout & \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout &
// \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q & ( ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q
// )) # (\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~6 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout = ( \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( ((\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q
// )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout & ( (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106]~8 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[106] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [106] = ( \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout & ( (((\u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ) #
// (\u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [106]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106] .lut_mask = 64'h7FFF7FFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[106] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y32_N2
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y32_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] $ (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 .lut_mask = 64'h5A5A5A5A00FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout &
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'h0800080000000000;
defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ((!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) #
// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout )))
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF050F050F050F050;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y21_N35
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))
// # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q
// )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F550F550F330F33;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y21_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout & (
// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0000000055555555;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y21_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h044404440CCC0CCC;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]))) #
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y21_N47
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X18_Y23_N11
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_015|src_data [105] = ( \u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) ) ) # (
// !\u0|hps_0|fpga_interfaces|h2f_ARID [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWID [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWID [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[105] .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y23_N13
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [105]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[105] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y23_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [105]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y23_N53
dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout = (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q & (((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q )))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q & (((\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q )) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout )))
.dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 .lut_mask = 64'h111F111F111F111F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q &
// \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout )) # (\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ) ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q & (
// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q & \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 .lut_mask = 64'h0303030357575757;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout = (!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & (\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & (\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ))) #
// (\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout & (((\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout & \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q )) #
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q )))
.dataa(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ),
.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 .lut_mask = 64'h0357035703570357;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y27_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q )) #
// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout &
// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ),
.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout = ( \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( ((\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q &
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 .lut_mask = 64'h0505050505FF05FF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105]~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|src_data[105] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|src_data [105] = ( \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout & ( \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout & (
// !\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout & ( ((\u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ) # (\u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout )) # (\u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|src_data [105]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105] .lut_mask = 64'h7F7FFFFFFFFFFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|src_data[105] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] = ((\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .lut_mask = 64'h555F555F555F555F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y23_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h000F000F0F0F0F0F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & (
// (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # ((!\u0|mm_interconnect_0|router|Equal6~2_combout ) # ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) #
// (!\u0|mm_interconnect_0|router|Equal6~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'hFFFFFFFEF0F0F0F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])))) ) ) ) # (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// ((\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1])))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h1500FFFF1500FFAA;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y19_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .lut_mask = 64'h8000800000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout &
// (((!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ) #
// (!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q )) # (\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [1]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .lut_mask = 64'hCCC4CCC4CC4CCC4C;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] &
// !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000F0F0F0F0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y19_N14
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h3313331320002000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & (
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout )) ) ) # (
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.datag(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h3000F700FFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00CC00CC33FF33FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N56
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h1B1B1B1B0A5F0A5F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'hFFFFFFFF00CC00CC;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y19_N11
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout
// & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF0F0F0F0FFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal6~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & (\u0|mm_interconnect_0|router|Equal6~2_combout &
// \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0])) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .lut_mask = 64'h0000000000050005;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000500050;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #
// ((!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )))) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h4444444454445444;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FF00FF00C000C0;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h000C000CCCCCCCCC;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (
// (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h773377337F3F7F3F;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y19_N26
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (((!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ),
.datag(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0808F0F00808F0FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & ( \u0|mm_interconnect_0|router|Equal6~0_combout & ( (\u0|mm_interconnect_0|router|Equal6~2_combout &
// ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~0 .lut_mask = 64'h0000000000001313;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & (
// (!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ) # (\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout & (
// !\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 .lut_mask = 64'h0000FFFF0000F5F5;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y32_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .lut_mask = 64'h0000FFFFFFFF0000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout
// ) ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h000F000F000FFFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] &
// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .lut_mask = 64'h30FF30FF30303030;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .lut_mask = 64'h0AA00AA05FF55FF5;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y20_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout )) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg
// [2] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .lut_mask = 64'h0033FF33F0330F33;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y20_N23
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hAAAAAAAA5AAA5AAA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &
// (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &
// ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hC0C0C0CFC5C5C5CF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y20_N38
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]
// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .lut_mask = 64'h003300330F3F0F3F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [5])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .lut_mask = 64'h2288228877DD77DD;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y20_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y20_N26
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (
// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h0303030303FF03FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] $
// (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [5])))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg
// [6] $ (((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h208A208A75DF75DF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_014|src_data [88] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|src_data [88]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|src_data [87]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hAAAAAAAA00000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q )) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .lut_mask = 64'h0030003000C000C0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[35] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [35]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .lut_mask = 64'h0000FFFF5555FFFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[35] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [35]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[32] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [32]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .lut_mask = 64'h0F0F0F0F0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[32] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N20
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [32]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[33] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]) ) ) # (
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [33]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .lut_mask = 64'h00FF00FF0FFF0FFF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[33] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [33]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_data[34] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_data [34]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .lut_mask = 64'h5555555555FF55FF;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_data[34] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y20_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|src_data [34]),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .lut_mask = 64'h00F000F0C0F0C0F0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] &
// !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000F0F0F0F0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N8
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// & ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// & ((\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0])))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0007FFFF0007F0FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N44
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y22_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &
// ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .lut_mask = 64'h0F0F0F0F3F3F3F3F;
defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N10
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h2220222022002200;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout &
// \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1])) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h000000000AFF0A0A;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout &
// ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFFF00001D1D0000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y20_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout
// & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0080FFFF0000FFFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y20_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00FF00FF1D1D1D1D;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00FF000300FF0000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout
// & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000100010;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) )
// # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q
// & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0E0E0E0E0C0C0C0C;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &
// ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h04040404CCCCCCCC;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (
// (((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h775577557F5F7F5F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N32
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
// # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h20222022A0AAA0AA;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|cmd_mux_014|src_payload [0]) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (
// \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (((!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (((!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (
// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (((!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .lut_mask = 64'hCE02CE02CE020A0A;
defparam \u0|mm_interconnect_0|cmd_mux_014|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y19_N20
dffeas \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [14]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .lut_mask = 64'h00000000FF0FFF0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & !\u0|mm_interconnect_0|router_001|Equal20~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .lut_mask = 64'hCCCCCCCCC0C0C0C0;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|WideOr1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout = ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|WideOr1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|WideOr1 .lut_mask = 64'hFF00FF00AA00AA00;
defparam \u0|mm_interconnect_0|cmd_mux_014|WideOr1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q & !\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ) )
// ) # ( !\u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout & ( (!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout & (\u0|mm_interconnect_0|cmd_mux_014|src_payload [0] &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),
.datab(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .lut_mask = 64'h0C000C0088888888;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y19_N50
dffeas \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y19_N37
dffeas \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal20~0_combout & (\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout &
// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1])) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal20~0_combout & (\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout &
// ((!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
.datab(!\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .lut_mask = 64'h0203020300030003;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y19_N32
dffeas \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y19_N1
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X30_Y19_N53
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .lut_mask = 64'h0033003333333333;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h2222222200000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ))) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h1005100511551155;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FFFF0000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y18_N41
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] $ ((((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .lut_mask = 64'h0000339300000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )))) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0777077700000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N11
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .lut_mask = 64'h0333033333333333;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout = (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout & \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout & \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0])) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h02029B9B0303CFCF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N47
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y17_N17
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y17_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00550055AAFFAAFF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N40
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y18_N50
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y17_N29
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y17_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q &
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .lut_mask = 64'h00F000F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X21_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & (
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout
// ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & (
// !\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout & ( (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout & (\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout &
// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 .lut_mask = 64'h0111033305550FFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( (\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 .lut_mask = 64'h01031133050F55FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout = ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) #
// (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout &
// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & (
// !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout
// ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout &
// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 .lut_mask = 64'h0015003F15153F3F;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y22_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 .lut_mask = 64'h0000000000000004;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & (
// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid .lut_mask = 64'hFF00AA0000000000;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid .lut_mask = 64'hCCC0CCC000000000;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout & (
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|WideOr1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout = ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout & ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ) #
// (((!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout )) # (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout )) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1 .lut_mask = 64'hFFFFFFFFFFFFFFFB;
defparam \u0|mm_interconnect_0|rsp_mux_001|WideOr1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal6~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal6~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] &
// (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|router_001|Equal2~0_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),
.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal6~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal6~0 .lut_mask = 64'h0000000100000000;
defparam \u0|mm_interconnect_0|router_001|Equal6~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y31_N29
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[18] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[18] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[18] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & (
// (\u0|mm_interconnect_0|router_001|Equal6~0_combout & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|router_001|Equal6~0_combout & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|router_001|Equal6~0_combout & \u0|hps_0|fpga_interfaces|h2f_ARVALID
// [0]) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 .lut_mask = 64'h0303030300000303;
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & (
// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & \u0|mm_interconnect_0|cmd_mux_018|src_payload [0]) ) ) ) # (
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout &
// (!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & ((\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]))) ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout &
// (!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q )) # (\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & (((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &
// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0])))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 .lut_mask = 64'h888D88DD000F00FF;
defparam \u0|mm_interconnect_0|cmd_mux_018|update_grant~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout = !\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y23_N14
dffeas \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & (
// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] )
// ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [18]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 .lut_mask = 64'h0F0F0F0F00000F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|router_001|Equal6~0_combout & ( ((\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & (\u0|mm_interconnect_0|router|Equal6~0_combout &
// \u0|mm_interconnect_0|router|Equal6~2_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|router_001|Equal6~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout &
// (\u0|mm_interconnect_0|router|Equal6~0_combout & \u0|mm_interconnect_0|router|Equal6~2_combout )) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal6~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal6~2_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 .lut_mask = 64'h001100110F1F0F1F;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & (
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|cmd_mux_018|src_payload [0]) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout & (((!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout &
// (!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ((\u0|mm_interconnect_0|cmd_mux_018|src_payload [0])))) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),
.datae(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 .lut_mask = 64'h0000A0E4000000CC;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y23_N29
dffeas \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0] .power_up = "low";
// synopsys translate_on
// Location: FF_X28_Y23_N25
dffeas \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & (
// !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( (\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout & (!\u0|mm_interconnect_0|router|Equal6~1_combout & !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0])) ) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1] & ( (\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]) ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
.datae(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 .lut_mask = 64'h5500440055555555;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y23_N5
dffeas \u0|mm_interconnect_0|cmd_mux_018|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal6~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal6~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 .lut_mask = 64'h0000000000550055;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout &
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #
// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0111011103330333;
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";
// synopsys translate_on
// Location: FF_X25_Y19_N47
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ) #
// ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q & ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] ) )
// ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]
// ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y19_N29
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( ((\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q )) #
// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ))) ) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 .lut_mask = 64'h2233333377333333;
defparam \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout & (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout )))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h150015003F003F00;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout & (
// ((\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout & !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] &
// ((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ))) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1] & (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0000CFCF00CF30FF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N5
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout & (
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout )) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]))) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00F700F7FFFFFFFF;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y18_N53
dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y18_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid (
// Equation(s):
// \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] &
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q & (
// (!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]) ) )
.dataa(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid .lut_mask = 64'hC0C0C0C080808080;
defparam \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ) ) # (
// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ) #
// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ))) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),
.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .lut_mask = 64'hC0CCCCCCC0CCCCCC;
defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y23_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout &
// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 .lut_mask = 64'h000F000F00000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_007|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_007|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_007|src1_valid .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_007|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_004|src1_valid (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout = ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_004|src1_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_004|src1_valid .lut_mask = 64'hF0F0F0F000000000;
defparam \u0|mm_interconnect_0|rsp_demux_004|src1_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y30_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & ( \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout &
// (!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ) # (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ) # (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ) #
// (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ) #
// (!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 .lut_mask = 64'hFAFAC8C8FA00C800;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & ( \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout & ( (!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout &
// (!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & (
// \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout & ( (!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) # (!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout & ( (!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) #
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout & ( !\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout & ( (!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ) #
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 .lut_mask = 64'hFAFAC8C8FA00C800;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y37_N38
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y37_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y37_N32
dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q & ( (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 .lut_mask = 64'h000000003F7F3F7F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~6 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y37_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout &
// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout )))) ) ) )
// # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout
// & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout )))) )
// ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout &
// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 .lut_mask = 64'h0A0B0A0B0A0B0A0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y30_N23
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y30_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h00330033CCFFCCFF;
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y30_N10
dffeas \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y30_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ) ) # (
// !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q & (((\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.datad(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 .lut_mask = 64'h030703070F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~10 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y32_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout = ( \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout
// & (((\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout & \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout )) #
// (\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ) ) ) # ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ) ) )
.dataa(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ),
.datae(!\u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(!\u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 .lut_mask = 64'h00FF000000FF0057;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y31_N11
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y31_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h5555555500FF00FF;
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X9_Y31_N50
dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q & ( (((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q &
// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 .lut_mask = 64'h000000001FFF1FFF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~12 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X9_Y31_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout & ((\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ) #
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout &
// ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & (
// (\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ),
.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 .lut_mask = 64'h0F0F00030F0F0103;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y36_N56
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y36_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),
.datac(gnd),
.datad(gnd),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h00003333CCCCFFFF;
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y33_N35
dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y33_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q & (((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 .lut_mask = 64'h0057005700FF00FF;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~14 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y37_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~15 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout & (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ) #
// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout &
// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ),
.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~15 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~15 .lut_mask = 64'h3030303130303333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N29
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X23_Y35_N43
dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q &
// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 .lut_mask = 64'h1133113313331333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y35_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout )))) ) ) ) #
// ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout )))) ) ) ) #
// ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout &
// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout )))) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 .lut_mask = 64'h0C0D0C0D0C0D0C0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X8_Y35_N41
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X8_Y35_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q )))
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hA0AFA0AFA0AFA0AF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder (
// Equation(s):
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder .shared_arith = "off";
// synopsys translate_on
// Location: FF_X13_Y35_N50
dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 .lut_mask = 64'h07070707070F070F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y35_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout &
// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout &
// ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 .lut_mask = 64'h5500550555005515;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout = ( \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout & ( \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout &
// (!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ) # (!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout & (
// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ) # (!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ))) ) ) ) # (
// \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout & ((!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ) #
// (!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout & ( (!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ) #
// (!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 .lut_mask = 64'hEEEEE0E0EE00E000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X19_Y17_N59
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X19_Y17_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hAAAAAAAA00FF00FF;
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y17_N5
dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y17_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ) ) # (
// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 .lut_mask = 64'h050705070F0F0F0F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~19 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y17_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout )) #
// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ),
.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 .lut_mask = 64'h5555000055550515;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~20 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X10_Y21_N29
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X10_Y21_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0FFF0FF000F000F;
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X11_Y20_N7
dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q &
// (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q & ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 .lut_mask = 64'h00770077007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~21 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y20_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout = ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout &
// (((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout )))
// ) ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ) )
.dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ),
.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 .lut_mask = 64'h0000FFFF00000307;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~22 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N35
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))
// # (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q )))
.dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h4747474747474747;
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X18_Y18_N5
dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q &
// (((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q & ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]) #
// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]))) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),
.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 .lut_mask = 64'h07070707070F070F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~23 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y18_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout & ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout & ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ) # ((\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout & \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) ) # (
// \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout & ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout &
// ((!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ) # (\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout & (
// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout & ( (\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout & !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) )
.dataa(!\u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ),
.datab(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ),
.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ),
.datae(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ),
.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 .lut_mask = 64'h0F000F050F010F05;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~24 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N5
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h05050505AFAFAFAF;
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y34_N14
dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q &
// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]))) ) )
// # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 .lut_mask = 64'h1313131313331333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~25 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y34_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #
// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout &
// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q &
// ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ),
.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),
.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 .lut_mask = 64'h3333333301010103;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~26 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y21_N14
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y21_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'hF0F0F0F000FF00FF;
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X17_Y19_N7
dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X17_Y19_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q &
// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]))) ) ) # (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),
.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 .lut_mask = 64'h005F005F007F007F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & (
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ) #
// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & (
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout & (\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout &
// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout & (
// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ) ) )
.dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ),
.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),
.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 .lut_mask = 64'h0F0F0F0F00030103;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~18 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N41
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h000F000FF0FFF0FF;
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X22_Y33_N22
dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] &
// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 .lut_mask = 64'h0313031333333333;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~27 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X22_Y33_N45
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~28 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~28_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q & (
// (\u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout & (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout )) #
// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q & (
// \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~28_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~28 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~28 .lut_mask = 64'h0F0F0F0F0000010F;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~28 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y31_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~28_combout & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout &
// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout & (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout & !\u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~28_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29 .lut_mask = 64'h8000000000000000;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X19_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux_001|src_payload [0] = ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout & ( ((!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ) #
// ((!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ) # (!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout ))) # (\u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout & ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ) ) # ( \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout & (
// !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ) ) # ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ),
.datab(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ),
.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout ),
.datae(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] .lut_mask = 64'hFFFFFFFFFFFFFFFD;
defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload[0] .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y28_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & (
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ) #
// (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] &
// ((!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) # ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])))) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [3] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout & (!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [3]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0 .lut_mask = 64'hF880E000E0008000;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N27
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4] & ( (\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]) #
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// \u0|hps_0|fpga_interfaces|h2f_AWADDR [4]) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 .lut_mask = 64'h00AA00AA55FF55FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y30_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout & (
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// ((!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout )))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout )))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (\u0|hps_0|fpga_interfaces|h2f_AWBURST [1] &
// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout ))) # (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout )))) ) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout & ( (\u0|hps_0|fpga_interfaces|h2f_AWBURST [0] &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [1]),
.datab(!\u0|hps_0|fpga_interfaces|h2f_AWBURST [0]),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 .lut_mask = 64'h003340738CBFCCFF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y30_N14
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[4] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[4] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst[4] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y30_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~0 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4] &
// !\u0|hps_0|fpga_interfaces|h2f_AWADDR [5])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR
// [4] & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [5])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4])) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [4]),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [4]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [5]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [5]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~0 .lut_mask = 64'hE222E222C000C000;
defparam \u0|mm_interconnect_0|router|Equal7~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y29_N39
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~5 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWADDR [15] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]
// & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13])) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWADDR [15] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &
// (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15] &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13])))) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [15]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [13]),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [13]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [15]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~5 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~5 .lut_mask = 64'hE4A0E4A044004400;
defparam \u0|mm_interconnect_0|router|Equal7~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~6 (
// Equation(s):
// \u0|mm_interconnect_0|router|Equal7~6_combout = ( \u0|mm_interconnect_0|router|Equal7~4_combout & ( \u0|mm_interconnect_0|router|Equal7~5_combout & ( (\u0|mm_interconnect_0|router|Equal7~0_combout & (\u0|mm_interconnect_0|router|Equal7~2_combout &
// (\u0|mm_interconnect_0|router|Equal7~3_combout & \u0|mm_interconnect_0|router|Equal7~1_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal7~0_combout ),
.datab(!\u0|mm_interconnect_0|router|Equal7~2_combout ),
.datac(!\u0|mm_interconnect_0|router|Equal7~3_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~1_combout ),
.datae(!\u0|mm_interconnect_0|router|Equal7~4_combout ),
.dataf(!\u0|mm_interconnect_0|router|Equal7~5_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router|Equal7~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router|Equal7~6 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router|Equal7~6 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|router|Equal7~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src11_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & ( (\u0|mm_interconnect_0|router|Equal7~6_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout & \u0|mm_interconnect_0|router|Equal14~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal14~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~1 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y26_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ) ) ) #
// ( \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1] & ( !\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0] & ( \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg
// [1] & ( !\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0] & ( (!\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout & \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ) ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [1]),
.dataf(!\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 .lut_mask = 64'h00CC00FF000000FF;
defparam \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y26_N41
dffeas \u0|mm_interconnect_0|cmd_mux_011|saved_grant[1] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[1] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_011|saved_grant[1] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y24_N43
dffeas \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_011|saved_grant [1]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";
// synopsys translate_on
// Location: FF_X21_Y24_N31
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q & ( (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) #
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q & (
// (\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h303030303F3F3F3F;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N56
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";
// synopsys translate_on
// Location: FF_X27_Y24_N11
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y24_N9
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ) ) # (
// !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),
.datad(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0F0F0F0F00FF00FF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N23
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68] .power_up = "low";
// synopsys translate_on
// Location: FF_X19_Y24_N43
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N48
cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 (
// Equation(s):
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used
// [1]) # (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ) ) ) # ( !\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (
// (\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used [1]),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h03030303CFCFCFCF;
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X21_Y24_N19
dffeas \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X21_Y24_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q & ( (!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q &
// \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ),
.datac(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 .lut_mask = 64'h0C0C0C0C00000000;
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y24_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout = ( !\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 .lut_mask = 64'h0F0F0F0F00000000;
defparam \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y29_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|WideOr1~0 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout = ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout &
// ((!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (
// \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout
// & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout
// ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout )))) ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (
// (!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ((!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ) # (\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),
.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~0 .lut_mask = 64'hCC440C04FF550F05;
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y26_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|WideOr1~1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout = ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout &
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout )))) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( (\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) #
// (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & (
// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout & ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout & ( !\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ) ) )
// )
.dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),
.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ),
.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),
.datad(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~1 .lut_mask = 64'hFF550F0533110301;
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X18_Y24_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux|WideOr1 (
// Equation(s):
// \u0|mm_interconnect_0|rsp_mux|WideOr1~combout = ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & (
// \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout & ( (((!\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ) # (\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout )) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout )) #
// (\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & ( !\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ) ) # ( !\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout & (
// !\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ) )
.dataa(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ),
.datab(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ),
.datad(!\u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ),
.datae(!\u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ),
.dataf(!\u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1 .lut_mask = 64'hFFFFFFFFFF7FFFFF;
defparam \u0|mm_interconnect_0|rsp_mux|WideOr1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~1 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal1~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [10] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [12] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [14] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [11])) ) )
.dataa(gnd),
.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [12]),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [14]),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [11]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [10]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal1~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal1~1 .lut_mask = 64'hC000C00000000000;
defparam \u0|mm_interconnect_0|router_001|Equal1~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y31_N21
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal20~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal20~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~1_combout & (\u0|mm_interconnect_0|router_001|Equal13~0_combout &
// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal18~0_combout ))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datab(!\u0|mm_interconnect_0|router_001|Equal13~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal20~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal20~0 .lut_mask = 64'h0000000000010001;
defparam \u0|mm_interconnect_0|router_001|Equal20~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]) #
// ((!\u0|mm_interconnect_0|router_001|Equal20~0_combout & \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1])))) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout &
// ((!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]) # (\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]))) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal20~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 .lut_mask = 64'h3033303330323032;
defparam \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y19_N56
dffeas \u0|mm_interconnect_0|cmd_mux_014|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_014|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ) # (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]))) ) ) # (
// !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ) ) )
.dataa(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.datad(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h000F000F050F050F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) )
// # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout
// ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(gnd),
.datac(gnd),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h55FF55FF00FF00FF;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N59
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N3
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )
// # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF0FFF0FFF0FFF0F;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y19_N33
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q
// ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y19_N35
dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y20_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &
// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )
// # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )))) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .lut_mask = 64'hE000000000000000;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X27_Y18_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & (
// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & (
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (
// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout )) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ))) ) ) ) # (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .lut_mask = 64'h505070D050505050;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y19_N12
cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = (
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &
// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q
// )))) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout &
// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),
.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),
.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),
.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datag(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0C00F0F00C00F5F5;
defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N51
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & \u0|mm_interconnect_0|router|Equal7~6_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~1 .lut_mask = 64'h0000000000000004;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N57
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|sink_ready~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout &
// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & \u0|mm_interconnect_0|router|Equal7~6_combout ))) ) ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),
.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),
.datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~2 .lut_mask = 64'h0000000000000001;
defparam \u0|mm_interconnect_0|cmd_demux|sink_ready~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N15
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout = ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// (!\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ) # ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (
// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ((!\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ) #
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout & (
// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( (!\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ) #
// ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &
// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ),
.datae(!\u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~0 .lut_mask = 64'hFF88F080FF880000;
defparam \u0|mm_interconnect_0|cmd_demux|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y28_N36
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & (
// (\u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ((!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ) # (\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout & (
// !\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout & ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] ) ) )
.dataa(gnd),
.datab(!\u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),
.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.dataf(!\u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 .lut_mask = 64'h000000FF000000CF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N6
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal14~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal14~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal14~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal14~0 .lut_mask = 64'h00000000F0F0F0F0;
defparam \u0|mm_interconnect_0|router_001|Equal14~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y31_N42
cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal15~0 (
// Equation(s):
// \u0|mm_interconnect_0|router_001|Equal15~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] &
// (\u0|mm_interconnect_0|router_001|Equal14~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~2_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]))) ) ) )
.dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),
.datab(!\u0|mm_interconnect_0|router_001|Equal14~0_combout ),
.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),
.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),
.datae(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|router_001|Equal15~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|router_001|Equal15~0 .lut_mask = 64'h0000000000000100;
defparam \u0|mm_interconnect_0|router_001|Equal15~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X11_Y36_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] &
// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )) #
// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) ) # (
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ) ) # (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout & (
// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] &
// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) )
.dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),
.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),
.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),
.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 .lut_mask = 64'h000F0F0F070F0F0F;
defparam \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y29_N54
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|router_001|Equal18~1_combout & (
// ((\u0|mm_interconnect_0|router_001|Equal15~0_combout & \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ) ) ) ) # (
// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( \u0|mm_interconnect_0|router_001|Equal18~1_combout & ( ((\u0|mm_interconnect_0|router_001|Equal15~0_combout &
// (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) # (\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ) ) ) ) # (
// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|router_001|Equal18~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal15~0_combout &
// \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & ( !\u0|mm_interconnect_0|router_001|Equal18~1_combout & (
// (\u0|mm_interconnect_0|router_001|Equal15~0_combout & (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) )
.dataa(!\u0|mm_interconnect_0|router_001|Equal15~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),
.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ),
.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),
.dataf(!\u0|mm_interconnect_0|router_001|Equal18~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 .lut_mask = 64'h0101111101FF11FF;
defparam \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X23_Y31_N0
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q &
// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3] $ (!\u0|mm_interconnect_0|router_001|src_data[103]~0_combout )))) ) ) # (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) )
.dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id [3]),
.datad(!\u0|mm_interconnect_0|router_001|src_data[103]~0_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id .lut_mask = 64'h3333333323322332;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X25_Y31_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout &
// (((!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ) # (\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout )) # (\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout & (
// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ),
.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout ),
.datac(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ),
.datad(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 .lut_mask = 64'hCCCCCCCCC4CCC4CC;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N18
cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid (
// Equation(s):
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout = ( \u0|hps_0|fpga_interfaces|h2f_WVALID [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWVALID [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid .extended_lut = "off";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid .lut_mask = 64'h0000000000FF00FF;
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y27_N37
dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[18] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|router|Equal6~1_combout ),
.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [18]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[18] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[18] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X28_Y27_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src18_valid~0 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout &
// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [18]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),
.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [18]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~0 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~0 .lut_mask = 64'h0F0F0F0F000F000F;
defparam \u0|mm_interconnect_0|cmd_demux|src18_valid~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X28_Y23_N24
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout = ( \u0|mm_interconnect_0|router|Equal6~1_combout & ( (\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout & ((!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]) #
// ((!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout & \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1])))) ) )
.dataa(!\u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ),
.datab(!\u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [0]),
.datad(!\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg [1]),
.datae(gnd),
.dataf(!\u0|mm_interconnect_0|router|Equal6~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 .lut_mask = 64'h0000000050545054;
defparam \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X28_Y23_N2
dffeas \u0|mm_interconnect_0|cmd_mux_018|saved_grant[0] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[0] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|cmd_mux_018|saved_grant[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X27_Y19_N30
cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 (
// Equation(s):
// \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_WDATA [2] & ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] ) )
.dataa(gnd),
.datab(gnd),
.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),
.datad(gnd),
.datae(gnd),
.dataf(!\u0|hps_0|fpga_interfaces|h2f_WDATA [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 .extended_lut = "off";
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 .lut_mask = 64'h000000000F0F0F0F;
defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload~2 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X27_Y19_N32
dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(\u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ),
.asdata(vcc),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .is_wysiwyg = "true";
defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[2] .power_up = "low";
// synopsys translate_on
// Location: FF_X25_Y19_N17
dffeas \u0|clock_sel|data_out[2] (
.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),
.d(gnd),
.asdata(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [2]),
.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),
.aload(gnd),
.sclr(gnd),
.sload(vcc),
.ena(\u0|clock_sel|always0~0_combout ),
.devclrn(devclrn),
.devpor(devpor),
.q(\u0|clock_sel|data_out [2]),
.prn(vcc));
// synopsys translate_off
defparam \u0|clock_sel|data_out[2] .is_wysiwyg = "true";
defparam \u0|clock_sel|data_out[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~41 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [0] ) + ( VCC ) + ( !VCC ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~42 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [0] ) + ( VCC ) + ( !VCC ))
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~42 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~41 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~41 .lut_mask = 64'h0000000000003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~41 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~17 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &
// \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &
// \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &
// (\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout & ((!\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout )))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & (
// !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout & \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout )) ) ) )
.dataa(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.datab(!\u0|clock_sel|data_out [2]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~17 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~17 .lut_mask = 64'h0005004500550055;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~17 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N20
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[0] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[0] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[0] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~2 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ))
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~42 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~2 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~1 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N3
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~7 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout & ( (((!\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout )) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\u0|clock_sel|data_out [2]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~7 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~7 .lut_mask = 64'h0000000000005FDF;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~7 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N5
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[1] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[1] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[1] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~6 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ))
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~2 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~6 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~5 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~8 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout & ( (((\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & !\u0|clock_sel|data_out [2])) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datad(!\u0|clock_sel|data_out [2]),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~8 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~8 .lut_mask = 64'h0000000000007F77;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~8 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N26
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[2] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[2] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[2] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N9
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~13 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~14 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~6 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~14 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~13 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~13 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~13 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~10 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout & ( (((\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & !\u0|clock_sel|data_out [2])) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datad(!\u0|clock_sel|data_out [2]),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~10 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~10 .lut_mask = 64'h0000000000007F77;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~10 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N44
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[3] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[3] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[3] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~17 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~18 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~14 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~18 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~17 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~17 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~17 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~10 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ))
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~18 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~10 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~9 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~9 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~37 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~10 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~38 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~10 ))
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~10 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~38 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~37 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~37 .lut_mask = 64'h0000FFFF00003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~37 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~16 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout & ( (((!\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout )) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\u0|clock_sel|data_out [2]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~16 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~16 .lut_mask = 64'h00000000000077F7;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~16 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N59
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[6] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[6] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[6] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|always4~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout )) ) ) #
// ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ((\R_400_to_2_5_10_100_200_300MHZ|counter [6]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter [5] &
// (\R_400_to_2_5_10_100_200_300MHZ|counter [3] & !\R_400_to_2_5_10_100_200_300MHZ|counter [6])))) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~0 .lut_mask = 64'h001A001A00500050;
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N21
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~21 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~22 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ))
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~38 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~22 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~21 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~21 .lut_mask = 64'h0000FFFF00005555;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~21 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~12 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout & ( (((\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & !\u0|clock_sel|data_out [2])) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datad(!\u0|clock_sel|data_out [2]),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~12 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~12 .lut_mask = 64'h0000000000007F77;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~12 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N32
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[7] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[7] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[7] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~29 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~30 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~22 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~30 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~29 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~29 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~29 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~33 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ))
// \R_400_to_2_5_10_100_200_300MHZ|Add0~34 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~30 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
.cout(\R_400_to_2_5_10_100_200_300MHZ|Add0~34 ),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~33 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~33 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~33 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~15 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout & ( (((\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout & !\u0|clock_sel|data_out [2])) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datad(!\u0|clock_sel|data_out [2]),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~15 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~15 .lut_mask = 64'h0000000000007F77;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~15 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N56
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[9] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[9] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[9] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add0~25 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter [10] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add0~34 ))
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(\R_400_to_2_5_10_100_200_300MHZ|Add0~34 ),
.sharein(gnd),
.combout(),
.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~25 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;
defparam \R_400_to_2_5_10_100_200_300MHZ|Add0~25 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~13 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout & ( (((!\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout )) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\u0|clock_sel|data_out [2]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~13 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~13 .lut_mask = 64'h0000000000005DFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~13 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N2
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[10] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[10] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[10] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|always4~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [8] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [10] & !\R_400_to_2_5_10_100_200_300MHZ|counter [9]) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~2 .lut_mask = 64'hF000F00000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|always4~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|always4~3_combout = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout &
// ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter [5]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & (
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & (
// (\R_400_to_2_5_10_100_200_300MHZ|counter [2] & (\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ))) ) ) ) # (
// !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (\R_400_to_2_5_10_100_200_300MHZ|counter [5] & \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ))
// ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~3 .lut_mask = 64'h0003000100CC00FC;
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~3 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N39
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout = (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & !\R_400_to_2_5_10_100_200_300MHZ|counter [6])
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datad(gnd),
.datae(gnd),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0 .lut_mask = 64'hA0A0A0A0A0A0A0A0;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N12
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|always4~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|always4~1_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout & (\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout &
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout )) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|always4~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~1 .lut_mask = 64'h0000000001010101;
defparam \R_400_to_2_5_10_100_200_300MHZ|always4~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout = ( \R_400_to_2_5_10_100_200_300MHZ|always4~1_combout & ( (!\u0|clock_sel|data_out [1] & ((!\u0|clock_sel|data_out [0] & ((\R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ))) #
// (\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout )))) # (\u0|clock_sel|data_out [1] & (\u0|clock_sel|data_out [0])) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|always4~1_combout & ( (!\u0|clock_sel|data_out [1] &
// ((!\u0|clock_sel|data_out [0] & ((\R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ))) # (\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout )))) ) )
.dataa(!\u0|clock_sel|data_out [1]),
.datab(!\u0|clock_sel|data_out [0]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|always4~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6 .lut_mask = 64'h028A028A139B139B;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N27
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~9 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout & ( (((!\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout )) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\u0|clock_sel|data_out [2]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~9 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~9 .lut_mask = 64'h00000000000077F7;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~9 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N29
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[5] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[5] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[5] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [3] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [4] &
// !\R_400_to_2_5_10_100_200_300MHZ|counter [1]))) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 .lut_mask = 64'h8000800000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y12_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Equal0~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [0] ) ) )
.dataa(gnd),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
.datad(gnd),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal0~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal0~0 .lut_mask = 64'h00000000F0F00000;
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N0
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout & ( (\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout &
// (((\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (
// !\R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout & ( (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1 .lut_mask = 64'h1111000013110000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] ) ) # (
// \R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [0]) #
// ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ) # (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ))) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 .lut_mask = 64'hFFFEFFFFFFFFFFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N24
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout & ( (\u0|clock_sel|data_out [1] & (!\u0|clock_sel|data_out [0] & (\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout
// ))) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout & ( (\u0|clock_sel|data_out [1] & (\u0|clock_sel|data_out [2] & ((\R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout ) # (\u0|clock_sel|data_out [0])))) ) )
.dataa(!\u0|clock_sel|data_out [1]),
.datab(!\u0|clock_sel|data_out [0]),
.datac(!\u0|clock_sel|data_out [2]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout ),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2 .lut_mask = 64'h0105010500040004;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N33
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~14 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout & ( (((!\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout )) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\u0|clock_sel|data_out [2]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~14 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~14 .lut_mask = 64'h00000000000077F7;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~14 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N35
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[8] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[8] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[8] .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [8] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [10] & !\R_400_to_2_5_10_100_200_300MHZ|counter [9])) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [8]),
.datab(gnd),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [10]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [9]),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 .lut_mask = 64'hA000A00000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|Equal2~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X17_Y12_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [0] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [1] ) )
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [0]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [1]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0 .lut_mask = 64'hFFFF000000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N30
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3_combout = ( \u0|clock_sel|data_out [0] & ( \u0|clock_sel|data_out [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ((!\u0|clock_sel|data_out [1]) #
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout )))) ) ) ) # ( !\u0|clock_sel|data_out [0] & ( \u0|clock_sel|data_out [2] & ( (!\u0|clock_sel|data_out [1] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [5] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter
// [2]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout )))) ) ) ) # ( \u0|clock_sel|data_out [0] & ( !\u0|clock_sel|data_out [2] & ( (!\u0|clock_sel|data_out [1]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2] &
// !\R_400_to_2_5_10_100_200_300MHZ|counter [5])) ) ) ) # ( !\u0|clock_sel|data_out [0] & ( !\u0|clock_sel|data_out [2] ) )
.dataa(!\u0|clock_sel|data_out [1]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datae(!\u0|clock_sel|data_out [0]),
.dataf(!\u0|clock_sel|data_out [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3 .lut_mask = 64'hFFFFEEAA8A008C00;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N57
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [3] & !\R_400_to_2_5_10_100_200_300MHZ|counter [2]) ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0 .lut_mask = 64'hC0C0C0C000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N6
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout = ( \u0|clock_sel|data_out [0] & ( !\u0|clock_sel|data_out [2] & ( (!\u0|clock_sel|data_out [1] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & !\R_400_to_2_5_10_100_200_300MHZ|counter [5])) ) ) ) #
// ( !\u0|clock_sel|data_out [0] & ( !\u0|clock_sel|data_out [2] & ( (!\u0|clock_sel|data_out [1] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ))))
// # (\u0|clock_sel|data_out [1] & (!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) ) )
.dataa(!\u0|clock_sel|data_out [1]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datae(!\u0|clock_sel|data_out [0]),
.dataf(!\u0|clock_sel|data_out [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4 .lut_mask = 64'hEE8A880000000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout & ( \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout & (
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & (\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout & (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~3_combout & !\R_400_to_2_5_10_100_200_300MHZ|counter [6]))) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~3_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5 .lut_mask = 64'h0100010033333333;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N45
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter~11 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout = ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ( \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout & ( (((!\u0|clock_sel|data_out [2] & \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout )) #
// (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ),
.datac(!\u0|clock_sel|data_out [2]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ),
.datae(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~11 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~11 .lut_mask = 64'h00000000000077F7;
defparam \R_400_to_2_5_10_100_200_300MHZ|counter~11 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X14_Y12_N47
dffeas \R_400_to_2_5_10_100_200_300MHZ|counter[4] (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4] .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|counter[4] .power_up = "low";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter [3] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] ) )
.dataa(gnd),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datac(gnd),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1 .lut_mask = 64'hCCCCCCCC00000000;
defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [2] & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) #
// (!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout )) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [2] )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ),
.datad(gnd),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 .lut_mask = 64'hFFFFFFFFFEFEFEFE;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] &
// ( ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [2] & !\R_400_to_2_5_10_100_200_300MHZ|counter [3]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter [5]) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter
// [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) #
// ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter [3])) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 .lut_mask = 64'hFAFFFFFFFDF5FFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X13_Y12_N51
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) # (\R_400_to_2_5_10_100_200_300MHZ|counter
// [6])) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [4] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ((!\R_400_to_2_5_10_100_200_300MHZ|counter [3]) #
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [5]))) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6] & ((\R_400_to_2_5_10_100_200_300MHZ|counter [5])))) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [3]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [4]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 .lut_mask = 64'hEEFBEEFBFFBBFFBB;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 .shared_arith = "off";
// synopsys translate_on
// Location: MLABCELL_X14_Y12_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (!\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ) #
// ((\R_400_to_2_5_10_100_200_300MHZ|counter [6] & \R_400_to_2_5_10_100_200_300MHZ|counter [5])) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter [7] & (
// (!\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter [6]) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & (
// (!\R_400_to_2_5_10_100_200_300MHZ|counter [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) # (!\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ))) ) ) ) # (
// !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter [7] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter [6]) # ((!\R_400_to_2_5_10_100_200_300MHZ|counter [5]) #
// (!\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout )) ) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter [7]),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 .lut_mask = 64'hFFFCFFFEFF33FF03;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N48
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout = ( !\u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & (((!\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout )) # (\u0|clock_sel|data_out [0] &
// ((\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout )))))) # (\u0|clock_sel|data_out [2] & ((((\u0|clock_sel|data_out [0]))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\u0|clock_sel|data_out [2] & ((!\u0|clock_sel|data_out [0] &
// (((\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout )))) # (\u0|clock_sel|data_out [0] & (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout )))) # (\u0|clock_sel|data_out [2] & ((((\u0|clock_sel|data_out [0]))))) ) )
.dataa(!\u0|clock_sel|data_out [2]),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ),
.datad(!\u0|clock_sel|data_out [0]),
.datae(!\u0|clock_sel|data_out [1]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ),
.datag(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 .lut_mask = 64'h0A550A770AFF0A77;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~4 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N18
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (
// \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout & ( ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter [5]))) #
// (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) ) ) ) # ( \R_400_to_2_5_10_100_200_300MHZ|counter [6] & ( !\R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter [6] & (
// !\R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter [5]),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter [6]),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 .lut_mask = 64'hFFFFFFFFFDFFFFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N15
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ) # ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ) #
// ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # (!\R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout )) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datac(gnd),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ),
.datae(gnd),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 .lut_mask = 64'hFFEEFFEEFFFFFFFF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N54
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout = ( \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout & ( (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ) #
// ((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout & ( \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout & (
// (!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ) # (((!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout )) # (\R_400_to_2_5_10_100_200_300MHZ|counter [2])) ) ) ) # (
// \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout & ( !\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter [2]),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout ),
.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 .lut_mask = 64'hFFFFFFFFFFBFFFAF;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X15_Y12_N36
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout = ( !\u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout & (((\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout & ((\u0|clock_sel|data_out [2])))))) #
// (\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout & ((((!\u0|clock_sel|data_out [2]) # (\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ))))) ) ) # ( \u0|clock_sel|data_out [1] & ( (!\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout &
// (((\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout & ((\u0|clock_sel|data_out [2])))))) # (\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout & ((((!\u0|clock_sel|data_out [2]))) # (\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ))) ) )
.dataa(!\R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ),
.datab(!\R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ),
.datac(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ),
.datad(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ),
.datae(!\u0|clock_sel|data_out [1]),
.dataf(!\u0|clock_sel|data_out [2]),
.datag(!\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 .extended_lut = "on";
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 .lut_mask = 64'h555555550A5F1B1B;
defparam \R_400_to_2_5_10_100_200_300MHZ|Mux0~0 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y10_N42
cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 (
// Equation(s):
// \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ) )
.dataa(gnd),
.datab(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),
.datac(gnd),
.datad(gnd),
.datae(!\R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ),
.dataf(gnd),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 .extended_lut = "off";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 .lut_mask = 64'h0000333300003333;
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X30_Y10_N44
dffeas \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i (
.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),
.d(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ),
.asdata(vcc),
.clrn(vcc),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.prn(vcc));
// synopsys translate_off
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i .is_wysiwyg = "true";
defparam \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i .power_up = "low";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N18
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_e~2 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_e~2_combout = ( \A_SPW_TOP|SPW|TX|tx_dout~6_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_e~q & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & !\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout )) ) ) ) #
// ( !\A_SPW_TOP|SPW|TX|tx_dout~6_combout & ( \A_SPW_TOP|SPW|TX|tx_dout_e~q & ( (!\A_SPW_TOP|SPW|TX|Selector4~2_combout & (!\A_SPW_TOP|SPW|TX|Selector5~3_combout & ((!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout )))) # (\A_SPW_TOP|SPW|TX|Selector4~2_combout &
// (((!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout )))) ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~6_combout & ( !\A_SPW_TOP|SPW|TX|tx_dout_e~q & ( (\A_SPW_TOP|SPW|TX|Selector4~2_combout & !\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout ) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|Selector4~2_combout ),
.datab(!\A_SPW_TOP|SPW|TX|Selector5~3_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_null~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|tx_dout~6_combout ),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~2 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~2 .lut_mask = 64'h50500000D8508800;
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~2 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X30_Y12_N30
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_e~1 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_e~1_combout = ( !\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q & ( !\A_SPW_TOP|SPW|TX|Selector4~0_combout & ( (!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & (((\A_SPW_TOP|SPW|TX|Selector5~0_combout )) #
// (\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ))) # (\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q & (((\A_SPW_TOP|SPW|TX|always7~4_combout )))) ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ),
.datab(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ),
.datac(!\A_SPW_TOP|SPW|TX|always7~4_combout ),
.datad(!\A_SPW_TOP|SPW|TX|Selector5~0_combout ),
.datae(!\A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ),
.dataf(!\A_SPW_TOP|SPW|TX|Selector4~0_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_e~1_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~1 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~1 .lut_mask = 64'h47CF000000000000;
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~1 .shared_arith = "off";
// synopsys translate_on
// Location: LABCELL_X31_Y11_N42
cyclonev_lcell_comb \A_SPW_TOP|SPW|TX|tx_dout_e~3 (
// Equation(s):
// \A_SPW_TOP|SPW|TX|tx_dout_e~3_combout = ( \A_SPW_TOP|SPW|TX|tx_dout~4_combout & ( ((\A_SPW_TOP|SPW|TX|tx_dout~9_combout & \A_SPW_TOP|SPW|TX|tx_dout_e~1_combout )) # (\A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ) ) ) # ( !\A_SPW_TOP|SPW|TX|tx_dout~4_combout
// & ( ((\A_SPW_TOP|SPW|TX|tx_dout_e~1_combout & ((\A_SPW_TOP|SPW|TX|tx_dout~9_combout ) # (\A_SPW_TOP|SPW|TX|tx_dout~5_combout )))) # (\A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ) ) )
.dataa(!\A_SPW_TOP|SPW|TX|tx_dout~5_combout ),
.datab(!\A_SPW_TOP|SPW|TX|tx_dout~9_combout ),
.datac(!\A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ),
.datad(!\A_SPW_TOP|SPW|TX|tx_dout_e~1_combout ),
.datae(gnd),
.dataf(!\A_SPW_TOP|SPW|TX|tx_dout~4_combout ),
.datag(gnd),
.cin(gnd),
.sharein(gnd),
.combout(\A_SPW_TOP|SPW|TX|tx_dout_e~3_combout ),
.sumout(),
.cout(),
.shareout());
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~3 .extended_lut = "off";
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~3 .lut_mask = 64'h0F7F0F7F0F3F0F3F;
defparam \A_SPW_TOP|SPW|TX|tx_dout_e~3 .shared_arith = "off";
// synopsys translate_on
// Location: FF_X31_Y11_N44
dffeas \A_SPW_TOP|SPW|TX|tx_dout_e (
.clk(\R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ),
.d(\A_SPW_TOP|SPW|TX|tx_dout_e~3_combout ),
.asdata(vcc),
.clrn(\A_SPW_TOP|SPW|FSM|enable_tx~q ),
.aload(gnd),
.sclr(gnd),
.sload(gnd),
.ena(vcc),
.devclrn(devclrn),
.devpor(devpor),
.q(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),
.prn(vcc));
// synopsys translate_off
defparam \A_SPW_TOP|SPW|TX|tx_dout_e .is_wysiwyg = "true";
defparam \A_SPW_TOP|SPW|TX|tx_dout_e .power_up = "low";
// synopsys translate_on
// Location: HPSINTERFACEDBGAPB_X32_Y53_N111
cyclonev_hps_interface_dbg_apb \u0|hps_0|fpga_interfaces|debug_apb (
.p_slv_err(gnd),
.p_ready(gnd),
.p_clk(gnd),
.p_clk_en(gnd),
.dbg_apb_disable(gnd),
.p_rdata(32'b00000000000000000000000000000000),
.p_addr_31(\u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ),
.p_write(),
.p_sel(),
.p_enable(),
.p_reset_n(),
.p_addr(),
.p_wdata());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|debug_apb .dummy_param = 256;
// synopsys translate_on
// Location: HPSINTERFACETPIUTRACE_X32_Y18_N111
cyclonev_hps_interface_tpiu_trace \u0|hps_0|fpga_interfaces|tpiu (
.traceclk_ctl(vcc),
.traceclkin(gnd),
.traceclk(),
.trace_data(\u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ));
// Location: HPSINTERFACEBOOTFROMFPGA_X32_Y46_N111
cyclonev_hps_interface_boot_from_fpga \u0|hps_0|fpga_interfaces|boot_from_fpga (
.boot_from_fpga_on_failure(gnd),
.boot_from_fpga_ready(gnd),
.bsel_en(gnd),
.csel_en(gnd),
.bsel({gnd,gnd,vcc}),
.csel({gnd,vcc}),
.fake_dout(\u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ));
// Location: HPSINTERFACEFPGA2HPS_X32_Y23_N111
cyclonev_hps_interface_fpga2hps \u0|hps_0|fpga_interfaces|fpga2hps (
.arvalid(gnd),
.awvalid(gnd),
.bready(gnd),
.clk(gnd),
.rready(gnd),
.wlast(gnd),
.wvalid(gnd),
.araddr(32'b00000000000000000000000000000000),
.arburst(2'b00),
.arcache(4'b0000),
.arid(8'b00000000),
.arlen(4'b0000),
.arlock(2'b00),
.arprot(3'b000),
.arsize(3'b000),
.aruser(5'b00000),
.awaddr(32'b00000000000000000000000000000000),
.awburst(2'b00),
.awcache(4'b0000),
.awid(8'b00000000),
.awlen(4'b0000),
.awlock(2'b00),
.awprot(3'b000),
.awsize(3'b000),
.awuser(5'b00000),
.port_size_config({vcc,vcc}),
.wdata(128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.wid(8'b00000000),
.wstrb(16'b0000000000000000),
.arready(\u0|hps_0|fpga_interfaces|fpga2hps~arready ),
.awready(),
.bvalid(),
.rlast(),
.rvalid(),
.wready(),
.bid(),
.bresp(),
.rdata(),
.rid(),
.rresp());
// synopsys translate_off
defparam \u0|hps_0|fpga_interfaces|fpga2hps .data_width = 32;
// synopsys translate_on
// Location: HPSINTERFACEFPGA2SDRAM_X32_Y27_N111
cyclonev_hps_interface_fpga2sdram \u0|hps_0|fpga_interfaces|f2sdram (
.cmd_port_clk_0(gnd),
.cmd_port_clk_1(gnd),
.cmd_port_clk_2(gnd),
.cmd_port_clk_3(gnd),
.cmd_port_clk_4(gnd),
.cmd_port_clk_5(gnd),
.cmd_valid_0(gnd),
.cmd_valid_1(gnd),
.cmd_valid_2(gnd),
.cmd_valid_3(gnd),
.cmd_valid_4(gnd),
.cmd_valid_5(gnd),
.rd_clk_0(gnd),
.rd_clk_1(gnd),
.rd_clk_2(gnd),
.rd_clk_3(gnd),
.rd_ready_0(gnd),
.rd_ready_1(gnd),
.rd_ready_2(gnd),
.rd_ready_3(gnd),
.wr_clk_0(gnd),
.wr_clk_1(gnd),
.wr_clk_2(gnd),
.wr_clk_3(gnd),
.wr_valid_0(gnd),
.wr_valid_1(gnd),
.wr_valid_2(gnd),
.wr_valid_3(gnd),
.wrack_ready_0(gnd),
.wrack_ready_1(gnd),
.wrack_ready_2(gnd),
.wrack_ready_3(gnd),
.wrack_ready_4(gnd),
.wrack_ready_5(gnd),
.cfg_axi_mm_select({gnd,gnd,gnd,gnd,gnd,gnd}),
.cfg_cport_rfifo_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
.cfg_cport_type({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
.cfg_cport_wfifo_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
.cfg_port_width({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
.cfg_rfifo_cport_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
.cfg_wfifo_cport_map({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
.cmd_data_0(60'b000000000000000000000000000000000000000000000000000000000000),
.cmd_data_1(60'b000000000000000000000000000000000000000000000000000000000000),
.cmd_data_2(60'b000000000000000000000000000000000000000000000000000000000000),
.cmd_data_3(60'b000000000000000000000000000000000000000000000000000000000000),
.cmd_data_4(60'b000000000000000000000000000000000000000000000000000000000000),
.cmd_data_5(60'b000000000000000000000000000000000000000000000000000000000000),
.wr_data_0(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.wr_data_1(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.wr_data_2(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.wr_data_3(90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
.cmd_ready_0(),
.cmd_ready_1(),
.cmd_ready_2(),
.cmd_ready_3(),
.cmd_ready_4(),
.cmd_ready_5(),
.rd_valid_0(),
.rd_valid_1(),
.rd_valid_2(),
.rd_valid_3(),
.wr_ready_0(),
.wr_ready_1(),
.wr_ready_2(),
.wr_ready_3(),
.wrack_valid_0(),
.wrack_valid_1(),
.wrack_valid_2(),
.wrack_valid_3(),
.wrack_valid_4(),
.wrack_valid_5(),
.bonding_out_1(\u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ),
.bonding_out_2(),
.rd_data_0(),
.rd_data_1(),
.rd_data_2(),
.rd_data_3(),
.wrack_data_0(),
.wrack_data_1(),
.wrack_data_2(),
.wrack_data_3(),
.wrack_data_4(),
.wrack_data_5());
// Location: IOIBUF_X46_Y0_N35
cyclonev_io_ibuf \KEY[0]~input (
.i(KEY[0]),
.ibar(gnd),
.dynamicterminationcontrol(gnd),
.o(\KEY[0]~input_o ));
// synopsys translate_off
defparam \KEY[0]~input .bus_hold = "false";
defparam \KEY[0]~input .simulate_z_as = "z";
// synopsys translate_on
altera_pll_reconfig_tasks pll_reconfig_inst_tasks();
// synopsys translate_off
defparam pll_reconfig_inst_tasks .number_of_fplls = 1;
// synopsys translate_on
endmodule
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